Parameters in FinFET Gate Tunneling Current Model

Transmission probability calculation is the most important part in this physical model. According to (2-24), 𝑚𝐼𝐿, 𝑚ℎ𝑖𝑔ℎ−𝐾, 𝜙𝐼𝐿,𝑎𝑛, 𝜙𝐼𝐿,𝑐𝑎𝑡ℎ, 𝜙ℎ𝑖𝑔ℎ−𝐾,𝑎𝑛, 𝜙ℎ𝑖𝑔ℎ−𝐾,𝑐𝑎𝑡ℎ and 𝐹_𝐼𝐿, 𝐹_{ℎ𝑖𝑔ℎ−𝐾} are essential for resolving this equation. How to find the tunneling effective masses in interfacial layer (𝑚𝐼𝐿) and high-K layer (𝑚ℎ𝑖𝑔ℎ−𝐾) will be explained later. In order to obtain 𝜙_{𝐼𝐿,𝑎𝑛}, 𝜙_{𝐼𝐿,𝑐𝑎𝑡ℎ}, 𝜙_{ℎ𝑖𝑔ℎ−𝐾,𝑎𝑛} and 𝜙ℎ𝑖𝑔ℎ−𝐾,𝑐𝑎𝑡ℎ, 𝜙_𝐼𝐿 and 𝜙ℎ𝑖𝑔ℎ−𝐾 are the two parameters used in the equations from (2-18) to (2-21). The electric field in interfacial layer (𝐹_𝐼𝐿) and high-K dielectric (𝐹_{ℎ𝑖𝑔ℎ−𝐾}) are defined in (2-22) and (2-23).

According to [8],[9], a method of extracting gate material parameters has been proposed, as long as gate current is dominated by direct tunneling or Fowler-Nordheim tunneling (F-N tunneling) from the plot of dlnIg/dVg versus Vg (Fig. 14). The transition of direct tunneling and F-N tunneling across high-K has a peak of dlnIg/dVg, and as a consequence, the position of the peak over can provide a direct estimate of metal work function and high-K electron affinity. From Fig. 14(b) and Fig. 14(c), 𝜙_{ℎ𝑖𝑔ℎ−𝐾} determines the peak position; 𝑚_{ℎ𝑖𝑔ℎ−𝐾} determines the peak height. So, adjusting 𝜙ℎ𝑖𝑔ℎ−𝐾 can shift the fitting curve of dlnIg/dVg versus Vg until the position of the peak is the same as the experimental value. Then, adjusting 𝑚ℎ𝑖𝑔ℎ−𝐾 can change the height of dlnIg/dVg peak until it approaches the experimental value. The parameters related to high-K are determined from the above method. Then, band offset with respect to silicon and the tunneling effective mass in interfacial layer, 𝜙_𝐼𝐿 and 𝑚_𝐼𝐿, can be extracted by fitting gate current versus gate voltage. Higher 𝜙𝐼𝐿 decreases the gate current because the electric barrier height can

𝜙

need more energy to tunnel across the interfacial layer, leading to gate tunneling current drop. Higher 𝑚_𝐼𝐿 also decreases the gate current because the electric effective mass can significantly affect the tunneling probability as shown in equation (2-24). The differential value of the band offset between the anode side and cathode side is negative. It means that the higher the effective mass is, the less likely the tunneling occurs. We can therefore extract the relevant HKMG material parameters by combining conventional Cg-Vg and Ig-Vg curve fittings with the new dlnIg/dVg-Vg curve fitting.

Chapter 4

Metal-Gate/High-K FinFET: Experiment and Fitting

The experimental devices were n-type FinFET with metal-gate/high-K/IL system, as schematically depicted in Fig. 3 in terms of energy band diagram in flat-band condition. Because of the small ratio of top gate width to total fin width, we can regard the FinFET structure as double gate structure, as shown in Fig. 5.

The electron tunneling current from inversion layer was measured with source, drain and bulk tied to ground. The measured terminal current is shown in Fig. 15(a).

The case of Vd = 0.05V is shown in Fig. 15(b). The following process parameters were obtained by Cg-Vg fitting using the Schrödinger-Poisson equation solver Schred [10], as depicted in Fig. 16. The results are that the metal work function Φ_𝑚 is 4.6eV, the EOT is 0.8nm, and the p-type substrate doping concentration 𝑁_𝑠𝑢𝑏 is 1×10¹⁸ cm^-3. Then, we took the permittivity of HfO₂ bases high-K (εk) as the literature value of 22 ε0 [11] and to meet EOT (0.8nm), the permittivity of IL (εIL) is determined to be 6.6 ε0. Corresponding band offsets of IL (ϕIL) to silicon conduction and valence band are therefore 2.44 eV [12].

The gate current was measured with source, drain, and bulk tied to the ground. The measured result has been depicted in Fig. 15(a) versus Vg. In the gate current fitting, the actual electron tunneling current is close to the electron tunneling current from the first and second subband. For the purpose of saving the computation time, we just calculate the first and second subband in this work. Many simplifications are employed in our tunneling simulation, but the results are reasonable as compared with experimental results as depicted in Fig. 17. The tunneling model is constructed by

WKB approximation of electron transmission probability through the high-K stacks.

From the fitting result in Fig. 17, the simulation by our model is not correct for the gate bias below threshold voltage. The reason for this failure can be attributed to the fact that the gate current is not dominated by direct tunneling in threshold region but our tunneling current model is limited to pure tunneling. Another drawback is that a serious deviation occurs at high gate voltage. This is due to the very large difference of permittivity between high-K dielectric (22 ε0) and IL (6.6 ε0). Thus, a gradual transition (intermixing) layer between high-K dielectric and IL needs to be considered in the calculation. The tunneling effective masses of transition layer can be assumed to be linear or parabolic type, as schematically plotted in Fig. 18. The current fitting results are shown in Fig. 19. We find that fitting quality can be improved with the transition layer included, especially for the parabolic one. Although the simulator cannot work in subthreshold region, WKB approximation still show good agreements with the experimental curve even when the gate bias is large enough. The following discussion focuses on the range of the current closely falling the range of gate bias larger than the threshold voltage.

Now, all the model parameters are known, except 𝜙ℎ𝑖𝑔ℎ−𝐾, 𝑚𝐼𝐿 and 𝑚ℎ𝑖𝑔ℎ−𝐾. In order to find the parameters related to high-K dielectric, dlnIg/dVg fitting is used again. As mentioned in Chapter 3.3, 𝜙ℎ𝑖𝑔ℎ−𝐾 and 𝑚ℎ𝑖𝑔ℎ−𝐾 dominate the position of the peak and the height of the peak in the dlnIg/dVg versus Vg, respectively. 𝜙_{ℎ𝑖𝑔ℎ−𝐾} is adjusted first until the position of the dlnIg/dVg peak approaches the experimental data (～1.5V). Next, 𝑚ℎ𝑖𝑔ℎ−𝐾 is changed until the height of the dlnIg/dVg peak closely meets the experimental data (～7V^-1). The fitting result is shown in Fig. 20 and the extracted results are 𝜙_{ℎ𝑖𝑔ℎ−𝐾} = 1.07 𝑒𝑉 and 𝑚_{ℎ𝑖𝑔ℎ−𝐾}= 0.02𝑚₀.

fitting. The experimental and fitting gate current without transition layer are plotted in Fig. 17 and Fig. 19 with linear and parabolic transition layer. In the Ig-Vg fitting, the gate current does not change by adjusting the value of 𝜙ℎ𝑖𝑔ℎ−𝐾 or 𝑚ℎ𝑖𝑔ℎ−𝐾 in case 3 (only direct tunneling through the IL). No matter how the high-K dielectric parameters change, gate tunneling current is not affected at high gate voltage.

Chapter 5 Conclusion

FinFET gate current model has been established by modifying the gate current model for metal-gate/high-K device. Because of the small ratio between top width and the whole width, double gate tunneling current model can be applied to FinFET. A compact model for the structure that is similar to double gate devices has been established.

As the width of FinFET is insignificant compared to the whole gate length, the fitting factor of electron subband energy has regularity in the region of body thickness between 10nm and 50nm. When the body thickness is fixed in double gate structure, the fitting factor does not need to adjust. The model can straightforwardly yield the correct subband energy. For the case of varying body thickness, we can obtain a reasonable fitting factor from the linear relationship. Conventionally, Ig-Vg and Cg-Vg curve fittings are used to extract the parameters. Because of the apparent deviation of gate current fitting at high voltage, transition layer between the high-K dielectric and the interfacial layer is incorporated. Linear and parabolic-type transition layer are adopted in the model. By taking into account the transition layer, the gate tunneling current fitting and dlnIg/dVg fitting can be significantly improved. It is found that parabolic transition layer can produce a better agreement with experiment than linear transition layer.

A peak of dlnIg/dVg indicates a transition of direct tunneling and F-N tunneling across a high-K part, and as a consequence, the position of the dlnIg/dVg peak over Vg can provide a direct estimate of the parameters in high-K. To accurately extract

systematically constructed a new fitting scheme over the dlnIg/dVg versus Vg curve, along with the combination of Cg-Vg and Ig-Vg fittings. In addition, we have demonstrated that the conventional method without the dlnIg/dVg fitting might lead to erroneous results, Thus, the dlnIg/dVg fitting should be taken into account in the assessment of the metal-gate high-K material parameters in FinFET devices.

References

[ 1 ] Amitava DasGupta, “Multiple Gate MOSFETs: The Road to Future,” in

Proceedings of the 2007 International Workshop on the Physics of Semiconductor Devices (IWPSD), pp. 96-101, Sep. 2007.

[ 2 ] Leonard F. Register, Elyse Rosenbaum, and Kevin Yang, “Analytic model for direct tunneling current in polycrystalline silicon-gate metal-oxide-semi- conductor devices,” Appl. Phys. Lett., vol. 74, no. 3, pp. 457-459, Jan. 1999.

[ 3 ] Kuo-Nan Yang, Huan-Tsung Huang, Ming-Chin Chang, Che-Min Chu, Yuh-Shu Chen, Ming-Jer Chen, Yeou-Ming Lin, Mo-Chiun Yu, Simon M. Jang, Douglas C. H. Yu, and M. S. Liang, “A physical model for hole direct tunneling current in p+ poly-gate PMOSFETs with ultrathin gate oxides,” IEEE Trans. Electron

Devices, vol. 47, no. 11, pp. 2161-2166, Nov. 2000.

[ 4 ] Yijie Zhao and Marvin H. White, “Modeling of direct tunneling current through interfacial oxideand high-K gate stacks,” Solid-State Electronics, vol.48, no.

10-11, pp. 1801-1807, Dec. 2003.

[ 5 ] Saibal Mukhopadhyay, Keunwoo Kim, Ching Te Chuang, and Kaushik Roy,

“Modeling and Analysis of Leakage Currents in Double-Gate Technologies,”

IEEE Trans. Computer–Aided Design of Integrated Circuits and Systems, vol. 25,

no. 10, pp. 2052-2061, Oct. 2006.

[ 6 ] Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rjiv V.

Joshi, Ching-Te Chuang, and Kaushik Roy, “Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50 nm double gate devices,”

Microelectronics Journal, vol. 38, no. 8-9, pp. 931-941, Jan. 2006.

[ 7 ] Leland Chang, Kevin J. Yang, Yee-Chia Yeo, Igor Polishchuk, Tsu-Jae King, and Chenming Hu, “Direct-Tunneling Gate Leakage Current in Double-Gate and Ultrathin Body MOSFETs,” IEEE Trans. Electron Devices, vol. 49, no. 12, pp.

2288-2295, Dec. 2002.

[ 8 ] Sufi Zafar, Cyril Cabral, Jr., R. Amos, and A. Callegari, “A method for measuring barrier heights, metal work functions and fixed charge densities in metal/SiO₂/Si capacitors,” Appl. Phys. Lett., vol. 80, no. 25, pp. 4858-4860, Jun.

2002.

[ 9 ] Chih-Yu Hsu, Hua-Gang Chang, and Ming-Jer Chen, “A Method of Extracting Metal-Gate High-k Material Parameters Featuring Electron Gate Tunneling Current Transition,” IEEE Trans. Electron Devices, vol. 58, no. 4, pp. 953-959, Apr. 2011.

[ 10 ] Schred. [Online]. Available: http://nanohub.org/resources/schred

[ 11 ] Y. T. Hou, M. F. Li, H. Y. Yu, and D. L. Kwong, “Modeling of tunneling currents through HfO₂ and (HfO₂)_x(Al₂O₃)_1-x gate stacks,” IEEE Electron

Device Lett., vol. 24, no. 2, pp. 96-98, Feb. 2003.

[ 12 ] Hongyu Yu, Yong-Tian Hou, Ming-Fu Li, and

Dim-Lee Kwong

, “Investigation of Hole Tunneling Current Through Ultrathin Oxynitride/Oxide Stack Gate Dielectrics for p-MOSFETs,” IEEE Trans. Electron Devices, vol. 49, no. 7, pp.

1158-1164, Jul. 2002.

Fig. 1 Schematic of energy band diagram of the n⁺ poly-gate/SiO₂/p-Si system.

Fig. 2 Tunneling probability illustration.

Fig. 3 Schematic of energy band diagram of the metal-gate/high-K/IL/p-Si system.

Fig. 4 Schematic description of three cases. (a)Case 1: direct tunneling through the two layers. (b)Case 2: F-N tunneling through the high-K stacks. (c)Case 3: direct tunneling through the IL

Fig. 5 Schematic of cross-sectional view of FinFET. FinFET with small fin width is like a double gate structure.

(a)

(b)

Fig. 6 Comparison of the self-consistent Schrödinger-Poisson simulation and analytical model for (a)surface potential and (b)electric field.

0.0 0.5 1.0 1.5 2.0 2.5

1.8 Numerical Simulation (Schred) Analytical Model (TRP)

Gate Voltage V _GS (V)

0.0 0.5 1.0 1.5 2.0 2.5

Gate Voltage V _GS (V)

η

_2-fold

= [0.6715,0.682]

(a)

(b)

Fig. 7-1 The analytically calculated (lines) subband energy versus gate voltage and the comparison with those (symbols) of the self-consistent Schrödinger-Poisson simulation. (a)E(1,1); (b)E(2,1); (c)E(1,2); (d)E(2,2).

0.0 0.5 1.0 1.5 2.0 2.5 1st Subband in 1st Valley

Numerical Simulation (Schred) 2nd Subband in 1st Valley

Numerical Simulation (Schred) Analytical Model (TRP)

S ubba nd E ne rgy ( m e V )

Gate Voltage V

_GS

(V)

t

_body

= 10nm

(c)

(d)

Fig. 7-2 The analytical calculated (lines) subband energy versus gate voltage and the comparison with those (symbols) of the self-consistent Schrödinger-Poisson simulation. (a)E(1,1); (b)E(2,1); (c)E(1,2); (d)E(2,2).

0.0 0.5 1.0 1.5 2.0 2.5 1st Subband in 2nd Valley

Numerical Simulation (Schred)

700 2nd Subband in 2nd Valley

Numerical Simulation (Schred)

Fig. 8 Comparison of gate tunneling current versus gate voltage from the self-consistent Schrödinger-Poisson (symbols) simulation and analytical model (lines).

0.0 0.5 1.0 1.5 2.0 2.5 10

^-12

10

^-10

10

^-8

10

^-6

10

^-4

10

^-2

10

⁰

10

²

10

⁴

10

⁶

EOT=0.84 nm N

_sub

=1x10

¹⁸

cm

^-3 Φ_m

=4.6 eV

G at e C u rr en t (A/ c m 2 )

Vg (V)

Numerical Simulation (Schred)

Analytical Model (TRP)

Fig. 9 The analytically calculated (lines) subband energy versus gate voltage and the comparison with those (symbols) of the self-consistent Schrödinger-Poisson simulation for EOT = 1.21nm, Φm = 4.4 eV, Nsub = 6x10¹⁷ cm^-3, and tbody = 10 nm.

0.0 0.5 1.0 1.5 2.0 2.5

0 200 400 600 800

(110) Surface η

_2-fold

= [0.6715,0.682]

η

_4-fold

= [0.67,0.68]

EOT = 1.21 nm Nsub = 6x10

¹⁷

cm

^-3

Φ m = 4.4 eV

t

_body

= 10nm

S ubba nd E ne rgy ( m e V )

Gate Voltage V

_GS

(V)

Line & Symbol : Numerical Simulation (Schred) E(1,1)

E(2,1)

E(1,2)

E(2,2) Line : Analytical Model (TRP)

E(1,1)

E(2,1) E(1,2)

E(2,2)

(a)

(b)

(c)

Fig. 10-1 The subband energy (best fitting) for different body thicknesses.

0.0 0.5 1.0 1.5 2.0 2.5

Gate Voltage V

_GS

(V)

by best fitting factors

Line & Symbol : Numerical Simulation (Schred) E(1,1) E(2,1)

E(1,2) E(2,2) Line : Analytical Model (TRP)

E(1,1) E(2,1)

Line & Symbol : Numerical Simulation (Schred) E(1,1) E(2,1)

E(1,2) E(2,2) Line : Analytical Model (TRP)

E(1,1) E(2,1) E(1,2) E(2,2)

(110) Surface η_2-fold = [0.6709,0.6802]

η_4-fold = [0.6694,0.6782]

EOT = 0.84 nm

η_4-fold = [0.6688,0.6776]

EOT = 0.84 nm Nsub = 1x10¹⁸ cm^-3 Φm = 4.6 eV

t_body = 30nm by best fitting factors

Line & Symbol : Numerical Simulation (Schred) E(1,1) E(2,1)

E(1,2) E(2,2) Line : Analytical Model (TRP)

E(1,1) E(2,1) E(1,2) E(2,2)

S u b b a n d E n e rg y ( m e V )

Gate Voltage V

_GS

(V)

(d)

(e)

Fig. 10-2 The subband energy (best fitting) for different body thicknesses.

(a)tbody=10nm; (b)tbody=20nm; (c)tbody = 30nm; (d)tbody = 40nm; (e)tbody = 50nm.

η

_2-fold

= [0.6697,0.6784]

η

_4-fold

= [0.6685,0.677]

Line & Symbol : Numerical Simulation (Schred) E(1,1)

E(2,1)

E(1,2)

E(2,2) Line : Analytical Model (TRP)

E(1,1)

E(2,1) E(1,2)

E(2,2)

S u b b a n d E n e rg y ( m e V )

Gate Voltage V _GS (V)

0.0 0.5 1.0 1.5 2.0 2.5

η

_2-fold

= [0.6694,0.6781]

η

_4-fold

= [0.6682,0.6767]

EOT = 0.84 nm Nsub = 1x10

¹⁸

cm

^-3

Φ m = 4.6 eV

t

_body

= 50nm

by best fitting factors

Line & Symbol : Numerical Simulation (Schred) E(1,1)

E(2,1)

E(1,2)

E(2,2) Line : Analytical Model (TRP)

E(1,1)

E(2,1) E(1,2)

E(2,2)

S u b b a n d E n e rg y ( m e V )

Gate Voltage V _GS (V)

Fig. 11 Subband fitting factors versus body thickness. Symbols are the values for best fitting and lines are for linear fitting.

10 20 30 40 50

0.666 0.669 0.672 0.675 0.678 0.681 0.684 0.687 0.690 0.693

η =0.67033 − 4.5x10

^-5

xt

_body

η =0.68024 − 7.8x10

^-5

xt

_body

η =0.68242 − 9.6x10

^-5

xt

_body

F it ti n g F a c to r ( j th su bban d , i th val ley )

Body Thickness (nm)

Symbol : Best Fitting Factors

η

(1,1)

η

(2,1)

η

(1,2)

η

(2,2) Line : Linear Fitting Factors

η

(1,1)

η

(2,1)

η

(1,2)

η

(2,2)

EOT = 0.84 nm Nsub = 1x10

¹⁸

cm

^-3

Φm = 4.6 eV

η =0.67198 − 5.4x10

^-5

xt

_body

(110) Surface

(a)

(b)

(c)

Fig. 12-1 The case of subband energy (linear relationship) for different body thicknesses. (a)tbody=10nm; (b)tbody=20nm; (c)tbody = 30nm; (d)tbody = 40nm; (e)tbody =

η_2-fold = [0.67144,0.68146]

η_4-fold = [0.67028,0.67946]

EOT = 0.84 nm Nsub = 1x10¹⁸ cm^-3 Φm = 4.6 eV

Energy Band (meV)

Gate Voltage V_GS(V) by linear fitting factors

Line & Symbol : Numerical Simulation (Schred) E(1,1) E(2,1)

E(1,2) E(2,2) Line : Analytical Model (TRP)

E(1,1) E(2,1) η_2-fold = [0.6709,0.6805]

η_4-fold = [0.66943,0.67868]

EOT = 0.84 nm Nsub = 1x10¹⁸ cm^-3 Φm = 4.6 eV

t_body = 20nm

Energy Band (meV)

Gate Voltage V_GS(V) by linear fitting factors

Line & Symbol : Numerical Simulation (Schred) E(1,1) E(2,1)

E(1,2) E(2,2) Line : Analytical Model (TRP)

E(1,1) E(2,1) η_2-fold = [0.67036,0.67954]

η_4-fold = [0.66898,0.6779]

EOT = 0.84 nm Nsub = 1x10¹⁸ cm^-3 Φm = 4.6 eV

t_body = 30nm

Energy Band (meV)

Gate Voltage V_GS(V) by linear fitting factors

Line & Symbol : Numerical Simulation (Schred) E(1,1) E(2,1)

E(1,2) E(2,2) Line : Analytical Model (TRP)

E(1,1) E(2,1) E(1,2) E(2,2)

(d)

(e)

Fig.12-2 The case of subband energy (linear relationship) for different body thicknesses. (a)tbody=10nm; (b)tbody=20nm; (c)tbody = 30nm; (d)tbody = 40nm; (e)tbody =

η

_2-fold

= [0.66982,0.67858]

η

_4-fold

= [0.66853,0.67712]

EOT = 0.84 nm Nsub = 1x10

¹⁸

cm

^-3

Φ m = 4.6 eV

t

_body

= 40nm

E ne rgy B a nd ( m e V )

Gate Voltage V

_GS

(V)

by linear fitting factors

Line & Symbol : Numerical Simulation (Schred) E(1,1) E(2,1)

E(1,2) E(2,2) Line : Analytical Model (TRP)

E(1,1) E(2,1)

η

_2-fold

= [0.66928,0.67762]

η

_4-fold

= [0.66808,0.67634]

EOT = 0.84 nm Nsub = 1x10

¹⁸

cm

^-3

Φ m = 4.6 eV

t

_body

= 50nm

E ne rgy B a nd ( m e V )

Gate Voltage V

_GS

(V)

by linear fitting factors

Line & Symbol : Numerical Simulation (Schred) E(1,1) E(2,1)

E(1,2) E(2,2) Line : Analytical Model (TRP)

E(1,1) E(2,1)

E(1,2) E(2,2)

(a)

(b)

Fig. 13 (a) Comparison of Ig(linear factors) with Ig(best factors) for tbody=10nm and tbody=30nm. (b) Gate current change by linear and best factors.

0.0 0.5 1.0 1.5 2.0 2.5

(Ig (η

Linear Fit

)- Ig (η

Best Fit

)) /Ig (η

Best Fit

) ( %)

Body Thickness (nm)

Vg = 1.6V

(a)

(b)

(c)

Fig. 14 (a) The demonstration of three different tunneling regions. And Ig and

1.0 1.5 2.0 2.5 3.0 3.5

(a)

(b)

Fig. 15 The measured terminal current versus gate voltage for nFinFET. (a) terminal current with source, drain and bulk tied to ground and (b) terminal current at Vd = 0.05 V.

Fig. 16 Experimental (symbol) and simulated (line) Cg versus Vg for n-type FinFET. The extracted process parameters are EOT = 0.8 nm, Φm = 4.6 eV and Nsub = 1×10¹⁸ cm^-3

0.0 0.5 1.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

metal-gate/high-K/IL/p-Si

Φ _m =4.6eV EOT=0.8nm N _sub =1x10 ¹⁸ /cm ³

C ap aci tan ce ( µF /c m 2 )

Vg (V)

Measured from FinFET Device

Simulation by Schred (Double Gate)

Fig. 17 Comparison of experimental (symbols) electron gate current with calculated (lines) results. Fitting parameters are ϕk = 1.07 eV, mk = 0.02 mo, mIL = 1.22 mo, tk = 1.2 nm, and tIL = 1 nm.

0.0 0.5 1.0 1.5 2.0 2.5 10

^-4

10

^-2

10

⁰

10

²

10

⁴

EOT=0.8 nm

G at e C u rr en t (A/ c m 2 )

Vg (V)

Measured

Calculated without transition layer

(a)

(b)

Fig. 18 Schematic of the energy band diagram for (a) a linear gradual transition layer and (b) a parabolic gradual transition layer.

(a)

(b)

Fig. 19 Comparison of experimental (symbols) electron gate current with calculated (lines) results in the presence of a transition layer. (a) Linear gradual transition layer, ϕk = 1.07 eV, mk = 0.02 mo, mIL = 0.8 mo, tk = 0.3nm , tmix = 1.31 nm,

Calculated with linear transition layer

0.0 0.5 1.0 1.5 2.0 2.5

Calculated with parabolic transition layer

Fig. 20 Comparison of experimental (symbols) dlnIg/dVg versus Vg with calculated (lines) results in the presence of a transition layer. The fitting parameters are: (I)for no transition layer, mk = 0.02 m0, mIL = 1.22 m0, tk = 1.2 nm, and tIL = 1 nm; (II) for linear transition layer, mk = 0.02 m0, mIL = 0.8 m0, tk = 0.3 nm, tmix = 1.31 nm, and tIL

= 0.6 nm; (III) for linear transition layer, mk = 0.02 m0, mIL = 1.39 m0, tk = 0.4 nm, tmix = 1 nm, and tIL = 0.59 nm

1.0 1.5 2.0 2.5

4 6 8 10 12 14

∆L n (J g )/ ∆V g ( V

-1

)

Vg (V)

Measured

Calculated without transition layer Calculated with linear transition layer Calculated with parabolic transition layer

N

_sub

=1x10

¹⁸

/cm

³ Φ_m

=4.6 eV , Φ

_IL

=2.44 eV

EOT=0.8 nm

在文檔中 金屬閘高介電n型金氧半場效電晶體及鰭式電晶體閘極電子穿隧電流的精確模擬 (頁 27-59)