Chapter 1 Introduction
1.2 Arrangement of this thesis
Different models trying to explain RTS amplitude have been proposed [3], [10]-[11], although the physical grounds of RTS phenomenon are not fully understood yet. Hence, building a new physical model of RTS is the major purpose of this thesis. Before building the model, we have to simulate RTS phenomenon of device by TCAD to observe its characteristics. The organization of this thesis is described below.
First, a brief introduction to the RTS was described in Chapter 1.
There are two parts in Chapter 2: in Section 2.1, we showed our high-k metal gate device in terms of key parameters and RTS experimental data in this work; in Section 2.2, we built a MOSFET structure by TCAD simulation with certain parameters, and discussed RTS effect by changing the parameters. The parameters involved can be divided into three primary parts: gate size, trap size, and trap position. By comparing the variation of drain/source current with different parameters, the trend of drain/source current variation changing with each parameter could be obtained and it is shown in Chapter 3. The effect of gate size and trap size is introduced in Section 3.1, and the effect of trap position is introduced in Section 3.2.
3
Second, in Chapter 4, we started trying to build a model for RTS data fitting. After getting and analyzing the result, we assumed that in the same gate bias, the measured relative magnitude ΔId/Id would only relate to gate width ( II WLt
d
d
) instead of both gate width and gate length
( II WLLt
d d
2
) when it is in subthreshold region, and we proved it by two different methods in Section 4.1. In Section 4.2, based on the simulated result, we combined the two models to constitute a new one via Boltzmann function so that there are two distinct characteristics in a new model in terms of II WLt
d
d
in subthreshold region and II WLLt
d d
2
in
strong inversion region. In Section 4.3, we made use of the new model to our experimental data to confirm the validity and applicability of the model. Finally, we summarized the conclusion of this work in Chapter 5.
4
Chapter 2 Device under Test
2.1 Experimental Device
The device under study was an n-channel MOSFET with a high-k metal gate stack. The key parameters were obtained by capacitance-voltage fitting: metal work function ψ m of 4.4V, effective oxide thickness EOT of 1.1nm, and body doping concentration Nsub of 4×1018cm-3. A semiconductor parameter analyzer HP4156 was utilized with the source and bulk tied to the ground and the drain connected to a bias Vd of 50mV. The measurement temperature was 300K. The probability of finding RTS events across the whole wafer was very low.
Only a few devices were eventually identified with two-level RTS, as displayed in Fig. 1. The same RTS events in the drain current also simultaneously occurred in the source current. No noticeable change in the gate current has detected, meaning that the trap responsible for the RTS is an atomic-sized trap relative to the 1.1nm gate oxide used. This trap should be naturally created during the manufacturing process instead of the electrical stressing in the long-term RTS measurement.
To get ΔId/Id, we analyzed the RTS experimental data in terms of the frequence count. Frequence count is an analysis method which divides RTS data into few intervals and counts how many data points are there in each interval. After that, we fitted the data points by a normal distribution,
5
and we would get two fitting peaks which are two normal distribution curves. By calculating the expectation value of the two curves, high and low level of the RTS data could be obtained, and ΔId could be derived by subtracting low level from high level. Fig. 2 shows Id - Vg curve and ΔId/Id
curve, respectively.
2.2 Simulation Device
The structure built by TCAD, as displayed in Fig. 3, was an n-channel MOSFET with the following key parameters: body doping concentration Nsub of 2×1018cm-3, drain/source doping concentration Nds
of 1×1020cm-3, n+ polysilicon doping concentration Npoly of 1×1020cm-3, and gate oxide thickness tox of 2nm.
To simulate the effect caused by a trap, we built an isolated polysilicon rectangular window in the center of gate poly and gave it another bias Vg2 differing from gate bias Vg. In contrast with setting a fixed charge into gate oxide, building an isolated polysilicon block into gate poly is easier to control and observe the effect range caused by trap.
In this work, we set Vg2 = -1V, Vd = 0.05V, and set Vg scanning from 0V to 1.2V with the interval of 0.1V.
In this work, we utilized TCAD to build the MOSFETs structure with a trap, and simulated RTS events in the structure to observe the effect of RTS. We discussed RTS effect in some aspects: (1) Changing gate width of devices to simulate Id - Vg curves affected by RTS for
6
different gate widths; (2) Changing gate length of devices to simulate Id - Vg curves affected by RTS for different gate lengths; (3) Changing trap size (Lt) to simulate different apparent Debye lengths; and (4) Changing trap position to simulate the effect of varying trap position.
Because we could not simulate dynamic trapping-detrapping process in TCAD, structures with a trap and without trap were built in each size to simulate static trapping and detrapping conditions respectively.
Therefore, ΔId/Id could be obtained by Fig. 6, and Fig. 7 reveal comparisons of ΔId/Id curves among the devices of different sizes. The data will be deeply analyzed in Chapter 3.
7
Chapter 3 Factors of RTS
As mentioned in Section 2.2, we built an isolated polysilicon rectangular window in the gate poly to simulate trap. Here, Lt is defined as the width and length of the rectangular window. Lt is set to simulate apparent Debye length that is the distance over which carriers screen out electric fields [12]. Generally, the relative amplitude ΔId/Id is considered as a ratio of the trap induced cored-out area Lt
2 to the gate area so that ΔId/Id of RTS can be expressed by a screened Debye length model [11].
Therefore, ΔId/Id as a critical factor of RTS will be focused in this thesis.
3.1 Device Gate Size and Trap Size versus RTS
To observe Id - Vg and ΔId/Id curves affected by RTS for different gate widths and lengths, we changed device size in TCAD simulation. In this work, we simulated different devices with gate width W = 500, 100, and 60nm; gate length L = 500, 100, and 60nm; trap size Lt = 10, 5, and 2nm. Fig. 5, Fig. 6, and Fig. 7 all show the ΔId/Id curves in devices with different gate sizes and different trap sizes.
From the diagrams three different observations can be drawn. First, ΔId/Id is larger when device length is shorter. For physical description, it means RTS events are more obvious in short channel devices. Second, there is a peak in ΔId/Id curve, and when device length is scaled, the peak will become sharper and sharper. The peak lies at about threshold voltage
8
which is the boundary between subthreshold and inversion region. Thus, ΔId/Id decreases due to the extreme increase of Id. Third, for the device with the same width, the slope of ΔId/Id curves in the subthreshold region is also the same. It may act as evidence that ΔId/Id is only related with device width in the subthreshold region.
3.2 Trap Position versus RTS
In Section 3.1, as the general case, trap is set in the center of gate polysilicon, but in the practical experiment, the trap may not locate right in the center of gate. Consequently, in this section we would change trap position for practical cases. To simplify the expression of trap position, we built a coordinate system on the gate: (1) Gate width direction is set to x-axis; (2) Gate length direction is set to y-axis where drain side is taken as positive side and source side is taken as negative side; and (3) The center of gate is set to the origin (0,0). After setting the coordinate system on the gate poly, we normalized it to that x-axis in the interval [1,-1] and y-axis in the interval [1,-1] as well. The pictures with traps at different positions are shown in Fig. 8, and the ΔId/Id curves of different trap positions are shown in Fig. 9 and Fig. 10.
From Fig. 9, we can observe that trap at (0,0) is larger, and trap at (0,1) and (0,-1) is smaller. Besides, though the curves of (0,1) and (0,-1) are about the same, the value of (0,-1) is larger than (0,1). From Fig. 9 and Fig. 10, ΔId/Id change with different trap positions in the width direction. However, ΔId/Id for trap at gate center changes much more than
9
ΔId/Id for trap at gate edge. Such result can be observed not only for different positions in the width directions, but also different positions in the length direction. It may prove that the influenced range of trap is large enough, so when trap position is at gate edge, the range of effect becomes smaller.
Id of trap near source is smaller than trap near drain. From the ΔId/Id
diagram, we can observe that the largest change between ΔId/Id curves is at about Vg = 0.3V. Therefore, electron density distribution along length direction (shown in Fig. 11) was extracted to compare the difference between gate edge of drain side and source side. We can observe that electron density is larger at source side, so trap has a larger effect when it is at source side.
10
Chapter 4
ΔId/IdModeling
From the TCAD simulated ΔId/Id curves, we can observe that the trend of ΔId/Id curves with Vg increasing is not continuously decreasing but increasing in subthreshold region and decreasing afterward. Based on the result, we assumed that there is another fitting model differing from
in subthreshold region. In subthreshold region, the energy band will be extremely sharp under the trap, and it may cause ΔId/Id involving with only the width factor instead of both width and length. Thus, we will apply II WLt
Therefore, we can observe the validity of Lt while verifying the models.
Fig. 13 shows the Lt curves which are obtained from II WLt and channel width (50nm) are also displayed in diagram as minimum and maximum value of Lt. From the diagram, we can observe that Lt obtained
11
cannot be applied to strong inversion case.
Besides, we can observe that Lt curve obtained by II WLLt without trap, as well as Δelectron density curves. For example, to define Lt, we assumed that the length with Δelectron density/electron density(without trap) = 45% is Lt. Fig. 14(b) shows Δelectron density/electron density(without trap) at different Vg. From the intersection of Δelectron
15). The two matching curves in combination with ΔId/Id curve is shown in Fig. 16.
12
By getting Lt from simulated electron density, we see that II WLLt
d and the fitting curve is shown in Fig. 17.
In data fitting case, parameter Vg0 and dV cannot be obtained
13 curve obtained by capacitance-voltage fitting. Therefore formula (4-3) can be applied to this case to extract Lt, and to make a comparison with
14 W
L I
I t
d
d
and II WLLt
d d
2
, the two curves and new model fitting line are
shown in Fig. 19. From the diagram we can observe that II WLLt
d d
2
is
near the new model fitting line at high Vg, and it is not obvious that
W L I
I t
d
d
is near the new model fitting line at low Vg because the experiment ΔId/Id curve in the interval between Vg = 0.46V to Vg = 0.6V is distant from subthreshold region.
15
Chapter 5 Conclusion
ΔId/Id fitting model has been established by analyzing both experimental and simulation data. In this thesis, by finding the RTS events in HKMG device, we built a structure by TCAD simulator to simulate RTS events and discussed about the relationship between various device parameters and RTS. In the over literal, the equation
WL L I
I t
d d
2
was widely applied to the entire ΔId/Id curves for different gate biases. We used TCAD to simulate structures with RTS events and extracted the practical range of trap Lt from electron density distribution while fitting ΔId/Id data. Besides, we have proved that RTS is 1D effect in subthreshold region and 2D effect in strong inversion region. Finally, a new ΔId/Id fitting formula was acquired by the two boundary conditions in this study.
16
References
[1] K. S. Ralls, W. J. Skocpol, L. D. Jackel, R. E. Howard, L. A. Fetter, R.
W. Epworth, and D. M. Tennant, “Discrete resistance switching in submicrometer silicon inversion layers: Individual interface traps and low-frequency (1/f ?) noise,” Phys. Rev. Lett., vol. 52, no. 3, pp.
228-231, Jan. 1984.
[2] K. R. Farmer, C. T. Rogers, and R. A. Buhrman, “Localized-state interactions in metal-oxide-semiconductor tunnel diodes,” Phys. Rev.
Lett., vol. 58, no. 21, pp 2255-2258, May 1987.
[3] M. J. Kirton and M. J. Uren, “Noise in solid-state microstructures: A new perspective on individual defects, interface states and low-frequency (1/f) noise,” Adv. Phys., vol. 38, pp. 367-468, 1989.
[4] M. Schulz, “Coulomb energy of traps in semiconductor space-charge regions,” J. Appl. Phys., vol. 74, no. 4, pp. 2649-2657, Aug. 1993.
[5] H. H. Mueller, D. Wörle, and M. Schulz, “Evaluation of the Coulomb energy for single-electron interface trapping in sub-μm metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 75, no. 6, pp. 2970-2979, Mar. 1994.
[6] M. J. Chen and M. P. Lu, “On-off switching of edge direct tunneling currents in metal-oxide-semiconductor field-effect transistors,” Appl.
Phys. Lett., vol. 81, no. 18, pp. 3488-3490, Oct. 2002.
[7] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors,”
IEEE Trans. Electron Devices, vol. 37, no. 3, pp. 654-665, Mar. 1990.
17
[8] M. J. Chen, T. K. Kang, Y. H. Lee, C. H. Liu, Y. J. Chang, and K. Y.
Fu, “Low-frequency noise in n-channel metal-oxide-semiconductor field-effect transistors undergoing soft breakdown,” J. Appl. Phys., vol. 89, no. 1, pp.648-653, Jan. 2001.
[9] E. Simoen, G. Eneman, P. Verheyen, R. Delhougne, R. Loo, K. De Meyer, and C. Claeys, “On the beneficial impact of tensile-strained silicon substrates on the low-frequency noise of n-channel metal-oxide-semiconductor transistors,” Appl. Phys. Lett., vol. 86, no.
22, 223509, May 2005.
[10] K. K. Hung, P. K. Ko, C. Hu and Y. C. Cheng, “Random telegraph noise of deep-submicrometer MOSFETs,” IEEE Electron Device Lett., vol. 11, no. 2, pp. 90-92, Feb. 1990.
[11] E. Simoen, B. Dierickx, C. L. Claeys, and G. J. Declerck,
“Explaining the amplitude of RTS noise in submicrometer MOSFETs,” IEEE Trans. Electron Devices, vol. 39, no. 2, pp.
422-429, Feb. 1992.
[12] K. Kandiah, M. O. Deighton, and F. B. Whiting, “A physical model for random telegraph signal currents in semiconductor devices,” J.
Appl. Phys., vol. 66, no. 2, pp. 937-948, Jul. 1989.
18
Fig. 1 Time records of the drain, source, and gate currents for W/L = 100/26nm device at Vg = 0.56V, and Vd = 0.05V.
0 1 2 3 4 5
2.0 2.1 2.2 2.3 2.4 2.5
I
d( A)
Time(s)
W/L=100/26nm @ Vg=0.56V, Vd=0.05V
0 1 2 3 4 5
-2.5 -2.4 -2.3 -2.2 -2.1 -2.0
I
s( A)
Time(s)
W/L=100/26nm @ Vg=0.56V, Vd=0.05V
0 1 2 3 4 5
-0.02 -0.01 0.00 0.01 0.02
I
g(nA )
Time(s)
W/L=100/26nm @ Vg=0.56V, Vd=0.05V
19
Fig. 2 The experimental data of Id and ΔId/Id versus Vg for W/L = 100/26nm device.
0.0 0.4 0.8 1.2 1.6 2.0 -5
0 5 10 15 20 25 30 35
I
d( A )
V
g(V) W/L=100/26nm
V
th=0.458V @ V
d=0.05V
0.45 0.50 0.55 0.60 0.07
0.08 0.09 0.10 0.11 0.12 0.13 0.14
I
d/I
dV
g(V)
W/L=100/26nm @ V
d=0.05V
20
Fig. 3 The structure built in TCAD under study with Nsub = 2×1018cm-3, Nds = 1×1020cm-3, Npoly = 1×1020cm-3, and tox = 2nm.
Drain Source
Trap Gate
21
(a)
(b)
Fig. 4 (a) The simulated drain currents (Id) versus gate voltage (Vg) of different sizes in linear scale. (b) The simulated drain currents versus gate voltage of different sizes in log scale.
0.0 0.2 0.4 0.6 0.8 1.0 1.2
22
23
24
25
(a) (b) (c) (d)
(e) (f) (g)
Fig. 8 The trap position presented in normalized form. (a) (0,0); (b) (0,1); (c) (0,-1); (d) (0,0.5); (e) (0,-0.5); (f) (-1,0); and (g) (-0.5,0).
26
Fig. 9 Δ Id/Id curves in device with different trap positions in x-axis direction (width direction).
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.00 0.05 0.10 0.15 0.20 0.25
I
d/I
dV
g(V)
W/L=200/50nm, L
t=10nm
@ V
g2=-1V, V
d=0.05V
trap @ (0,0)
trap @ (0,1)
trap @ (0,-1)
trap @ (0,0.5)
trap @ (0,-0.5)
27 gate edge of source side.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 trap at y-axis position is fixed at gate center trap at y-axis position is fixed at gate edge of drain side trap at y-axis position is fixed at gate edge of source side
trap @ (0,-1) trap @ (-1,-1) trap @ (-0.5,-1)
28
Fig. 11 Electron density distribution along length direction. The region of gate length is in the interval at Y = 200nm to Y = 250nm.
200 210 220 230 240 250
10
1710
1810
19Drain e le c tr o n d e n s it y (cm
-3)
Y(nm) W/L=200/50nm, without trap
@ V
g=0.3V, V
d=0.05V
Source
29
Fig. 12 The simulated ΔId/Id curve in W/L = 80/50nm, Lt = 10nm device.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0
0.1 0.2 0.3 0.4 0.5 0.6
I
d/I
dV
g(V)
W/L=80/50nm
@ V
g2=-1V, V
d=0.05V
30
Fig. 13 Lt obtained from II WLt
d
d
(red line) and II WLLt
d d
2
(black
line). Trap width defined by TCAD (10nm) and channel width (50nm) are also displayed in diagram as minimum and maximum value of Lt, respectively.
0.0 0.5 1.0 1.5 2.0
0 10 20 30 40 50
L
t(n m )
V
g(V)
W/L=80/50nm @ V
g2=-1V, V
d=0.05V L
t(=(
I
d/I
d*W*L)^0.5) L
t(=
I
d/I
d*W)
L
tminimum value
(TCAD trap width)
L
tmaximum value
(channel width)
31
(a)
(b)
Fig. 14 (a) Electron density with a trap (giving Vg2 = -1V) and without trap, as well as the Δelectron density curves. (b) Δelectron density/electron density(without trap) curves at different Vg.
120 140 160 180 200
10
9120 140 160 180 200
0.0
electron density/electron density (without trap)
X(nm)
32
33
Fig. 16 Fit of WLt and WLLt
2
to ΔId/Id curve. WLt curve matches the ΔId/Id at low Vg and WLLt
2
curve matches ΔId/Id at high Vg.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0
0.1 0.2 0.3 0.4 0.5 0.6 0.7
I
d/I
dV
g(V)
W/L=80/50nm @ V
g2=-1V
I
d/I
dL
t,45%/W
L
2t,45%/(W*L)
34
35
36
Fig. 19 Lt curve derived by II WLt
d
d
and II WLLt
d d
2
, as well as our new fitting model (4-3).