Trap Position versus RTS

In Section 3.1, as the general case, trap is set in the center of gate polysilicon, but in the practical experiment, the trap may not locate right in the center of gate. Consequently, in this section we would change trap position for practical cases. To simplify the expression of trap position, we built a coordinate system on the gate: (1) Gate width direction is set to x-axis; (2) Gate length direction is set to y-axis where drain side is taken as positive side and source side is taken as negative side; and (3) The center of gate is set to the origin (0,0). After setting the coordinate system on the gate poly, we normalized it to that x-axis in the interval [1,-1] and y-axis in the interval [1,-1] as well. The pictures with traps at different positions are shown in Fig. 8, and the ΔId/Id curves of different trap positions are shown in Fig. 9 and Fig. 10.

From Fig. 9, we can observe that trap at (0,0) is larger, and trap at (0,1) and (0,-1) is smaller. Besides, though the curves of (0,1) and (0,-1) are about the same, the value of (0,-1) is larger than (0,1). From Fig. 9 and Fig. 10, ΔId/Id change with different trap positions in the width direction. However, ΔI_d/I_d for trap at gate center changes much more than

9

ΔId/Id for trap at gate edge. Such result can be observed not only for different positions in the width directions, but also different positions in the length direction. It may prove that the influenced range of trap is large enough, so when trap position is at gate edge, the range of effect becomes smaller.

Id of trap near source is smaller than trap near drain. From the ΔId/Id

diagram, we can observe that the largest change between ΔId/Id curves is at about Vg = 0.3V. Therefore, electron density distribution along length direction (shown in Fig. 11) was extracted to compare the difference between gate edge of drain side and source side. We can observe that electron density is larger at source side, so trap has a larger effect when it is at source side.

10

Chapter 4

ΔId/Id

Modeling

From the TCAD simulated ΔId/Id curves, we can observe that the trend of ΔId/Id curves with Vg increasing is not continuously decreasing but increasing in subthreshold region and decreasing afterward. Based on the result, we assumed that there is another fitting model differing from

 in subthreshold region. In subthreshold region, the energy band will be extremely sharp under the trap, and it may cause ΔId/Id involving with only the width factor instead of both width and length. Thus, we will apply _I^I _W^Lt

Therefore, we can observe the validity of Lt while verifying the models.

Fig. 13 shows the Lt curves which are obtained from _I^I _W^Lt and channel width (50nm) are also displayed in diagram as minimum and maximum value of L_t. From the diagram, we can observe that L_t obtained

11

 cannot be applied to strong inversion case.

Besides, we can observe that L_t curve obtained by _I^I _WL^Lt without trap, as well as Δelectron density curves. For example, to define Lt, we assumed that the length with Δelectron density/electron density(without trap) = 45% is Lt. Fig. 14(b) shows Δelectron density/electron density(without trap) at different Vg. From the intersection of Δelectron

15). The two matching curves in combination with ΔId/Id curve is shown in Fig. 16.

12

By getting Lt from simulated electron density, we see that _I^I _WL^Lt

d and the fitting curve is shown in Fig. 17.

In data fitting case, parameter Vg0 and dV cannot be obtained

13 curve obtained by capacitance-voltage fitting. Therefore formula (4-3) can be applied to this case to extract L_t, and to make a comparison with

14 W

L I

I _t

d

d 

 and _I^I _WL^Lt

d d

 2

 , the two curves and new model fitting line are

shown in Fig. 19. From the diagram we can observe that _I^I _WL^Lt

d d

 2

 is

near the new model fitting line at high Vg, and it is not obvious that

W L I

I t

d

d 

 is near the new model fitting line at low Vg because the experiment ΔId/Id curve in the interval between Vg = 0.46V to Vg = 0.6V is distant from subthreshold region.

15

Chapter 5 Conclusion

ΔId/Id fitting model has been established by analyzing both experimental and simulation data. In this thesis, by finding the RTS events in HKMG device, we built a structure by TCAD simulator to simulate RTS events and discussed about the relationship between various device parameters and RTS. In the over literal, the equation

WL L I

I _t

d d

 2

 was widely applied to the entire ΔI_d/I_d curves for different gate biases. We used TCAD to simulate structures with RTS events and extracted the practical range of trap Lt from electron density distribution while fitting ΔId/Id data. Besides, we have proved that RTS is 1D effect in subthreshold region and 2D effect in strong inversion region. Finally, a new ΔId/Id fitting formula was acquired by the two boundary conditions in this study.

16

References

[1] K. S. Ralls, W. J. Skocpol, L. D. Jackel, R. E. Howard, L. A. Fetter, R.

W. Epworth, and D. M. Tennant, “Discrete resistance switching in submicrometer silicon inversion layers: Individual interface traps and low-frequency (1/f ?) noise,” Phys. Rev. Lett., vol. 52, no. 3, pp.

228-231, Jan. 1984.

[2] K. R. Farmer, C. T. Rogers, and R. A. Buhrman, “Localized-state interactions in metal-oxide-semiconductor tunnel diodes,” Phys. Rev.

Lett., vol. 58, no. 21, pp 2255-2258, May 1987.

[3] M. J. Kirton and M. J. Uren, “Noise in solid-state microstructures: A new perspective on individual defects, interface states and low-frequency (1/f) noise,” Adv. Phys., vol. 38, pp. 367-468, 1989.

[4] M. Schulz, “Coulomb energy of traps in semiconductor space-charge regions,” J. Appl. Phys., vol. 74, no. 4, pp. 2649-2657, Aug. 1993.

[5] H. H. Mueller, D. Wörle, and M. Schulz, “Evaluation of the Coulomb energy for single-electron interface trapping in sub-μm metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 75, no. 6, pp. 2970-2979, Mar. 1994.

[6] M. J. Chen and M. P. Lu, “On-off switching of edge direct tunneling currents in metal-oxide-semiconductor field-effect transistors,” Appl.

Phys. Lett., vol. 81, no. 18, pp. 3488-3490, Oct. 2002.

[7] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors,”

IEEE Trans. Electron Devices, vol. 37, no. 3, pp. 654-665, Mar. 1990.

17

[8] M. J. Chen, T. K. Kang, Y. H. Lee, C. H. Liu, Y. J. Chang, and K. Y.

Fu, “Low-frequency noise in n-channel metal-oxide-semiconductor field-effect transistors undergoing soft breakdown,” J. Appl. Phys., vol. 89, no. 1, pp.648-653, Jan. 2001.

[9] E. Simoen, G. Eneman, P. Verheyen, R. Delhougne, R. Loo, K. De Meyer, and C. Claeys, “On the beneficial impact of tensile-strained silicon substrates on the low-frequency noise of n-channel metal-oxide-semiconductor transistors,” Appl. Phys. Lett., vol. 86, no.

22, 223509, May 2005.

[10] K. K. Hung, P. K. Ko, C. Hu and Y. C. Cheng, “Random telegraph noise of deep-submicrometer MOSFETs,” IEEE Electron Device Lett., vol. 11, no. 2, pp. 90-92, Feb. 1990.

[11] E. Simoen, B. Dierickx, C. L. Claeys, and G. J. Declerck,

“Explaining the amplitude of RTS noise in submicrometer MOSFETs,” IEEE Trans. Electron Devices, vol. 39, no. 2, pp.

422-429, Feb. 1992.

[12] K. Kandiah, M. O. Deighton, and F. B. Whiting, “A physical model for random telegraph signal currents in semiconductor devices,” J.

Appl. Phys., vol. 66, no. 2, pp. 937-948, Jul. 1989.

18

Fig. 1 Time records of the drain, source, and gate currents for W/L = 100/26nm device at V_g = 0.56V, and V_d = 0.05V.

0 1 2 3 4 5

2.0 2.1 2.2 2.3 2.4 2.5

I

d

(  A)

Time(s)

W/L=100/26nm @ V_g=0.56V, V_d=0.05V

0 1 2 3 4 5

-2.5 -2.4 -2.3 -2.2 -2.1 -2.0

I

s

(  A)

Time(s)

W/L=100/26nm @ V_g=0.56V, V_d=0.05V

0 1 2 3 4 5

-0.02 -0.01 0.00 0.01 0.02

I

g

(nA )

Time(s)

W/L=100/26nm @ V_g=0.56V, V_d=0.05V

19

Fig. 2 The experimental data of I_d and ΔI_d/I_d versus V_g for W/L = 100/26nm device.

0.0 0.4 0.8 1.2 1.6 2.0 -5

0 5 10 15 20 25 30 35

I

d

(  A )

V

_g

(V) W/L=100/26nm

V

_th

=0.458V @ V

_d

=0.05V

0.45 0.50 0.55 0.60 0.07

0.08 0.09 0.10 0.11 0.12 0.13 0.14

 I

d

/I

d

V

_g

(V)

W/L=100/26nm @ V

_d

=0.05V

20

Fig. 3 The structure built in TCAD under study with N_sub = 2×10¹⁸cm^-3, Nds = 1×10²⁰cm^-3, Npoly = 1×10²⁰cm^-3, and tox = 2nm.

Drain Source

Trap Gate

21

(a)

(b)

Fig. 4 (a) The simulated drain currents (I_d) versus gate voltage (V_g) of different sizes in linear scale. (b) The simulated drain currents versus gate voltage of different sizes in log scale.

0.0 0.2 0.4 0.6 0.8 1.0 1.2

22

23

24

25

(a) (b) (c) (d)

(e) (f) (g)

Fig. 8 The trap position presented in normalized form. (a) (0,0); (b) (0,1); (c) (0,-1); (d) (0,0.5); (e) (0,-0.5); (f) (-1,0); and (g) (-0.5,0).

26

Fig. 9 Δ Id/Id curves in device with different trap positions in x-axis direction (width direction).

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.00 0.05 0.10 0.15 0.20 0.25

 I

d

/I

d

V

_g

(V)

W/L=200/50nm, L

_t

=10nm

@ V

_g2

=-1V, V

_d

=0.05V

trap @ (0,0)

trap @ (0,1)

trap @ (0,-1)

trap @ (0,0.5)

trap @ (0,-0.5)

27 gate edge of source side.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 trap at y-axis position is fixed at gate center trap at y-axis position is fixed at gate edge of drain side trap at y-axis position is fixed at gate edge of source side

trap @ (0,-1) trap @ (-1,-1) trap @ (-0.5,-1)

28

Fig. 11 Electron density distribution along length direction. The region of gate length is in the interval at Y = 200nm to Y = 250nm.

200 210 220 230 240 250

10

¹⁷

10

¹⁸

10

¹⁹

Drain e le c tr o n d e n s it y (cm

-3

)

Y(nm) W/L=200/50nm, without trap

@ V

_g

=0.3V, V

_d

=0.05V

Source

29

Fig. 12 The simulated ΔI_d/I_d curve in W/L = 80/50nm, L_t = 10nm device.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0

0.1 0.2 0.3 0.4 0.5 0.6

 I

d

/I

d

V

_g

(V)

W/L=80/50nm

@ V

_g2

=-1V, V

_d

=0.05V

30

Fig. 13 Lt obtained from _I^I _W^Lt

d

d 

 (red line) and _I^I _WL^Lt

d d

 2

 (black

line). Trap width defined by TCAD (10nm) and channel width (50nm) are also displayed in diagram as minimum and maximum value of L_t, respectively.

0.0 0.5 1.0 1.5 2.0

0 10 20 30 40 50

L

t

(n m )

V

_g

(V)

W/L=80/50nm @ V

_g2

=-1V, V

_d

=0.05V L

_t

(=(



I

_d

/I

_d

*W*L)^0.5) L

_t

(=



I

_d

/I

_d

*W)

L

_t

minimum value

(TCAD trap width)

L

_t

maximum value

(channel width)

31

(a)

(b)

Fig. 14 (a) Electron density with a trap (giving V_g2 = -1V) and without trap, as well as the Δelectron density curves. (b) Δelectron density/electron density(without trap) curves at different V_g.

120 140 160 180 200

10

⁹

120 140 160 180 200

0.0

electron density/electron density (without trap)

X(nm)

32

33

Fig. 16 Fit of _W^Lt and _WL^Lt

2

to ΔId/Id curve. _W^Lt curve matches the ΔId/Id at low Vg and _WL^Lt

2

curve matches ΔId/Id at high Vg.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0

0.1 0.2 0.3 0.4 0.5 0.6 0.7

 I

d

/I

d

V

_g

(V)

W/L=80/50nm @ V

_g2

=-1V

 I

_d

/I

_d

L

_t,45%

/W

L

²_t,45%

/(W*L)

34

35

36

Fig. 19 Lt curve derived by _I^I _W^Lt

d

d 

 and _I^I _WL^Lt

d d

 2

 , as well as our new fitting model (4-3).

0.45 0.50 0.55 0.60 8

10 12 14 16 18 20

L

t

(n m )

V

_g

(V)

W/L=100/26nm @ V

_d

=0.05V fitting by new model (4-3) fitting by L

_t

/W

fitting by L

_t²

/WL

在文檔中 高介電金屬閘金氧半場效電晶體之隨機擾動電子訊號：實驗、建模與TCAD模擬 (頁 21-0)