1.1.1 Poly-Si TFTs
Ongoing researches for polycrystalline silicon thin-film transistors (poly-Si TFTs) have attracted intense attention recently, due to their advantages over amorphous silicon thin-film transistors (a-Si TFTs), such as higher carrier mobility, lower leakage, and higher drive current. Thus, poly-Si TFTs have been widely used in large-area flat panel displays, for example, active-matrix liquid crystal displays (AMLCDs) and active matrix organic light-emitting displays (AMOLEDs) [1.1]-[1.2].
However, the grain boundaries and intra-grain defects degrade carrier transport [1.3]; therefore, they exert a profound influence on the device performance. For this reason, reducing defects inside the poly-Si layer plays a crucial role in optimizing the performance of poly-Si TFTs. It has been reported that poly-Si, formed by the crystallization of a-Si, results in larger grain size and better electronic properties than as-deposited poly-Si [1.4]. In order to improve the characteristics of poly-Si TFTs, there are various techniques in the fabrication which are aimed at two characteristics:
1) enlargement of grain size, and 2) removal of defects in poly-Si films.
Various techniques have been used to crystallize the a-Si into the poly-Si, for instance, solid phase crystallization (SPC), rapid thermal annealing (RTA), excimer laser crystallization (ELC), and metal-induced lateral crystallization (MILC). For SPC process, although it usually takes a long crystallization time of about 20-60 hours at 600℃, its advantages, such as low cost and superior uniformity, make it a commonly used technique [1.5]. RTA is a high temperature (>600℃) process that can complete
crystallization in a short period of time, but this results in films with high defect density [1.6]-[1.7]. Compared with SPC and RTA, ELC can be considered a low temperature process. Even though it is capable of producing poly-Si films with low defect density, it suffers from high initial setup cost, high process complexity and poor uniformity [1.8]. Furthermore, MILC has the problem with metal residues which lead to unacceptable leakage current [1.9]-[1.10].
To passivate the grain boundaries and intra-grain defects, various passivation methods such as hydrogen plasma treatment, hydrogen implantation, and hydrogen-containing nitride film deposition have been applied [1.11]-[1.13].
Although hydrogen passivation eliminates defects and improves the performance of poly-Si TFTs effectively, the poly-Si TFTs after hydrogen passivation suffer from hot-carrier, which might degrade the reliability [1.14]. Because the formation of weak Si–H bonds after hydrogen passivation are easily-broken under hot-carrier stress, F, N2, NH3 plasma treatment are used to obtain a better hot-carrier reliability than H2
plasma treatment [1.14]-[1.16].
1.1.2 Plasma Treatment
Poly-Si thin film consists of different oriented grains, containing many grain boundaries and intra-grain defects. These defects act as trap centers and degrade carrier transport, resulting in unacceptable characteristics of poly-Si TFTs [1.17]. The deep states, which originate from the dangling bonds at grain boundaries, have a faster response to hydrogenation. These deep states degrade the threshold voltage and the subthreshold swing. The tail states, which originate from the strain-bond-related intra-grain defects, respond slower to hydrogenation with an onset period of 4 to 12 hours depending on the grain size. And these tail states degrade the field-effect mobility and minimum leakage current [1.3]. In order to obtain superior
characteristics of poly-Si TFTs, numerous techniques have been used to enhance the device performance by reducing the trap density or increasing the grain size of the polysilicon [1.4].
H2 plasma treatment, also called hydrogenation, is an effective method to passivate defects and improve the performance of poly-Si TFTs. Unfortunately, poly-Si TFTs after hydrogen passivation suffer from hot-carrier issue because the formation of weak Si–H bonds are easily-broken during hot-carrier stressing [1.15].
Also, poly-Si TFTs with H2 plasma treatment loss their passivation effect after subjecting to high temperature (>500℃) annealing [1.16].
N2 plasma treatment can effectively improve device characteristics, such as field-effect mobility, subthreshold swing, minimum leakage current, and on/off current ratio [1.14]. Furthermore, N2 plasma treatment has been proposed to attenuate hot-carrier degradation. Poly-Si TFTs with N2 plasma treatment have better hot-carrier reliability than using H2 plasma treatment, due to strong Si–N bonds with higher bonding energy that would replace the weak Si–H bonds.
Because of the passivation effect of nitrogen and hydrogen radicals, NH3 plasma treatment has also been studied. Similar to N2 plasma treatment, NH3 plasma treatment can passivate defects, improve the performance and the hot-carrier reliability of poly-Si TFTs [1.18]-[1.19]. Besides, it is found that NH3 plasma pretreatment before SPC annealing significantly shortens the a-Si film crystallization time and simultaneously improves device performance and hot-carrier reliability [1.20]. These improvements can be attributed to the combination of following mechanisms: 1) hydrogen radicals that enhance the formation of seed nuclei which reduces crystallization time, and 2) nitrogen and hydrogen radicals pile-up at SiO2/poly-Si interface and terminate the dangling bonds at the grain boundaries, leading to improved performance.
1.1.3 Bottom Gate TFT Structure
Bottom gate TFTs as shown in Fig. 1-1(a), have been widely used because of good match with process integration of conventional SRAMs. Their channel areas are good isolated from parasitic electric field caused by under layers [1.21]. Also, bottom gate TFTs are commonly used as the switching elements in AMLCDs fabrication. It has been reported that bottom gate TFTs can be easily fabricated by the laser annealing of a-Si film for the active layer [1.22], allowing higher circuit density and improving topography compared with top gate devices [1.23]. In addition, because the gate electrode is located under gate insulator for bottom gate structure, the channel is not damaged by the plasma radiation during gate insulator deposition. Therefore, bottom gate TFTs have larger on-state current (ION) than the top gate TFTs [1.24].
Unfortunately, compared with top gate devices as shown in Fig. 1-1(b), smaller grain size and irregular grains of the poly-Si channel result in unacceptable characteristics of bottom gate TFTs [1.25]. Besides, because the gate is located under the active layer, it is difficult to fabricate a bottom gate TFT with its gate edges self-aligned to its source/drain. Thus, bottom gate TFTs suffer from significant performance variation, large parasitic capacitance and poor scalability owing to the misalignment effect [1.23]. Although some self-aligned bottom gate TFTs processes have been proposed, the device processes were too complicated to be utilized [1.26].