The semiconductor industry has emerged as one of the most important industries in many countries such as the USA, Germany, South Korea, Japan, and Taiwan. Semiconductor devices are absolutely essential for almost all electronic products and systems in the sense that most of the electronic products and systems cannot be produced or operated without them. Their influences over human society are enormous. In recent years, the mainstream evolution of the electronic products, such as computers, cell phones, digital cameras/camcorders, and portable audio/video players, has continually striving people toward designing/manufacturing products to be faster in operation, smaller in size, lighter in weight, and of more value-added functionalities. Therefore, how to cope these desirable features has become major challenges in ensuing competitiveness in the semiconductor industry. Needless to say, advanced semiconductor packaging technologies play a very important role in such efforts.
One major goal in advanced semiconductor packaging technologies is to increase the density of devices in a fixed packaging size. To achieve this, the multi-chip module (MCM) was developed and a widely application of the MCM is system-in-package (SiP), which consists of multiple dies stacked vertically and connected within package. Each of these dies, such as a specialized processor, DRAM, or FLASH memory, usually has one sin-gle functionality. Dies are then combined with passive components to form a system or subsystem. Various dies can be manufactured separately in different semiconductor man-ufacturing companies, and then assembled together. However, the cost, as well as the quality and production yield, highly depends on the cost and the quality of the individual dies. Illustrating this with a simplified case that ignores assembly defects and different yield levels of parts in an assembly, Figure 1 shows that the predicted yield of an assembly decreases exponentially as a function of the number of devices used. A SiP consists of various types of dies packaged together in an IC. Any of these dies failed will cause the system not working properly. So, to drive up the yield of a SiP is more difficult than a traditional single-chip IC.
In the final product, if one die fails, the whole module is typically useless or so reduced in performance that it cannot be sold for its intended purpose or at a price that can cover
the cost. Thus, there is no doubt that the high quality of dies is playing an important role for an MCM in the aspect of reducing the cost and enhancing the quality/yield. This leads to the demands for high-quality dies, which are called “known good dies (KGD)”
in the die market. A KGD is a bare die (i.e., without package) with high quality and reliability that can assure the functionality in the integrated circuit (IC) level. Because of that, KGD has become an imperative for component manufacturers who provide various types of dies for the multi-chip module business.
Dies
Figure 1: System predicted yield as a function of the number of dies assembled for various die yields.
However, the semiconductor manufacturing process is more complicate than those of traditional manufacturing industries. It takes about 30–60 days to complete the process of making bare silicon wafers into integrated circuits, such as microprocessors or memory chips. In general, several wafers are processed simultaneously as a “lot”, typically of 25 wafers, and the size of each wafer ranges from 3 to 12 inches in diameter. Each wafer would contain thousands of dies depending on the size of the dies being produced.
After wafer fabrication, all dies on a wafer must go through a process called the wafer sort (WS). The purpose of the wafer sort is to examine the electrical functions of each die and to prevent from packaging bad dies into a multi-chip package. The results of the wafer sort give each die a binary code that denotes it as either a good die (0) or bad
die (1). These wafer sort data then are used to generate the wafer sort map (WSM). A WSM displays the locations of bad dies on the wafer. Figure 2 presents an example of WSMs. The white squares and black squares on the map denote the good dies and bad dies, respectively.
Figure 2: The left panel is a WSM with the code and the right panel is the corresponding visual figure of bad dies.
Since the occurrences of any quality excursions can induce WS failures, WSM analysis can help determine the possible causes of failures and help devise solutions to prevent such failures from reoccuring. For example, uneven temperatures or chemical aging often lead to spatial clusters on the WSM. Clustering also can be the result of crystalline nonuniformity, photo-mask misalignment, or particles caused by mechanical vibration.
Improper material shipping and handling also can leave scratch lines on a WSM (see, for example, Cunningham and McKinnon [1], Hansen and Tyregod [2], Hansen et al. [3], and Taam and Hamada [4]).
Because WSMs contain important information that might guides quality engineers to trace back to the source of process failures, WSMs has been considered as one of the most important analysis tools in the semiconductor industry.
On the other hand, more important issues for KGD vendors to consider are (i) how to provide quality assurance to their customers and (ii) what sale strategies to take to make more profits. One possible solutions for that is to examine WSMs. If a WSM is of
some patterns, it implies process problems exist. Furthermore, the general market has a common view that the good dies on a wafer with no patterns have better quality than the good dies on a wafer with patterns in the semiconductor manufacturing industry. To determine whether a wafer is of some patterns or not, spatial randomness tests are a useful tool. Some tests are available in the literature, see, for example, Taam and Hamada [4]
and Hansen et al. [3].
Ideally, a completely random mechanism for dies can be defined as “bad dies on the wafer are randomly distributed under the spatial homogeneous Bernoulli process (SHBP).” This means the probability of each die being bad is the same. In practice, however, almost all WSMs exhibit some regions of inherent failures, which generally are due to process limitations caused by, say, layouts, equipments, process technologies, etc.
These types of failures are inevitable at the present technology level; thus, in the view of statistical process control, they should be considered as caused by common causes instead of process problems caused by special causes. Thus, in fab, they are often accepted and referred to as the “baseline” of the process. Simply speaking, “common causes” induce usual, historical, and quantifiable variations in a system, whereas “special causes” lead to unusual, not previously observed, and non-quantifiable variations. Figure 3 presents some WSM examples: the top panel shows four “random” wafer sort maps with a baseline of a central disc pattern and the bottom panel exhibits four WSMs with patterns such as linear scratch, ring, bottom, and crescent moon patterns in addition to a central disc baseline.
However, the currently available spatial randomness tests can not distinguish between the wafer patterns induced by common causes or special causes. Because of this reason, semiconductor companies usually hire engineers to classify these WSMs visually based on their own experiences. This approach is subjective as well as time-consuming. It would be desirable to develop an automatic detecting procedure for classifying the wafer patterns induced by common causes or special causes and this is the main objective of this study.