As mentioned early, the wafer sort is a process that examines the functionalities of each die by specific test conditions. One can color each die black (fail) or white (pass) from the test results for a wafer, and the resulting map is called a “wafer sort map”. By incorporating various plotting features into these maps, spatial patterns for passing and failing dies become readily apparent. Since the occurrence of any quality inferiority can usually be attributed to some specific causes, WSM analysis can help determine the possible causes of process failures and help devise solutions to prevent the reoccurrence of these failures.
Usually the failure patterns of WSM can be classified into three major categories as follows: (Kaempf [12])
1. Random patterns:
No spatial clustering and pattern exist, and the defective dies randomly distributed in the two-dimensional map. Figure 11 is an example. Random defects are usually caused by manufacturing environment factors. Even in a near sterile environment, particles cannot be removed completely. Nevertheless, reducing the level of random defects can improve the overall productivity of wafer fabrication.
Figure 11: Random defects of various defect level.
2. Systematic patterns:
As examples, Figure 12 shows some patterns of systematic defects. The positions of defective dies in the wafer show the spatial correlation. Therefore, one may be able to trace back to the assignable cause from the problematic process steps or mechanism by analyzing the spatial distribution of failed dies. Systematic defects usually give an analyst some clues to find problematic steps and ways to eliminate them.
Figure 12: Examples of systematic defects.
3. Mixed pattern:
A mixed pattern is most common for a WSM, which consists of random defects and
systematic defects in one map. Figure 13 gives an example.
Figure 13: Random defects plus systematic defects to form a mixed defects.
The following are four patterns occurring most often and some potential causes asso-ciated with them. A baseline of a central disc is included as an example in the illustrative figures.
• Bottom
The bottom pattern (Figure 14) could be the result of uneven heating during a diffusion process or the probe card itself failed.
Figure 14: Bottom pattern
• Ring
The ring pattern (Figure 15) appears on the WSM as a result of non-uniformities created in the thin film deposition process or an uneven temperature distribution during the rapid thermal annealing process.
Figure 15: Ring pattern
• Linear Scratch
The linear scratch pattern (Figure 16) on the WSM could be a result of material shipping and handling during the manufacturing or testing.
Figure 16: Linear scratch pattern
• Crescent Moon
The crescent moon pattern (Figure 17) could be the result of defective wafer ma-terials or adverse processes. For example, a fab engineer who notices this pattern might decide to immediately look at the rapid thermal anneal (RTA) process.
Figure 17: Crescent moon pattern
3 Literature Review
In this section, we review some areas of research related to wafer maps, two spatial randomness tests for testing the spatial randomness of wafer maps, and the kernel density estimation that we use as a tool in our proposed schemes.
3.1 Related Studies
These areas in semiconductor manufacturing related to wafer maps are briefly described here, including decision systems, yield models, and pattern recognition.
1. Decision System
Decision system is namely the application of various kinds of knowledge systems to failure analysis. It integrates parameter analysis and engineering experiments to help engineers effectively find the assignable causes and make decisions.
Two early examples of knowledge systems used in semiconductor manufacturing are PIES (Pan and Tenenbaum [13]) and SMART (Mary [14]) that diagnose problems in semiconductor fabrication processes by analyzing parametric test data. Maly et al. [15] recommended using a hierarchical methodology for the interpretation of test data. Methods such as CART (Breiman et al. [16]) and decision tree (Venkat [17]) would be useful in developing a decision system.
2. Yield Models
Yield in many ways is the most important financial factor in producing ICs. This is because yield is inversely proportional to the total manufacturing cost. The higher the yield is, the lower is the cost.
A yield model that provides good estimates of manufacturing yield can help predict product cost, determine optimum equipment utilization, or be used as a metric for supporting decisions involving new technologies and the identification of problematic products or processes. Cunningham [18] provided a good historical review of yield models.
Yield prediction of semiconductor dies can be used to:
• determine the cost of a new chip before fabrication,
• identify the cost of defect types for a particular chip or a range of chips,
• estimate the number of wafer starts required,
• show which defect types accounted for the most yield loss,
• identify when a fabrication process is not performing as expected,
• determine the extent of parametric problems (in both design and process),
• monitor the fabrication process.
3. Pattern Recognition
Since wafer maps contain important information that could be used to trace the process failures back to their root causes for quality engineers, how to recognize wafer patterns is an important issue.
Gleason et al. [19] employed an automated clustering algorithm using artificial intelligence. Chen and Liu [20] and Liu et al. [21] used neural networks for pattern recognition. Lee et al. [22] adopted a self-organized feature map for advanced process controls. Chao and Tong [23] used multi-class support vector machines with a novel defect cluster index for pattern recognition. The above methods need a large number of good training samples in order to successfully recognize defect patterns.
In the process of pattern recognition, performing a spatial randomness test is an important step to classify raw WSMs into two categories, patterned or random. If the spatial randomness test is too sensitive, the frequency of false alarms would be large.
Conversely, if the spatial randomness test is not powerful enough, process failures may not be detected and opportunities of quality improvement are lost. In the following, we describe two existing spatial randomness tests.