In this section, the concept of the previous model is explained and the inadequacy of this model is demonstrated. A number of have attributed subbreakdown to the
band-to-band tunneling process in silicon in the gate-to-drain overlap region, as illustrated in Fig. 4.16. The cross section shown in Fig. 4.16 is simply a gated-diode configuration. When high voltage is applied to the drain with the gate grounded, a deep-depletion region is formed underneath the gate-to-drain overlap region.
Electron-hole pairs are generated by the tunneling of valence band electrons into the conduction band and are collected by the drain and substrate separately. Since all the minority carriers generated thermally or by band-to-band tunneling in the drain region flow to the substrate due to the lateral field, the deep-depletion region is always present and the band-to-band tunneling process can continue without creating an inversion layer. Band-to-band tunneling is possible only in the presence of a high electric field and when the band bending is larger than the energy band gap, Eg.
The conventional model has assumed that (a) the value of band bending in the depletion layer in the drain-to-gate overlap region is fixed at Eg=1.12 eV, which is the minimum value necessary for a tunneling process to occur, and that (b) band-to-band tunneling occurs only at a point of the Si-SiO2 interface, as shown in Fig. 4.16.
A simple expression for the surface field ([23], [32]) at the dominant tunneling point is:
where ESi is the vertical electrical field at the silicon surface, 3 is the ratio of silicon permittivity to oxide permittivity, and Tox, is the oxide thickness in the overlap region.
The theory for tunneling current predicts [32] that exp( )
where A is a pre-exponential constant and B = 21.3 MV/cm. The dependence of the
‐ 23 ‐
subbreakdown current on both the oxide thickness and the impurity distribution plays an important role in the subbreakdown phenomenon. Although the previous model took into account the effect of oxide thickness, the dependence on the impurity distribution was neglected. But, the calculated results do not agree with the experimental results, especially under the stressed condition. The simplified model is, therefore, totally inadequate for the subbreakdown phenomenon.
Fig. 4.16(c) shows a cross-sectional view of an n-MOSFET device. When the drain is connected to a positive bias and the gate is connected in the vicinity of zero bias or even to a negative bias, a depletion region is formed underneath the drain-to-gate overlap region and a high field is created in the depletion region. Electron-hole pairs are generated by the tunneling of valence band electrons into the conduction band and collected by the drain and substrate separately. In Fig. 4.14(a), a vertical and lateral energy band diagram is presented near the point, as shown in Fig. 4.14(b). In Fig.
4.14(b), the electrons tunnel into the drain due to the vertical field ESi is shown. For the band-to-band tunneling process, because the tunneling electrons in the drain dominate the GIDL, the vertical field in the drain is the dominant field for the leakage and is an important parameter in the tunneling current model [36] in Fig. 4.15. In addition, the vertical field depends on the band bending Vbend, as shown in Fig.
4.16(b), and the Vbend is strongly related to the drain doping concentration. Therefore, the drain doping concentration is also an important parameter in the tunneling current model. Thus, the vertical field in the overlap region could be estimated using depletion approximation.
When the VDG is a constant, the vertical fields in the gate-to-drain overlap region are nearly equal regardless of what drain and gate voltage are applied. However, if the
gate voltage is more negative, the drain voltage must be more positive. The GIDL would not be equal under constant drain-to-gate voltage VDG. The GIDL is dependent on both the drain-to-gate voltage VDG and drain voltage VD [33], [34].
In this section, the concept of the new accurate model is explained, and the new model is introduced in detail. The concept underlying the new model has four aspects:
(a) a deep-depletion layer is created in silicon in the drain-to-gate overlap region and the value of band bending increases monotonically over 1.12 eV as a function of drain voltage.
(b) The dependence of subbreakdown on the impurity distribution is considered.
(c) Both the electric field of the deep-depletion layer and the tunneling region are calculated by depletion approximation.
(d) The band-to-band tunneling rate is calculated by the two-band theory.
The concept for this model is given as follows. Holes are generated by band-to-band tunneling. However, an inversion layer is not formed in the drain-to-gate overlap region, because the generated holes flow into the substrate due to the lateral electric field. Therefore, the band bending value and the electric field increases monotonically as drain voltage increases in Fig. 4.17-4.20. The width of the depletion region where electron tunneling occurs also increases as the drain voltage increases. Both the electric field and the band bending value can be estimated by depletion approximation, as functions of the drain voltage, the distribution of impurity density in the drain, and the oxide thickness.
When the impurity distribution in the drain-to-gate overlap region is uniform, for example, the electric field in the depletion region becomes [33]
‐ 25 ‐
where Esi is the electric field in the depletion region, Vbend is the band bending value, ND is the impurity density in the drain region, q is the electron charge, εSi is dielectric constant of the silicon, and X is a coordinate normal to the Si-SiO2 interface.
The silicon surface is represented by the plane at X = 0 and the bulk by a positive value of X. From the Gaussian law, the continuity equation for electric displacement at the Si-SiO2 interface becomes
( 0) ( ) /
SiESi X oxEox ox VDG Vbend Tox
ε = =ε =ε − (4.4)
where EOX is the electric field in the SiO2 layer, and εox is the dielectric constant of the oxide. Substituting (3) into (4), the band bending value is given as a function of drain voltage as follows:
2 2
When the gate electrode is biased negatively, the gate overlap region over the source/drain extension region immediately goes into accumulation given the fact that the flat band voltage between the heavily doped n+ poly-Si region and the source/drain extension region is almost zero.
2 2
Full-overlap LDD is used to study this tunneling leakage because the lateral field is suppressed while the drain concentration is high enough so that the dominant tunneling point has a band bending of 1.2 eV (Fig. 4.16(a), (b)). However, the energy gap decreases as the STI spacing wall a decreasing in Fig. 4.21. The proper and simple current model for GIDL (or surface BTBT) ([34], [36-38]) can be expressed as
follows: effective tunneling area. Therefore, using this simplified model, we can fit the measured GIDL under the stressed condition well.