In order to shrink MOSFET devices into the deep sub-micrometer regime, the level of channel dopants will increase inevitably and the gate dielectric thickness must decrease. This leads to a significant increase of the normal electric field, imposing high demands on the advanced technology and on the understanding of the device physics involved. Thus, accurate characterization and modeling of ultra thin oxides in the leakage current in the high field conditions is essential and crucial [1]. A series of models including the tunneling regime have recently been published concerning the electron direct tunneling in n+ poly-gate nMOSFETs and the electron tunneling from the valence band into the conduction band in the gate-to-drain overlap region.
Recently, the mechanical stress induced by shallow trench isolation (STI) attracts a lot of attention [2]. Both the experimental work and numerical simulation have demonstrated that the STI stress magnitude is rather high in scaled MOSFETs [3, 4].
The effect of the STI-induced stress on the carrier mobility has been discussed in [5].
The enhancement or suppression of dopant diffusion due to STI-induced stress is also reported in [6].
Moreover, the leakage currents at high electric field are not only the single factor induced by the only one mechanism [1], but also have the mechanical stress induced variation [2]. In this thesis, the mechanical stress induced by shallow trench isolation (STI) significantly affects the device behavior in the advanced CMOS technology.
The thesis presents that the stress induced from the STI spacing sidewall can be extracted by the basis of the triangular potential approximation [7].
The electrical approach to the local mechanical stress around the source/drain extension corner of uniaxially stressed nMOSFETs is also presented later. With the proper measurement, we can separate correctly the dominated leakage current mechanism in the off-state regime. Therefore, the edge direct tunneling current in the n+ poly-gate and the gate-induced drain leakage at high electrical field in the gate-to-drain overlapped region can be simulated from the triangular potential simulator. Thus, the parameters from the current mechanism can be extracted reasonably.
Section 1.2 Organization of The Thesis
In this thesis, it is organized based on the following arrangement. Chapter 2 discusses the techniques of the stress extracted from the gate-to-STI (shallow trench isolation) spacing sidewall for ultrathin gate oxide nMOSFETs. Through the TRP (triangular potential) simulator, the STI-induced stress can be extracted and the quantum confinement phenomenon is depicted in the subbands in nMOSFETs.
In Chapter 3, on the one hand, the stress-induced leakage current variation is investigated, and the edge direct tunneling (EDT) currents reflect the STI-induced stress. On the other hand, the EDT of electrons from n+ plysilicon to underlying n-type drain extension in off-state nMOSFETs can be simulated via TRP. Moreover, it is in agreement with the measured data under the stress condition resulted from the STI. Applying the correct model, the EDT under the stress condition can reveal the effective tunneling path of EDT with the doping concentration of drain extension
‐ 3 ‐
taken into account.
In Chapter 4, under off-state situation, the drain leakage results from the edge direct tunneling (EDT) rather than conventionally gate-induced drain leakage (GIDL) or bulk band-to-band tunneling (BTBT). However, the conventional GIDL (or surface BTBT) is recognized as the major drain leakage in off-state, but from our experiment, the leakage current is dominated by the different magnitude of the drain to gate voltage. They can be separated through this experiment, and fitted by the proper model. Especially, in high electric field, the dominated leakage is the GIDL and it is influenced by the stress. Thus, the energy gap and band bending voltage vary and are not always constant. In addition, using the TRP, the simulated data can be calculated in the adequate model. The parameters can be extracted subsequently.
Finally, conclusions are given in Chapter 5, where the major contribution of the work is proposed.
Chapter 2 Stress Extraction
Section 2.1 Device Under Study
The n+ poly-silicon gate n-MOSFETs were fabricated in a state-of-the-art manufacturing process. The device process flow is depicted in Fig. 2.1. Three key process parameters obtained by the capacitance-voltage (C-V) fitting are as follows:
n+ poly-silicon doping concentration = 1 10 cm× 20 −3, gate oxide thickness = 1.27 nm , and substrate doping concentration = 4 10 cm× 17 −3. In this chapter, the devices was characterized, for gate length L of 1 mμ , and gate width W of 10 mμ . For the devices, the gate length along the 110 direction was 1 mμ large enough that the following effects can be effectively eliminated: external series resistance and short channel or drain induced barrier lowering (DIBL), whereas the gate width was 10 mμ , indicating that the transverse stress is relatively negligible. The layout technique was utilized in terms of gate edge to STI (Shallow Trench Isolation) sidewall spacing, which is designated as a , with four values of 10, 2.4, 0.495, and 0.21 mμ . A decrease in a means increased magnitude of longitudinal stress. The schematic cross section and the topside view of the test device are depicted in Fig. 2.2(a) and (b).
A considerable number of contacts were formed on the source/drain diffusion along the gate width direction, far away from the STI in 110 direction. The spacing between the gated edge is fixed in this work. It has been reported that silicide can introduce stress into channel and its effect can be eliminated by well controlling the
‐ 5 ‐
silicide formation [5]. Thus, the silicide process was fine tuned for the device under study to minimize its effect as compared with STI stress.
The gate direct tunneling current was measured in inversion conditions with the source, drain, and substrate all tied to ground. Also characterized was mobility on the same device at VD = 25mV. The change of the conduction-band electron direct tunneling current at VG=1V and the mobility at VG=0.5V, all with respect to A = 10 μm , are plotted in Fig. 2.3 versus gate to STI spacing. It can be seen that a decrease in the gate to STI spacing can produce an increase in both the gate current and threshold voltage while degrading the mobility [9].
Section 2.2 The TRP simulator
The TRP simulator was constructed to quantify the direct tunneling current density on the basis of the triangular potential approximation in the channel, taking into account the poly-silicon depletion [7]. A good starting point to understand the band splitting induced by strain or stress is from the aspect of broken symmetry. Due to the commutation between operations and crystal Hamiltonian, symmetry plays a vital role in determining the band structure. Compressive stress causes the repopulation of the electrons, decreasing the electron density and Si/ SiO2barrier height in theΔ valley, 2 while increasing the electron density and Si/ SiO2barrier height in theΔ valley [10]. 4 Note from the expression listed above that the change in the conduction band energy may cause the strain altered gate leakage (Fig. 2.4).
Sketched in Fig. 2.5 (a) and (b) is the band’s structure for silicon, which are
ellipsoids of constant electron energy in reciprocal space, each corresponding to one of the degenerate conduction band valleys. In this thesis, quantum confinement and stress both enhance the degeneracy between the four in-plane valleys (Δ ) and the 4 two out-of- plane valleys (Δ ) owing to energy splitting. Compressive stress 2 decreases the electron population in theΔ valley due to a higher out-of-plane mass 2 and a significantly longer lifetime compared to theΔ valley, resulting in an increased 4 electron tunneling current [11].
The electron direct tunneling current density can be modeled by the TRP simulator.
First of all, the potential drop due to poly depletion is determined through the following expression [9]:Vpoly =εox2 Fox2 2qεsiNpoly , and the substrate band bending can be written as Vs = VG −VFB −Vpoly−Vox , where V is the applied gate G voltage,V the flat band voltage , FB V the oxide potential drop, andox Vpoly the potential drop in the n+ poly-silicon region. The reference point of this model is the conduction band edge of the Δ subband. Therefore, the tunneling barrier at the 4 cathode-side interface and the relative positions of the Δ and 2 Δ subbands can be 4 defined as [12]:
The change in the energy bandgap is then considered:
( )
( ) 1 4g g V d
E stressed =E unstressed + ΔE + ΔE (2.7)
Fig. 2.6 presents the band diagram when the cathode side is stressed, whereas no stress is applied on the cathode-side. Taking into consideration that the n+ poly-silicon region is also stressed, as depicted in Fig. 2.7, the electron group velocity normal to the interface in the anode-side should also be modified. By modeling the energy band as parabolic one, we can compare the relative energy shifts on both sides of the silicon oxide to derive electron group velocity normal to the interface on both the anode and cathode sides. The modifications in the following expressions alter the correction factors in our TRP simulator and thus change the transmission probability [12].
The normal components of electron group velocity on both the anode and cathode sides are listed below:
( ) ( )
the primed and unprimed symbols represent the energy shift in the n+ poly-silicon region and the underlying substrate region, respectively.
It is now a straightforward task to calculate the electron direct tunneling current density. If all the subband energy levels are determined, then the inversion-layer carrier density per unit area can be expressed as [9, 12-15]
( )
and mdiis the density of state effect mass. Then, by relating the boundary conditions between the oxide and silicon surface, the charge conservation relationship(
NS Ndepl)
oxFoxq + ≈ε [7, 9] can be established. From now on, it is the TRP simulator that employs an iteration procedure to select the appropriate oxide field value to meet the above expression. The flowchart of the TRP simulator is drawn in Fig. 2.8.
Section 2.3 Stress Extraction via TRP simulator
Existing direct tunneling models [16, 17] on the basis of the triangular potential approximation [7] in the channel, which takes into account the poly-silicon depletion, can be readily applied with some slight modifications such as incorporating stress dependencies of the subbands. The electrons in inversion primarily populate the two
‐ 9 ‐
lowest subbands [15]: one of the twofold valley Δ2 and one of the fourfold valley Δ4.The corresponding stress dependencies are well defined in the literature [15, 18-19]. The hydrostatic and shear deformation potential constants Ξd =1.13eV and
u =9.16eV
Ξ , which are close to those of Ref.[15], [20] were cited here. Stress along
110 direction can be resolved into two different components normal and shear
stress terms in 110 coordination. Shear terms can cause the band distortion, which in turn influences the effective mass. This effect becomes significant when applied strain approaches 1% and beyond, whose magnitude is much greater than that in our study case. Thus, it is reasonable to assume that effective mass change can be neglected under moderate stress in the subsequent calculation. One of the expressions for the effective electric field Eeff can be found elsewhere [15]. With the aforementioned process parameters as input, the two lowest subband levels with respect to the Fermi level Ef can be determined. The stress dependencies of the lowest subbands under different gate voltages were found to be consistent with those
in earlier works [15]. The inversion-layer carrier density per unit area can further be calculated by N KBT gimdi
( ( (
Ef Ei)
KBT) )
valley, and mdi is the density of state effective mass. It is then a straightforward task to calculate the Wentzel–Kramers–Brillouin tunneling probability, taking into account the corrections for reflections from the potential discontinuities [12]. Here, the electron effective mass in the oxide for the parabolic-type dispersion relationship was used with mox ∼ 0.50 m0, which is equivalent to mox = 0.53m0 for the tunneling electrons in the oxide using the Franz-type dispersion relationship [21]. The SiO2/Si interface barrier height in the absence of stress is 3.15 eV.Consequently, without adjusting any parameter, the conduction band electron direct tunneling current density can be calculated as a function of stress σ [15] as
( ) ( )
The tunneling lifetime in (3) can be related to the transmission probability T as
2( ) /(T 2( )E 2( ))
τ σΔ = hπ Δ σ Δ σ and τ σΔ4( )= hπ /(TΔ4( )σ EΔ4( ))σ .
With the above approach, we found that the uniaxial channel stress of around 0, −20,
−125, and −320 MPa for a gate-to-STI spacing of 10, 2.4, 0.495, and 0.21 mμ , respectively, can reproduce gate direct tunneling current versus gate voltage characteristics. The corresponding gate current change is plotted in Fig. 2.3 versus the extracted channel stress with gate voltage as a parameter. It can be seen that the magnitude of the gate current change increases linearly with the stress, which is
‐ 11 ‐
consistent with those published elsewhere [15]. Again, in agreement with the citation [15], the slope of the straight line in Fig. 2.3 increases with decreasing gate voltage.
This trend clearly points out that the accuracy of the proposed method can be enhanced by lowering gate voltages.
Chapter 3
Edge Direct Tunneling Leakage Current Simulated with TRP
Section 3.1 Introduction
The off-state drain leakage is one of the big issues for aggressively shrunk MOSFET’s. The well recognized mechanisms are the gate-induced-drain-leakage (GIDL or surface band-to-band tunneling) [22], [23], the bulk band-to-band tunneling (BTBT) [24], and the drain-induced-barrier-lowering (DIBL) enhanced subthreshold conduction. In the case of reverse substrate bias for suppression of DIBL or subthreshold leakage, the bulk BTBT dominates [25]. On the other hand, the gate leakage due to direct tunneling (DT) [26] was measured per unit oxide area and a certain criterion of 1 A/cm set the ultimate limit of scalable oxide thicknesses [27], [28]. Recently, Yang et al. [29] have originally explored a dominant off-state leakage component via edge direct tunneling (EDT) of electron from n poly-silicon to underlying n-type drain extension. Also carried out in [29] is the I-V modeling obtained by following the procedure in [12], [16]. However, some parameters of great relevance were not clarified yet, such as the tunneling path area and the doping concentration of drain extension. In particular, the oxide field is an essential input parameter to the DT I-V model in [12]. We report that as scaled gate oxide thickness approaches the DT regime, the EDT of electron from n poly-silicon to underlying n-type drain not only dominates the gate leakage, but also can prevail over the conventional GIDL (Fig. 3.1), in agreement with [29]. This phenomenon is more pronounced for thinner oxide thicknesses, and EDT can even compete over the bulk
‐ 13 ‐
BTBT in the case of reverse substrate bias not mentioned in [29]. It is clarified that the gate leakage in stand-by mode indeed originates from the edge part rather than the whole gate oxide, and thus should be measured per unit gate width rather than per unit oxide area as in [27], [28]. Also presented is a physical model for the first time derived for the oxide field at the gate edge by accounting for electron subband in the quantized accumulation poly-silicon surface and its band diagram can be seen in Fig.
3.2. This model is valuable in enabling consistently the reproduction of EDT I–V, the extraction of EDT path size (Fig. 3.3), and doping concentration of drain extension.
Section 3.2 Experiment and Characterization
The test device was an n+ poly-silicon gate n-MOSFET as fabricated in a state-of-the-art manufacturing process. The device process flow is depicted in Fig. 2.1.
Also plotted in the figure is the schematic topside view of the test device. Three key process parameters were obtained by capacitance–voltage (C–V) fitting: n+
poly-silicon doping concentration =1 10 cm× 20 −3, gate oxide thickness =1.27 nm , and substrate doping concentration=4 10 cm× 17 −3 . In this process, the shallow-trench isolation (STI)-induced compressive stress was applied. A layout technique was utilized to produce a variety of stress in terms of the gate edge to STI sidewall spacing, designated as a, with four values of 10, 2.4, 0.495, and 0.21 μm. A decrease in a means increased magnitude of longitudinal stress. Considerable numbers of contacts were formed on the source/drain diffusion along the gate width direction, far away from the STI in the 110 direction. The spacing between the diffusion contact and the gate edge is fixed in this paper. With the source, drain, and substrate all tied to ground (in Table. 1 Bias condition (2)), the measured valence-band electron tunneling current in inversion (for the gate voltage VG larger than the threshold voltage Vth ) or
equivalently the substrate hole current was found to be unchanged, regardless of the stress. This indicates that the gate oxide thickness under study remains constant. The I-V curves are shown in the following Fig. 3.4 and 3.5.
Section 3.3 Physical Model for EDT
The electron direct tunneling from the accumulated poly-silicon surface down to the underlying silicon was measured versus negatively biased gate voltage with the source, drain, and substrate all tied to the ground. It can be seen in Fig. 3.4 that the resulting substrate hole current, which essentially is equal to the electron gate-to-substrate tunneling current, increases with decreasing a. Such dependency reflects the increasing magnitude of lateral compressive stress in the poly-silicon. The confirmative evidence of this origin is that for a given gate-to-STI spacing, the corner stress and channel stress both are comparable, and since the tunnel oxide is rather thin, the lateral compressive stress at the surface of the poly-silicon is reasonably close to that of the underlying silicon. In contrast, the simultaneously measured source/drain or edge direct tunneling (EDT) current decreases with decreasing a, as shown in Fig.
3.5 and Fig. 3.6. To determine the underlying gate-to-source/drain extension overlap length where the EDT prevails, the existing edge direct tunneling models [1], [15], [17] on the basis of the triangular potential approximation [7] (Fig. 3.6) can readily apply with some slight modifications such as incorporating stress dependencies of the subbands in the accumulated poly-silicon surface. First of all, the oxide field Eox at the gate edge is determined through the following expression:
DE
‐ 15 ‐
whereV is the applied gate voltage,DG V the flat band voltage, andFB V the oxide ox potential drop, tox is the gate oxide thickness, and Vpoly and VDE are the potential drops in the n+ poly-silicon and source/drain extension region, respectively. The accumulated electrons mainly populate in the first subband E1 due to the lowest quantized energy dominating. Then, relating the sheet charge density to the number of occupied subband states can establish the charge conservation relationship
1 2
( fn ) md ox ox
q E E η ε E Q
− π = =
h (3.2)
where Efn is the quasi-Fermi level in n+ poly-gate, η is the degeneracy factor, and Q is the available charge for tunnel process. The corresponding stress dependency of the quantized energy is well defined in the literature [9], [15].
( )( ) ( )( ) here. With the aforementioned parameters as input, the lowest subband level with respect to the Fermi level can be quantified. Employing the lowest subband approximation to the accumulated n+ poly-gate and the deep depletion approximation to the source/drain extension region, as drawn in Fig. 3.6, the following expressions can, therefore, be derived:
2
2 2
where NDE is the doping concentration of the source/drain extension. Here, the quantization effective masses mz = 0.98 m0 and md = 0.19m0, and η = 2 were adopted to approximate the band structure for 110 oriented poly-silicon grain [12]. Then, it is a straightforward task to calculate the WKB tunneling probability, taking into account the corrections for reflections from the potential discontinuities [12]. Here, the electron effective mass in the oxide for the Franz-type dispersion relationship was used with mox = 0.53 m0. The SiO2 /Si interface barrier height in the absence of stress is 3.15 eV. Consequently, the edge electron direct tunneling current density can be
where NDE is the doping concentration of the source/drain extension. Here, the quantization effective masses mz = 0.98 m0 and md = 0.19m0, and η = 2 were adopted to approximate the band structure for 110 oriented poly-silicon grain [12]. Then, it is a straightforward task to calculate the WKB tunneling probability, taking into account the corrections for reflections from the potential discontinuities [12]. Here, the electron effective mass in the oxide for the Franz-type dispersion relationship was used with mox = 0.53 m0. The SiO2 /Si interface barrier height in the absence of stress is 3.15 eV. Consequently, the edge electron direct tunneling current density can be