Above all, this work is to discuss the impacts of inserting a TEOS buffer layer and using Hi-wafers as substrates on the performance of strained-channel NMOSFETs with Si3N4 capping layer. For brevity, we name all splits as follows,
“Hi” represents the Hi-wafer control split, “Cz-control” represents the Cz wafer control split, “SiN/Buffer/Hi” represents the Hi-wafer with TEOS buffer layer and Si3N4 capping layer, “SiN/Buffer/Cz” represents the Cz wafer with TEOS buffer layer and Si3N4 capping layer, “SiN/Hi” represents as Hi-wafer with Si3N4 capping layer, “SiN/Cz” represents the Cz wafer with Si3N4 capping layer, “Hi-F” represents the Hi-wafer with F channel implant, “Cz-F” represents the Cz wafer with F channel implant, respectively. Figure 3.1 shows the capacitance-voltage (C-V) characteristics of devices. In the figure, we could distinctly observe that the poly-depletion effect becomes obvious in the splits with Si3N4 capping layer depositions, irrespective of the use of Cz or Hi wafers. Based on the results of our group’s previous study [28], this is attributed to the additional thermal budget associated with the nitride deposition step. It is known that the solid solubility of dopants is temperature-dependent and the thermal conditions mentioned above tend to lower the activated carrier concentration in the poly-Si gates [62] as illustrated in Figure 3.2. Besides, the C-V characteristics of MOSFETs are very essential for
verifying the gate oxide quality and calculating the equivalent oxide thickness (EOT). Figure 3.1 (c) illustrates the C-V characteristics of NMOSFETs for all splits of samples, and the EOT, given by
inv
capping layer is approximately 20.7 Å, while those splits with Si3N4 capping layer is about 22.21 Å. The difference under inversion is the direct evidence of the poly-depletion effect. Figure 3.1 (d) shows the C-V characteristics of NMOSFETs for the F-channel-implanted splits, there is no obvious difference between them, indicating the F channel implant would not influence the fundamental performance and EOT of devices.
The drain current (ID) versus gate voltage (VG) characteristics and the transconductance (Gm) versus gate voltage characteristics of all splits with
m found that the subthreshold slope is higher and the off-state leakage current is also about two orders larger for the splits with Si3N4 capping layer. However, there is a significant increase in transconductance for the splits with Si3N4 capping layer due to the induced tensile stress in the channel, which in turn could enhance the electron mobility. In addition, ID and transconductance (Gm) versus VG characteristics of the splits with F-implanted channel for both Cz and Hi-wafers are illustrated in Figure 3.4. From the figure, there is no obvious difference in the off-state leakage current and the subthreshold slope among the splits irrespective of F implantation, while a slight difference approximately 3.6％ could be observed at Gm,max. Therefore, it seems that the F ion implantation draws no major influence on the fundamental properties of the devices. The output characteristics of all splits with
m
There is no obvious difference between Cz and Hi-wafers, and it is seen that the
insertion of the TEOS buffer layer prior to the Si3N4 capping layer deposition would not degrade the drive current enhancement caused by the capping of thicker Si3N4
etch-stop layer which is tensile inherently [63].
Figure 3.6 shows the distribution of the subthreshold slope (S.S.) versus the gate length of the F-free split conditions. For the splits of Cz-controls and Hi, S.S. is independent of gate length, and further Hi split depicts lower S.S. than Cz-controls, demonstrating that it has better interface quality due to the high temperature hydrogen anneal.However, the splits with Si3N4 capping layer depict higher S.S than those without the SiN capping, especially when the device channel length becomes longer. The root cause for such phenomenon is not clear yet at this stage.
Increase in EOT due to poly depletion effect may play a role. It is noted that the TEOS buffer layer could effectively block hydrogen molecules diffusion from Si3N4
capping layer deposition. As a consequence, the S.S. increases due to less effective interface passivation. Furthermore, the distribution of the S.S. versus the gate length of the F-implanted split conditions is illustrated in Figure 3.7. Again, the impact of F implant on the S.S. of the fabricated devices is not significant.
Figure 3.8 shows the percentage increase of the transconductance (Gm) among different splitswith respect to the Cz-control split as a function of channel length.
The transconductance enhancement reaches about 20% at a channel length of 0.5μm.
When the channel length is scaled to less than 1μm, the Gm increases sharply owing to the aforementioned strain effect. In other words, the strain is distributed locally inside the channel region and concentrated near the source and drain region. This effect can be explained by the splitting of the degeneracy at the conduction band edges under the uniaxial strain [64]. Figure 3.9 exhibits the percentage increase of Gm among the F-implanted splits with respect to the Cz-control split as a function of channel length. There is a negative percentage increase in Gm of the Cz-F split,
which may result from the implantation-induced damages, and an increase in the interface traps, which may degrade the carrier mobility. On the contrary, no obvious difference of the Gm percentage increase between the Hi and Hi-F splits is observed.
Figure 3.10 exhibits the percentage increase of the on- current among different splitswith respect to the Cz-control split as a function of channel length. In this figure, it can be seen that the trend of on-current enhancement is the same as that of Gm enhancement as shown in Figure 3.8. The percentage increase of the on-current among the F-implanted splitswith respect to the Cz-control split as a function of channel length is illustrated in Figure 3.11, showing similar trend as that of Gm enhancement in Figure 3.9.
Figure 3.12shows the charge pumping current (Icp) versus the base voltage. The device size is
= , the pulse amplitude is 1.5V, and a gate voltage train of square waveform is used for Icp extraction. From the figure, the splits of SiN/Cz and SiN/Hi depict slightly higher Icp as compared with the splits of Hi and Cz-control. We discover that a large amount of the interface states are produced during the Si3N4 capping layer deposition as compared with the devices without the Si3N4 capping layer, revealing that the channel strain certainly leads to the increase of the interface states at the Si/SiO2 interface. But at the same time, the hydrogen species contained in the nitride layer can effectively passivate the dangling bonds at the Si/SiO2 interface. For deposition of the LPCVD- Si3N4, SiH2Cl2 and NH3 were used as the reaction precursors, and a significant amount of hydrogen may be incorporated in the deposited film. However, the above results indicate that the number of interface states passivated by the hydrogen species is less than that generated by the channel strain. Moreover, the charge pumping current increases doubly for the splits of SiN/Buffer/Cz than the SiN/Cz and SiN/Hi splits. These
results indicate that the TEOS buffer layer can effectively block the diffusion of hydrogen species into the channel region during the Si3N4 capping layer deposition process.As a result, the incorporation of hydrogen species in the gate oxide and at the interface can be suppressed remarkably with the insertion of TEOS buffer layer, and the strain-induced interface trap states from the Si3N4 capping layer will not be effectively passivated. This explains why the percentage increase of Gm for the SiN/Buffer/Cz splits is lower than that for the SiN/Cz splits. Nevertheless, it is noted that the Icp of the SiN/Buffer/Hi splits is only slightly higher than that of the SiN/Hi split.Therefore, the blocking of hydrogen diffusion is not a serious concern for the SiN/Buffer/Hi splits. The Icp versus base voltage for the F-implantated splits is illustrated in Figure 3.13. As can be seen in the figure, we find that the Icp of the F-implant split is much higher than that of other splits, owing to the implant damages in the channel region, consistent with the trend of the percentage increase of the Gm.
Figure 3.14 shows the comparison of the effective mobility extracted from the split C-V method among different split of samples. The device size is
m m WL
μ μ 50 50
= . The splits of Cz group depict degraded behaviors for the splits with the Si3N4 capping layer in the low field region, as shown in Figure 3.14(a).
This indicates that the higher interface states tend to enhance the Coulomb scattering mechanism. On the other hand, from the splits of Hi group, it is very interesting to note that the TEOS buffer layer will not cause the mobility degradation, as shown in Figure 3.14(b). Figure 3.15 exhibits the distribution of the on-current (VG=1.8V, VD=1.8V) versus off-current (VG=0V, VD=1.8V). From the figure, we can find that the splits fabricated with the Hi-wafers possess lower off- current than the splits fabricated with the Cz wafers, due to inherently better surface
quality of Hi-wafers.