In this thesis, the effects of both the Si3N4 layer capping over the gate and the hydrogen-blocked TEOS buffer layer inserted prior to the Si3N4 deposition, on the NMOS device characteristics as well as the correlative hot-electron degradation were investigated. The devices were built on two kinds of the substrates, namely, Cz and Hi-wafers. Besides, the influences of the F channel implant on both fundamental performance and the related reliability of the fabricated devices were also explored.
Several important findings were obtained and summarized as follows.
(1) For devices on the Hi-wafer, the buffer layer would not degrade the device performance. For examples, the enhancement ratio of transconductance for the devices of SiN/Buffer/Hi split at a channel length of 0.5μm is 20%, comparable to 19% of the SiN/Hi split at the same channel length. On the contrary, the buffer layer for devices built on Cz wafers would degrade the performance. Enhancement ratio of transconductance for the SiN/Buffer/Cz split at a channel length of 0.5μm is lowered to 11% from 15% of the SiN/Cz split. Such disparity is attributed to the better surface quality of the Hi wafers. On the other hand, the F channel implant draws significant impacts on the device performance for devices built on Cz wafers, such as degradation of Gm and S.S. When Hi wafers were used as the starting substrates, such negative impacts could be relaxed. These findings highlight the merits of Hi wafers over that of Cz wafers.
(2) The thermal budget associated with the deposition of the Si3N4 capping layer could help redistribute the segregated boron dopants in the channel and alleviate the reverse short-channel effect, although the poly-depletion effect becomes worse. The
bandgap narrowing effect due to the channel strain may result in further lowering in VTH as the channel length is shortened.
(3) The TEOS buffer layer could effectively block the diffusion of hydrogen species from Si3N4 into the channel and interface of Si/SiO2 during the Si3N4
deposition and subsequent thermal cycles.
(4) The hot-electron degradation is adversely affected when the Si3N4 capping layer is deposited over the gate as compared with the control samples, regardless of the types of wafers. When a TEOS buffer layer was inserted prior to the Si3N4
deposition, although still worse than the control ones, significant improvement in resistance to the hot-carrier degradation over that without buffer is achieved.
(5) The hot-electron degradation could be improved by the F channel implant. In this aspect, the Cz wafer-split with the F-implant possesses the most significant improvement in resisting the hot-electron degradation. This is ascribed to the stronger Si-F bonds at the interface by the OED effect for the Cz wafers, even the split with the worst fresh performance. This result implies the only demerit of the purpose of Hi-wafer when collocated with the F-implant.
In this work, we found that hydrogen species is the primary culprit for the aggravated reliabilities in the strained devices. The insertion of a buffer layer has been shown to be effective in this work to alleviate the associated hot-carrier degradation.
The usages of both Hi-wafer and F channel implant ought to be treated carefully to optimize both device characteristics as well as hot-carrier reliability. Optimization of Si3N4 deposition conditions, search of other suitable materials for buffer layer, and use of different wafer orientation are possible ways for further improving the characteristics of devices implemented with uniaxial channel strain.
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Wafer
F channel implant
Gate Buffer
Layer CESL Passivation Layer
W/O W/O
CZ
W/O
W/O Si3N4 3000 Å
Hi W/
N2O Oxide
22 Å
Undoped Poly-Si 2000 Å
TEOS 100 Å
Si3N4 3000 Å
TEOS 3000 Å
Table 2.1 Split table of buffer layer and CESL.
Fig. 1.1 Gate length scaling as a function of the year of introduction for technology node [2].