Results and Discussion
3.1 Basic Electrical Characteristics
3.1.1 Transfer Curves
Figures 3.1(a) and 3.1(b) show the transfer curves of the J-less and IM devices,
respectively. In Fig. 3.1(b), due to the existence of un-gated regions in the operation
of SG-1 mode [21], the electrical performance of the SG-1 mode for the IM device is
basically worse than that of the SG-2 mode. This issue is efficiently ameliorated when
adopting the J-less scheme as shown in Fig. 3.1(a). This is because the high doping
concentration in the channel of the J-less device tends to eliminate the impacts of the
un-gated regions stated above. In Fig. 3.1, moreover, the J-less transistor displays
more negative Vth values as compared with the IM one, owing to the adoption of the
same doping type with the S/D and the heavily doped channels (channel doping is
estimated to be around 1x1020 cm-3). In addition, because of the ultra-thin channel
(see Fig. 2.3), the J-less device can still be effectively turned off in all operation
modes despite the very high doping concentration contained in the channel. The
On/Off ratio can thus reach 106~107 which is higher than that of the IM device.
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With the two types of devices, it should be noted that there are some differences
in the conduction mechanisms. For the IM devices, the current mainly conducts
through the inversion layer formed near the interface between the channel and the
gate dielectric. However, it can be observed that the curves of the J-less devices
conspicuously shift to the left side (with more negative value of Vth), showing the
normally-on characteristics in Fig. 3.1(a). Unlike conventional IM devices that the on
current conduction is mainly restricted in the inversion layer close to the
channel/oxide interface, in J-less devices the major conduction is through the
quasi-neutral region inside the channel. For our fabricated N-type J-less devices, if the
gate bias is not sufficiently negative to effectively deplete the free carriers in the
ultra-thin channel, a high leakage current conducting through the inner quasi-neutral
region will remain. In this regard, DG mode [22] is more efficient since it depletes the
channel from the two sides. When it comes to gate coupling effect, as long as the
channel fin thickness is sufficiently thin, the device can be turned off effectively with
the adoption of DG configuration, even though the channel is heavily doped. For the
IM devices, the DG mode can strongly improve the gate controllability to form the
inversion layer and hence turn the devices on more effectively, and also enhance the
electrical performance obviously. For the J-less devices, the DG mode can use the two
gates simultaneously to deplete the channel and therefore turn the devices off more
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effectively, leading to a smaller S.S. and a larger Vth than those in the SG modes.
In Figs. 3.1(a) and 3.1(b) we can also compare the S.S. characteristics under
three operation modes for the two types of devices. For the IM devices, the SG-1
mode shows the worst S.S. among the three modes. This is because of the existence of
un-gated regions as operated under the SG-1 mode as mentioned before. Nevertheless,
for the J-less devices, the high doping concentration in the channel tends to reduce the
impacts from the un-gated regions stated above. Therefore, the gate controllability of
the SG-1 mode is improved for the J-less devices, which is less affected by the
un-gated regions. Ion of the SG-1 mode is also obviously improved and becomes
comparable to those of the other two modes.
3.1.2 Output Characteristics
Figure 3.2 shows the significant performance enhancement made by the J-less
device over the IM one. For the J-less devices, the on-state current conduction occurs
essentially through the whole channel layer rather than the regions close to the
channel surface as the IM devices do [22]. As can be seen in the figure, the J-less
device can provide about 333% enhancement of saturation current at Vg-Vth = 3 V and
Vd =5 V over the IM one.
When it comes to the S/D resistance, it can be extracted from the Id-Vd curves of
the two types of devices under the DG mode. In Figs. 3.3(a) and (b), we can observe
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the total resistance ( ) as a function of the channel length of both devices.
Here we can extract the S/D resistance from the intercept of the y-axis of the plots.
Owing to the extra implantation which can reduce the S/D resistance of the J-less
devices, the S/D resistance of the J-less devices is about 69 kΩ, just a little smaller
than 73 kΩ of the IM devices. Moreover, the channel resistance can be figured out by
subtracting the S/D resistance from the Rtotal, and Fig. 3.4 shows the results for both
devices. Because of the heavily doped channel of the J-less devices, the channel
resistance (96 ~146 kΩ/μm) is smaller than that of the IM devices with the un-doped
channel (169 kΩ/μm).
3.1.3 Basic Difference of both Devices
Figure 3.5 shows the S.S. characteristics of the three operation modes for both
devices with channel length of 2μm. Thanks to the ultra-thin channel in our fabricated
devices, the S.S. can be about 140 mV/dec for both the IM and the J-less devices
under the DG mode. But for the J-less devices, owing to the heavily doped channel,
the S.S. under the SG-1 mode and SG-2 mode is worse than that under the DG mode.
It is interesting to see that, if we compare the S.S. under the SG-2 mode of the J-less
devices with that of the IM devices, the S.S. under the SG-2 mode of the J-less
devices are much more worse than that of the IM devices. This indicates the present
DG structure is even more beneficial for the operation of the J-less scheme.
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Figure 3.6 compares the Vth roll-off effect of the fabricated J-less and IM devices.
It can be seen that the J-less transistors perform worse than the IM counterparts. Such
a phenomenon can be expounded from the concept of the difference in the effective
oxide thickness (EOT) between the two types of devices. Fig. 3.7 is the schematic
illustration of the conducting current paths under the DG mode of the two types of
devices [23]. As mentioned before, for the IM devices, the conducting current takes
place along the inversion layer induced near the interfaces between the channel and
the gate dielectric. In contrast, the major conduction region in the J-less transistors is
away from the oxide/channel interface. With this concept, there is an additional gate
dielectric component contributed by the surface depletion layer in the channel of the
J-less devices, leading to an increase in the EOT. Consequently, with the same gate
oxide thickness, J-less transistors have thicker EOT and therefore Vth roll-off effect
becomes more significant [24]. Fig. 3.8 schematically shows the situations of
depletion and conduction regions in the channel of the J-less device operated under
SG or SG mode at Vg ~Vth. Since Vth is determined with the constant current scheme,
thickness of the conduction (quasi-neural) region for the two modes should be
comparable. Thus for the SG mode it needs a thicker depletion region (at the
driving-gate side) than the DG modes to achieve the same current conduction at Vg
~Vth, as shown in the figure. Therefore the J-less devices have poorer gate
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controllability under the SG mode owing to the thicker EOT, resulting in the more
negative Vth over that of the DG mode (Fig. 3.1). The thinner EOT for the DG mode
also explains the S.S. improvement with the DG mode of operation shown in Fig. 3.5.