Gate Controllability

Figure 3.9 shows the transfer curves of the IM device and the J-less devices with

various channel doping concentration under the DG mode with channel length of 0.7

μm. It should be noticed that the Vth of the J-less devices becomes more negative as

the channel doping concentration increases. Such a phenomenon indicates that the

higher channel doping concentration the J-less devices have, the harder the J-less

devices can be effectively turned off at V_g = 0. In other words, for the J-less devices, a

more negative gate bias is necessary to deplete the channel and shut off the off-state

leakage current with the increasing channel doping concentration. Moreover, for the

J-less devices with higher channel doping concentration, the On/Off current ratio can

still reach 10⁶~10⁷ which is comparable to that of the IM devices (Off current here is

defined as the minimum of the drain current).

Figure 3.10 shows the V_th characteristics as a function of channel doping

concentration for the fabricated devices under the DG mode. The data for each

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specific condition were measured from 10 devices with channel length of 0.4 μm. As

mentioned above, the Vth characteristics become more and more negative as the

channel doping concentration of the J-less devices increases. Moreover, the Vth

fluctuation also gets much larger with the increasing channel doping concentration, in

contrast to the results the IM devices exhibit. This is because the conduction

mechanisms for the J-less devices are distinctly different from those of the IM ones.

For the J-less scheme, the carriers are mainly concentrated in the channel center while

the channel surface is depleted [23]. The channel depletion layer would serve as an

extra gate dielectric layer and aggravate the gate controllability and Vth fluctuation.

More details and analysis will be discussed later.

Here we can use the TCAD simulation to analyze the differences in the

conduction mechanisms between the two types of devices. The simulation is based on

the assumption that the structures are with uniform doping concentration throughout

the channel and, for simplicity, the S/D series resistance is ignored for the J-less

devices [23]. The channel doping element is phosphorous at carrier concentrations of

5×10¹⁸ cm^-3, 8×10¹⁸ cm^-3, and 1×10¹⁹ cm^-3. The channel thickness is 16 nm while the

gate oxide thickness is 15 nm. Moreover, the work-function of the gate electrode is

assumed to be 4.17 eV, and here we ignore the quantum effects in order to simplify

the simulated condition. Also, the V_th is defined at the value of V_g as I_d is equal to 10

20

nA. Figs. 3.11(a) and (b) show the simulation results of the electron density along the

channel depth for the J-less devices with various channel doping concentration under

the DG and SG modes, respectively. As the gate overdrive equals 1 V, Fig. 3.11(a)

exhibits that the active electrons are concentrated in the central Si channel, and the

carrier concentration is more tightly distributed with the increasing channel doping

concentration. It means that with a higher channel doping concentration, the J-less

devices can offer more carriers at the same gate overdrive.

As mentioned before, the J-less devices exhibit the unique conduction

mechanism with conducting current flowing mainly through the channel body rather

than at the oxide/silicon interface, which is in strong contrast to that of the IM devices.

Moreover, Figs. 3.11(a) and (b) show distinct differences between the DG mode and

the SG one. In Fig. 3.11(b), it can be noticed that the peak of carrier density is moving

toward the interface with decreasing channel doping concentration under the same

gate overdrive. This is reasonable since under the DG mode the channel is depleted

from the two opposite sides of the channel and the side depletion regions tend to

widen and approach the channel center as the device is turned off, while under the SG

mode the depletion region is modulated by the driving gate bias from only one side of

the channel, resulting in the asymmetrical carrier distribution. For the SG mode with

lower channel doping concentration, such an asymmetrical carrier distribution is more

21

significant.

The Vth as a function of channel doping concentration under the DG mode is

given in Fig. 3.12 for devices with channel length of 2 and 0.7 μm. It can be seen that,

with channel length shortened from 2 to 0.7 μm, Vth drop is more significant for the

device with a higher channel doping concentration. To highlight this phenomenon,

Fig. 3.13 shows Vth as a function of channel length for J-less devices with channel

doping of 10¹⁹ and 10²⁰ cm^-3. The results indicate that as the channel doping

concentration is higher, the SCE for the J-less devices gets much worse, and the Vth of

the device becomes more sensitive to the channel doping, explaining why the

fluctuation becomes larger with increasing channel doping in Fig. 3.10. Such a

phenomenon can be expounded from the different ∆EOT concept between the two

types of fabricated devices mentioned in Chapter 3.1. For the IM devices, the

conducting current occurs along the inversion layer induced near the interfaces

between the channel and the gate dielectric. In contrast, the concentration peak of the

conduction carriers of J-less transistors is away from the interface and is located at the

center of the Si channel, as shown in Fig. 3.11(a). In this figure the electron density is

simulated as a function of Si channel depth with different channel doping

concentrations under the gate overdrive of 1 V under DG mode. The simulated

electron density for the same devices operated under SG mode is shown in Fig.

22

3.11(b) in which we can see that the peak carrier concentration varies with channel

doping concentration. Here, for simplicity, we define the extra EOT contributed by

the Si depletion layer as the average location of the electrons with respect to the Si

channel surface of the driving gate side, and can be calculated with the formula:

,

where Ne(x) is the number of active electrons as a function of location and x is the

location of the electrons with respect to the Si channel surface. Following the formula,

we can quantitatively acquire the contribution of the Si depletion layer to the EOT

which is related to the channel doping concentration, as shown in Fig. 3.11(b).

Fig. 3.14 shows the electron density as a function of depth of Si channel with the

channel doping concentration equaling 5×10¹⁸ (cm^-3) under the SG mode with gate

overdrive of 1 and 0.5 V. In this picture, we can observe that not only the height of

peak of the carrier density but also its location depend on the gate overdrive condition

as operated under SG mode. Here we define the displacement of the peak of the

carrier density with gate overdrive varies from 1V to 0.5 V as ∆EOT, i.e.,

23

By the way, because of the differences of dielectric constant between the Si and SiO2,

the EOT is equal to one-third of the thickness of Si (or

T



EOT

3.16, we also take the consideration mentioned above into account.

Fig. 3.15 demonstrates the ∆EOT as a function of channel doping concentration,

revealing that the more heavily doped channels the J-less devices have, the smaller

∆EOT the devices possess. In brief, the location of the peak of the active electrons in

the channel of the J-less devices with higher channel doping concentration is less

affected by the gate overdrive condition. In other words, we can extrapolate that the

J-less devices with lower channel doping concentration possess better gate

controllability since they can more effectively modulate the depletion region with

varying gate overdrive. Since the EOT of the Si depletion layer is always high and

less dependent of the gate overdrive, the much severer fluctuation of the J-less devices

with higher-doping channel shown in Fig. 3.10, as well as the more severe SCE

exhibited by the J-less devices with higher channel doping concentration in Fig. 3.10

becomes reasonable.