CHAPTER 1 INTRODUCTION
2.2 CMOS READOUT TECHNIQUE FOR IR IMAGE
The IR FPAs system can be separated into two important parts which are the readout circuit electronics and the IR detector array. Readout electronics is deigned to support a good interface between IR detector and the following signal processing stage. The performance of the entire IR image system will be bad if the readout circuit is not well designed. For specific IR FPAs with different materials and structures, different circuit techniques have been discussed. The readout circuit techniques based on silicon CMOS VLSI technology will be discussed in the following discussed.
Recently, the trend of developing IR image system is the reducing pixel pitch with increasing array size and higher resolution. Moreover, the total power dissipation of the entire IR FPA system is limited with different applications. With the elements mentioned above, there are two major factors often put constraints on circuit design space and circuit complexity. Thus the design of IR FPA readout electronics requires a trade-off between circuit performance and complexity.
Some simple readout structures like source-follower per detector (SFD), direct injection (DI), and gate-modulation input (GMI), are still commonly used in large staring IR FPAs because of the small pixel area and power consumption. In addition, more complex circuit techniques like buffered direct injection (BDI)] and buffered gate modulation input (BGMI)
have been developed to improve the important parameters of the IR image system such as excellent bias control, high injection efficiency, linearity, and noise performance. Simple and high-performance circuit techniques have been a challenging work in the design of readout circuits for IR FPAs.
In the following section, some of the commonly used CMOS readout techniques as well as the state-of-the-art structures will be reviewed.
1) Source-follower per Detector [13]:
A simple readout circuit called the source-follower per detector (SFD) is shown in Fig.
2.3 where a NMOS source-follower composed by MNI and MNL, a PMOS gate M-Rst as the reset path, and a multiplexing NMOS device M-Sel as the selection control switch are used in each cell. The integration capacitance is the summation of detector shunt capacitance Cdetector
and all the parasitic capacitance from the input node to ground of the SFD. The integration capacitor is reset to high by the reset MOS M-Rst then discharged by the photocurrent Idetector. After one integration period, the cell voltage signal is sampled to the output stage serially through the device M-Sel controlled by the clock Select. The simple structure of the SFD makes it suitable for the applications of high density, large format, and low power IR FPA.
However, since the photon excited carrier charges are integrated on the input node capacitance of the detector directly, the detector bias voltage changes through integration. It can result in variations of detector characteristics and non-linearity of readout current, which limit the application of SFD. Moreover, the SFD is susceptible to KTC noise induced by the integration-and-reset function and fixed pattern noise (FPN) caused by the process-dependent threshold voltage variations. Usually, a correlated double sampling (CDS) stage is used to reduce the KTC noise of the SFD readout circuit.
IR Detector Cdetector
Ietector
Reset M-Rst Vdd
Vbn
MNI
MNL
Select
M-Sel To output stage
Vdetector
Fig. 2.3. The source follower per detector (SFD) readout circuit.
2) Direct Injection [14]:
Another simple readout circuit called the direct injection (DI) is shown in Fig. 2.4. In the DI circuit, a common-gate PMOS device MDI is used to bias and sense the current photo of the IR detector. The detector current Idetector passing through the gate MDI is further integrated on the integration capacitor Cint which can be reset by the NMOS device M-Rst. The integrated voltage on Cint is sample to the output stage through the PMOS source follower MPI and the multiplexing device M-Sel controlled by the clock Select. In the DI circuit, a better bias control than the SFD during integration is supported by the common gate device MDI. Like the SFD circuit, the DI circuit has a simple structure and no active power dissipation. This makes it suitable for high-density IR FPA applications. The injection efficiency of a readout circuit is defined as the ratio of the current flowing into the readout circuit to the detector photocurrent Idetector. The injection efficiency of the DI is determined by the ratio of detector shunt resistance to input resistance of MDI. Thus a lower input resistance
means a higher injection efficiency and better detectivity. Since the input resistance of the PMOS device MDI is proportional to its overall current including the background current level.
Thus, the DI is not suitable for the applications of low-background IR image readout.
Moreover, a stable and low noise dc bias VDI is needed in the DI circuit. Both threshold voltage non-uniformity and KTC noise are still problems of the DI readout circuit.
IR Detector
Ietector
Vdetector
Cdetector
VDI
MDI
Reset M-Rst Cint
MPI
Select
M-Sel To output stage
Fig. 2.4. The direct injection (DI) readout circuit.
3) Buffered Direct Injection [15]:
A more complex readout circuit called the buffered direct injection (BDI) circuit is shown in Fig. 2.5 where the circuit structure is similar to the DI except that an additional inverted gain stage with the gain -A is connected between the gate node of the common-gate input device MBDI and detector node. The input impedance can be decreased by a factor of A due to the negative feedback structure. Thus, the injection efficiency is increased to near unity.
Usually, the inverted gain stage can be implemented by differential pair or inverter. The detector bias control of the BDI is more stable than those of SFD and DI due to the virtual-short property of the gain stage. Besides, the source voltage of MBDI can be tuned by adjusting Vcom, thus the bias of the IR detector can be turned to get a stable photo current.
Moreover, both equivalent input referred noise and operational bandwidth can also be
improved as compared to the DI circuit by this inverted gain stage. Since the detector bias is controlled by the input voltage Vcom of the differential pair instead of VDI and gate-to-source voltage of MDI in the DI circuit, both threshold voltage non-uniformity problem and strict low-noise bias requirement of the DI are immune. However, the additional gain stage consumes active power during integration. For large size IR FPA system, this additional power will be a problem. This additional power loading can be reduced by proper design of the gain stage with low bias current. The photo current through MBDI flows into Cint and transferred to voltage, then sampled to the output stage by MPI and MSEL with control signal controlled Select. Generally, the BDI is suitable for those applications which require high readout performance and can afford additional circuit complexity, chip area, and power dissipation.
IR Detector
Ietector
Vdetector
Cdetector
MBDI
Reset M-Rst Cint
MPI
Select
M-Sel To output stage -A
Vcom
Fig. 2.5. The buffered direct injection (BDI) readout circuit.
4) Gate Modulation Input [16]:
The conventional gate modulation input (GMI) structure is composed with the IR detector, a current mirror which mirrors and amplifies the photo excited current and a integration capacitance Cint as shown in Fig 2.6. The detector absorbs the infrared flux and generates photo current. The photo excited current flows into Mload of the current mirror and amplified by Minput. The amplified current then flows into the integration capacitance and
transferred it to output voltage.
The effective injection efficiency ( or current gain ) AI.GMI of this structure which is the current ratio between the drain current of the input MOSFET of the current mirror (Minput) and the drain current of the load MOSFET multiplies ηinj.DI which is the injection efficiency of the direct injection (DI) readout structure, and the detector bias VD can be expressed as:
A I where gm.input is the transconductance of the input MOSFET Minput under input background current bias as well as the gm.load, RD is the detector shunt resistance, Vsub is the detector N-node bias (N-on-P type PV detector), VGS.Mload is the gate-to-source voltage under input background current bias, and Vsource is the external adjustable source node voltage. The current Iload and the gate-to-source voltage VGS.Mload of the load device Mload can be expressed as where Kload is the transconductance parameter of the MOS device and VT is the threshold voltage of Mload. From eqs. (2.7) and (2.9), the detector bias VD can be expressed as It is shown from Eq. (2.10) that the detector bias is sensitive to the adjustable source voltage Vsource noise and threshold-voltage variations. Since the detector shunt resistance RD is sensitive to the detector bias VD, the injection efficiency is also sensitive to Vsource and
threshold voltage variations as may be seen from Eqs. (2.6) and (2.7). To obtain a stable injection efficiency, a strict control on both Vsource and threshold voltage uniformity is required.
Using Eqs. (2.8) and (2.9) and the relation VG.Minput = VGS.Mload + Vsource, the mirrored current Iinput can be represented as
( )
I K
K I
K
input input GS.Mload source T
input
Since the transimpedance gm = 2 KI , the transimpedance ratio between Minput and Mload is g range of several orders of magnitude depending on the IR detector background current. The smaller the current is, the higher the current gain. This means an adaptively controlled current gain. Moreover, the current gain also depends on ηinj.DI and Vsource. Thus the current gain can be additionally adjusted by Vsource.
However, it is shown in Eq (2.6) that the GMI circuit, like the DI readout structure, needs a large detector shunt resistance to achieve high injection efficiency and thus a high current gain. Since the injection efficiency is sensitive to Vsource and threshold voltage variations, so is the current gain. From Eqs (2.5) and (2.13), it can be shown that the GMI circuit is susceptible to fixed-pattern-noise due to threshold-voltage variations in the
transistors Mload and Minput causing the current gain to vary from one cell to another.To obtain a large total dynamic range in the GMI circuit, the current gain should be kept high and uniform. This leads to strict requirements on MOSFET threshold-voltage uniformity and extremely low noise of the dc bias Vsource which are difficult to control. From Eq (2.7), it is shown that the detector bias VD is sensitive to the existence of the noise of Vsource. If the detector bias is not identical from cell to cell, the photon excited current will not be stable.
Therefore, the performance of linearity will be bad.
IR Detector
To the output stage
Mninput Mnload
Vsource
Cint Vsub
Iinput Iload
Fig. 2.6. The gate modulation input (GMI) readout circuit.
From the discussion above, the properties of the GMI structure are obtained. The advantages are :
1) The current mirror amplifies the photo excited current, therefore the GMI can achieve high injection efficiency.
2) Due to the simple structure, the pixel pitch can be very small to extend the array size larger.
3) The current gain can be adjusted to suitable value according to the current level by the external adjustable Vsource
.
And the drawbacks of the GMI are :
1) The injection efficiency (or current gain) is affected by the threshold voltage variation and the noise of the adjustable Vsource, and the linearity is affected at the same time.
2) From eq (2.7), it is shown that the bias of the detector varies with the level of the excited photo current and the noise of noise of the adjustable Vsource. Therefore, the linearity will be affected by this factor.
5) Buffered Gate Modulation Input (BGMI) [17] :
The buffered gate modulation input (BGMI) structure is improved from GMI. Fig. 2.7 shows the circuit of BGM readout structure. The main differences from GMI are 1. the amplifier connected between the detector and the current mirror. The amplifier is connected as negative feedback type. By applying Vcom to the amplifier, the detector bias will keep stable to improve the linearity, 2. the current mirror with adaptive gain control and is not sensitivity to source noise.
The effective current gain AI.BGMI of the BGMI circuit, the injection efficiency of the SBDI readout structure , and V
ηinj.SBDI where A is the gain of the amplifier and Vcom is the common input bias. As may be seen from Eq (2.14), high injection efficiency can be achieved with a smaller RD requirement as compared to that in the GMI circuit. Moreover, the injection efficiency is not sensitive to threshold voltage variations and noise of the source bias voltage. The detector bias VD is independent of the MOS threshold voltage and any source bias voltage as in Eq. (2.16).
Besides, VD is adjustable by adjusting Vcom. Unlike the GMI circuit, the threshold non-uniformity and source-bias-voltage noise have no effect on the detector bias.
As seen from Eq. (2.14), the current gain is equal to the transconductance ratio between Minput1 and Mload1. To increase the current gain, gm.input1 should be larger than gm.load1. To achieve this without any external bias voltage, shorter channel length is used in Minput whereas narrower channel width is used in Mload. Due to short-channel and narrow width effects, the threshold voltage of Mload1 is greater than that of Minput1. With the arrangement of∆VT, the transconductance ratio in Eq. (2.14) can be similarly derived as
g
The threshold voltage difference ∆VT is geometry dependent and thus is very stable.
From Eq. (2.17), the current gain increases as the load current increases and decreases while as the load decreases, therefore achieve the adaptive current gain control. Unlike the GMI structure, no strict source bias voltage control is required in the BGMI circuit. The current gain of BGMI circuit is immune to threshold non-uniformity and noise of the source bias voltage. This high front-stage current gain makes the downstream circuit and system noise contribution extremely low. It results in a low input referred noise. Moreover, BGMI circuit can operate with a larger integration capacitance compared to DI and BDI and still obtain low noise performance and high charge detection sensitivity.
The integration capacitance is connected to the input MOSFET Minput through a row select device. In the integration period, the drain voltage of Minput will not be identical.
Therefore, the current gain of the current mirror will not keep constant, thus the linearity decrease. Besides, the integration capacitance is shared for each column, the value of the capacitance should be chosen large to eliminate all the parasitic capacitance of the connecting node of the integration capacitance and all the row select switches. With the larger value of integration capacitance, the readout rate decreases.
From the discussion above, the characteristics of BGMI are obtained. The BGMI not only keeps the advantages of GMI such as high injection efficiency, low noise, but also has more benefits like fixed detector bias control and adaptive gain control. However, this structure still suffers from some problems such as: the variation of current gain due to the voltage on the integration and the limited readout rate.
+ -Vcom A
SENSOR
Mnload Mninput
Mpbuff
To the shared integration capacitor cell Vsub
Iload
Iinput
Fig. 2.7. The buffered gate modulation input (BGMI) readout circuit.
Chapter 3
ARCHITECTURE AND CIRCUIT DESIGN
3.1 THE IMPROVED BUFFERED GATE MODULATION INPUT (BGMI)
In order to design a high performance readout chip to combine with the detector array developed by Chunghwa Telecom Lab, an improved buffered gate modulation input (BGMI) structure is proposed. The whole IR image system will operate in room temperature. The proposed improved BGMI not only keeps the benefits of the conventional GMI and BGMI structure such as high injection efficiency, low input referred noise, small pixel pitch, but also solves the problems of these structures. There are two major parts of the readout circuit, the analog circuits and the digital control circuits. The design of the circuits will be discussed in the following sections.
3.1.1 Analog Circuit
Fig 3.1 shows the architecture of the analog circuits. The analog circuits are the main signal processing stage. There are three important parts of the analog circuits in the proposed structure which are: the unit cell, the correlated double sampling (CDS) stage and the dynamic discharge output stage as the common output stage. The negative feedback amplifier is separated into two parts: half of the amplifier is shared by each row as the common left half and the other half is contained in every single pixel. By this arrangement the chip area and the power dissipation will decrease. Every unit cell will combine with the detector by an indium bond. When the detector absorbs infrared flux, the photo-generate current flows into the
current mirror in the unit cell. Then the mirrored and amplified current flows into the integration capacitance and transferred to voltage. The integrated signals from pixels in the same row are sampled to the CDS stages one row at one time controlled by the vertical row select logic. There are 64 CDS stages, each of them is shared by one column. The selected CDS signal is sampled to the common output stage column by column.
64 x 64 unit cells with BGMI circuit 1 x 64 shared CDS stage Common
Fig 3.1 The architecture of analog part in the improved BGMI readout chip
3.1.1.1 The Unit Cell
Fig 3.2 shows the unit cell combines with the common left half. The amplifier is connected as negative feedback type; therefore the bias voltage of the detector is fixed and is adjustable by adjusting Vcom. Besides, as the conventional BGMI structure, the applying of the amplifier makes the injection efficiency increase substantially as mentioned in chapter 2.
The input referred noise of the input stage as shown in Fig 3.3 is given by the superposition of the OP input gate referred noise voltages en12
and the noise voltage of the
VDD
Fig 3.2 The unit cell in the improved BGMI
The input referred noise current generated by en22 is
2
The gate referred noise voltage source of a MOSFET can be represented as [19]
The transconductance of MOSFET is proportional to its operation current. By minimizing the device sizes of the OP stage, the total input referred noise is very small.
Therefore the noise performance will be good.
+
Fig 3.3 The noise model and equivalent circuit of the improved buffered gate modulation input (BGMI) stage
In the conventional BGMI, the input MOS of the current mirror is connected to the integration capacitance directly. During the integration period, the voltage of the integration capacitance is not constant; this means the drain to source voltage of the input MOSFET varies with time. Therefore, the current gain of this current mirror will not be constant during the integration period. This effect comes from the Early effect and the linearity of this system will be lower down by this effect. In the improved BGMI structure, high swing cascode current mirror is used to eliminate the Early effect. With proper design of sizes of the devices
In the conventional BGMI, the input MOS of the current mirror is connected to the integration capacitance directly. During the integration period, the voltage of the integration capacitance is not constant; this means the drain to source voltage of the input MOSFET varies with time. Therefore, the current gain of this current mirror will not be constant during the integration period. This effect comes from the Early effect and the linearity of this system will be lower down by this effect. In the improved BGMI structure, high swing cascode current mirror is used to eliminate the Early effect. With proper design of sizes of the devices