CHAPTER 3 ARCHITECTURE AND CIRCUIT DESIGN
3.2 THE IMPROVED BGMI CHIP OPERATION
C
4 C
5 C
6 C
Start of Frame Signal
Fig 3.10 The trigger in the improve BGMI readout chip
3.2 THE IMPROVED BGMI CHIP OPERATION
The total architecture is shown as Fig 3.11.The clock timing waveforms of the column start signal, row select clock, and column select clock and clamping control Vclamp are shown in Fig. 3.12 where the clock signal has a high level of 3.3V and a low level of 0V. The readout operation of the BGMI chip is described below. When the start-of-frame signal is on, the first row is selected and the first column select Vcsel is on, the integration voltages of the unit cell input stages of the first row are switched to the CDS stages. After an integration time controlled by the reset signal, the voltage signal of the first column in the first row is sampled to the common output stage. The integration capacitor is reset immediately after it is sampled.
Then the second pixel of the first row is read out serially. After all pixels in the first row have been readout, the second row is switched to the common output stage. After the Nth column of the Nth row is selected, the12-stage counter signal is invited to form the second start-of-frame signal which the second frame starts to be readout.
The 64 x 64 improved BGMI readout chip is designed and all the simulation results are presented in chapter 4.
64x64 unit cells with BGMI circuit
Fig 3.11 The total architecture of the improve BGMI readout chip
.
Fig 3.12 The total control clock of the improve BGMI readout chip
CHAPTER4
SIMULATION RESULTS
4.1 LAYOUT DESCRIPTION
The layout of the entire is shown as in Fig 4.1. The total chip area is 3.5 x 3.6 mm2. The analog circuits including 64 x 64 unit cells with pads, 64 x 1 common left half circuits, 1 x 64 CDS stages, and a common output stage. The digital including 12-stage counter, row select logic, column select logic and trigger. The layout of unit cell is shown as Fig 4.2. There is a pad in each pixel to bond with the IR detector. There are pads around the 64 x 64 unit cells.
These pads are connected to the substrate of the detectors and applying a substrate bias to fix the detector bias.
12-Stage
counter Column select logic
1 x 64 CDS Dynamic
Output stage
64 x 64 Unit Cell Row
Select Signal
Fig 4.1 The Layout of the 64 x 64 improved BGMI
Unit Cell : 30 x 30 um2
8 fF Integration Capacitance
Fig 4.2 The Layout of the unit cell in the improved BGMI
4.2 POST-SIMULATION RESULTS
In order to show how the Early effect effects the current gain of the current gain, a comparison of pre-simulation current gain between the simple current mirror used in GMI and the high swing current mirror used in the improved BGMI as shown in Fig 4.3.
Fig 4.4 shows the voltage of the integration capacitance and Fig 4.5 shows the output voltage of the common output stage. Fig 4.6 shows the linearity of the output voltage. In order to observe how the process variation effect the linearity, the linearity of different corners is shown in Fig 4.6
The summary of the 64 x 64 improved BGMI readout chip is show as Table 4.1.
Current Gain of different current mirror
6 6.6 7.2 7.8 8.4 9 9.6 10.2 10.8 11.4 12
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 Voltage of Integration Capacitance (V)
Current Gain
sigle stage current mirror two stage current mirror
Fig 4.3 The comparison of current gain of different current mirror structure
Fig 4.4 The voltage on the integration capacitance
Fig 4.5The output voltage of the common output stage
Output Voltage Linearity : 99.98%
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n Input Photo Current (nA)
Voutput (V)
Fig 4.6 The linearity of the output voltage.
Voutput of Different Corners
0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n Photo Current (nA)
V out put (V )
SS FF SF FS
Fig 4.7 The linearity of the output voltage of different corners
Technology TSMC 0.35 um 2P4M CMOS
Power Supply 3.3 V
Pixel Pitch 30 x 30 um2
Integration Capacitance 8f F
Maximum Output Swing 0.75 V
Linearity 99.98 %
Power Dissipation 25 mW
Maximum Readout Rate 10 MHz
Frame Rate 2.44k frame/sec
Table 4.1 The summary of the 64 x 64 improved BGMI readout chip
4.3 DISCUSSIONS
The current gain of the high swing cascode current mirror is more stable than the current gain of the simple current mirror as shown in Fig 4.3. In order to reduce the chip area, the device size of the reset MOS, Mpreset and the row select switches are chosen very small.
Therefore at the beginning of the integration period, the integration voltage has a nonlinearity phenomenon for a short time due to the clock feedthrough of the reset clock. And the voltage drop of the row switches will be large. Therefore the maximum output voltage swing will be small. The proposed improved BGMI can achieve high linearity as shown in Fig 4.6.
CHAPTER5
CONCLUSION AND FUTURE WORKS
5.1 CONCLUSION
The improved buffered gate modulation input (BGMI) is proposed, designed and simulated. It contains a high swing cascade current mirror to increases the output range. Due to the cascode topology, the current gain is nonsensitivity to the Early effect, therefore the current gain is fix during the integration period. There is an integration capacitance in every pixel to increase the readout rate. The output stage is composed by correlated double sampling (CDS) stage and dynamic discharge output stage. The designed dynamic discharge output stage is a common output stage, and controlled by specific clock to increase the readout rate and save the power dissipation. The circuit has been designed with TSMC 0.35 µm double-poly-quadruple-metal CMOS process. The chip area is 3500 x 3600 µm2 and includes 4096 pixels. The area of a single pixel is 30 x 30 µm2. The linearity from post simulation can achieve more than 99%, and the power is 25mW.
5.2 FUTURE WORKS
The proposed improved BGMI is well simulated and will be fabricated and measured.
After the measurement of the 64 x 64 improved BGMI readout chip, the larger array size, higher readout rate and larger operation range will be designed base on the data.
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