C OMPARISONS OF S IMULATION T IME

After finishing the circuit simulation and RF/Baseband co-simulation, the

simulation time comparisons are presented. Figure 4.16 shows the comparisons of the circuit simulation time, the simulation time of the proposed behavior model are less than transistor level. Figure 4.17 shows the comparisons of the simulation time of the RF/Baseband co-simulation, the behavior model could save about 93% simulation

time compared with the transistor level. Therefore, the proposed behavior model could save a lot of simulation time.

15.25

HB HB_Pin HB_Vdd HB_Freq TRAN LSSP

Transistor Level Behavior Model

Figure 4.16 Comparisons of circuit simulation time.

174926.1

Figure 4.17 Comparisons of simulation time of RF/Baseband simulation.

Chapter 5

Conclusions and Future Works

5.1 Conclusions

This thesis presents an on-chip Class-E PA implemented in UMC 0.13-µm

CMOS technology. Instead of the RF choke, the proposed design uses the finite dc-feed inductor technique for suitable implement in a single chip. In order to obtain higher output power, increasing the supply voltage (VDD) by the cascode topology is successful. The efficiency could be improved by tuning out the parasitic capacitor between two transistors, M1 and M2. The proposed Class-E PA achieves power added efficiency (PAE) of 48.4 % while delivering 21 dBm output power with the input driving power of -3 dBm at 2.5 GHz. In the design band, 2.3 GHz ~ 2.7 GHz, PAE is still above 44 %. The simulation time of RF/Baseband co-simulation could be reduced about 93% by the proposed behavior model.

5.2 Future Works

For the future works, the behavior model of the Class-E PA can be further

improved for the RF/Baseband co-simulation. And it also can be used in investigating

the effect of the loading network of the Class-E PA on polar transmitter to try to find out what kind of loading network of Class-E PA is suitable for polar transmitter.

Appendix 1

Analysis of Ideal Class-E PA with Finite DC-Feed Inductor

In [22], one of the first attempts was made to study finite dc-feed inductor. Some other relevant papers include [23] [24]. All these papers have something in common, the procedure of obtaining final circuit component values is either long, complex and iterative, and doesn’t provide a direct insight into the circuit design, or is too simplistic and not exactly. Practically, the design of the Class-E PA with finite dc-feed inductor is a transcendent problem from the mathematical point of view.

Therefore, the designer needs to iteratively figure out the system of equations for a certain set of input parameters to gain the final circuit component values. If any of the input parameters is changed, the calculation must be repeated from the beginning.

Thus, it is a tedious and extremely impractical procedure. The [8] propose another approach to this problem. The system of transcendent equations is numerically solved for a certain number of discrete points of an input parameter, and the obtained results are interpolated by the Lagrange polynomial. The polynomial interpolation provides adequate accuracy and can be used for any value of the input parameter on that

segment, if it performs with enough density of points on the segment of interest. In other words, it obtains clear and directly usable design equations for the Class-E PA.

The design parameters of the Class-E PA have presented in equations (1.1), (1.2) and (1.3). These equations are base on the Lck is RF choke. But in case of the Class-E PA with finite dc-feed inductor, these equations don’t hold anymore [8]. At the beginning of the design procedure, the designer could choose a value of inductance that he would like to use for the finite dc-feed inductor. Therefore, the reactance of this inductor is known, and it is given by

ck

dc

L

X = ω

(A.1)

On the other hand, an ideal Class-E PA provides a 100% DC-to-RF efficiency.

Therefore, the DC resistance that the circuit presents to the supply source is also known from the PA specifications, and is simply given as

out dd

dc

P

R V

2

=

(A.2) Depending on the

dc dc

R

X

ratio, the circuit parameters R, B and X will change their

value from those given in equations (1.1), (1.2) and (1.3) for the RF choke based Class-E PA. These three parameters have calculated by numerically solving the transcendent circuit equations for a number of different values of

dc dc

R

X

ratio. The

results of these calculations are given in Table A.1 [8].

Table A.1 Class-E PA elements as function of the

dc dc

R

X

ratio [8].

Figure A.1 Effect of the finite DC-feed inductor on the Class-E PA elements [8].

In order to obtain explicit design equations for the Class-E PA component values, [8] have used the Lagrange polynomial interpolation of the numerically obtained results. Finally, the new equations for Class-E power amplifier with finite dc-feed inductor are presented in the following equations.

If 1

<

(

= z

)

<

5 results in a higher load resistance in comparison to the case of RF choke. This effect makes the design of low-loss matching networks easier, since the designer typically needs to transform a standard 50 Ohm termination to the load resistance of several

Ohms. Furthermore, the excessive inductance X is also lower, and the shunt susceptance B is increased. This increase of the shunt susceptance is particularly useful, as it extends the maximum frequency limitation of the device imposed by its output capacitance.

Appendix 2

Behavior Model of Switched-Mode Transistor

•Step 1 – Ideal switch in ADS

ON Resistance

-1 0 1 2

-2 3

100 200 300 400

0 500

Vgg1

Id (mA)

Transistor Level Behavior Model

Figure A.2 Simulation results and Verilog-A code of step 1.

•Step 2 – Modify ON resistance at region of 0.3(V) < Vgg1 < 0.8(V),

where Vgg1 is Vbias1

-1 0 1 2

•Step 4 – Combine step 1, step 2 and step 3

-1 0 1 2

-2 3

100 200 300 400

0 500

Vgg1

Id (mA)

Transistor Level Behavior Model RMSE = 0.003 mA

Figure A.5 Simulation results and Verilog-A code of step 4.

Bibliography

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second edition, Cambridge University Press 1998.

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[11] L. R. Kahn, “Single-Sideband Transmission by Envelope Elimination and

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John Wiley & Sons, Inc., 1980.

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[18] Munir M. El-Desouki, M. Jamal Deen and Yaser M. Haddara, “A Low-Power CMOS Class-E Power Amplifier for Biotelemetry Applications,” Microwave Conference, 2005 Oct. European

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Vita

姓名 : 吳家岱 性別 : 男 籍貫 : 桃園縣

生日 : 民國七十二年四月三十日

地址 : 桃園縣龍潭鄉中興村中興路 388 號

學歷 : 國立交通大學電子工程研究所碩士班 2005/09~2007/06 私立中原大學電機工程學系 2001/09~2005/06

桃園國立陽明高級中學 1998/09~2001/06

論文題目 : RF CMOS Class-E Power Amplifier Design

射頻互補金氧半 E 類功率放大器設計

在文檔中 射頻互補金氧半E類功率放大器設計 (頁 62-0)