Simulation and Measurement Results

In the beginning, the DC measurement is performed. Unfortunately, a dc current is found at the gate of transistor M2, as shown in Figure 3.4. But M2 gate should not have dc current. So, some debug works is done after measurement. The reasonable answer could be due to the gate leakage current of MOS bypass capacitor. Since the 1.2V MOS bypass capacitors are used at each dc bias nodes. However, the bias voltage of M2 gate is 2.1V that exceeding the 1.2 V, which may cause the gate-oxide of the MOS bypass capacitor breakdown and produce leakage current at M2 gate.

Therefore, the circuit performances have severely degradation due to incorrect bias.

The measurement results of the P1 are list below.

•M

2

Gate Current v.s. M

2

Gate Voltage

0.5 1.0 1.5 2.0 2.5 3.0

0.0 3.5

500 1000 1500

0 2000

Vg2 (V)

Ig2 (uA)

m1 m1indep(m1)=

plot_vs(Ig2, Vg2)=191.300

3.4 (a)

3.4 (b)

Figure 3.4 M2 gate leakage current of (a) simulation result (b) from UMC document [19].

•Output Power & Power Gain & PAE v.s. Input Power

-10 -8 -6 -4 -2 0 2 4 6 8

-12 10

-5 0 5 10 15 20

-10 25

Pin (dBm)

P o u t (d B m )

3.5 (a)

-10 -8 -6 -4 -2 0 2 4 6 8

-12 10

10 15

5 20

Pin (dBm)

P o w e r G a in ( d B )

Simulation Measured

3.5 (b)

-10 -8 -6 -4 -2 0 2 4 6 8

-12 10

10 20 30 40

0 50

Pin (dBm)

P A E ( % )

3.5 (c)

Figure 3.5 Simulation results of (a) output power v.s. input power (b) power gain v.s.

input power (c) PAE v.s. input power.

•Pout & PAE v.s. Freq.

2.2 2.4 2.6 2.8

2.0 3.0

12 14 16 18 20

10 22

Frequency (GHz)

Pout (dBm)

Simulation Measured

3.6 (a)

2.2 2.4 2.6 2.8

2.0 3.0

10 20 30 40

0 50

Frequency (GHz)

PAE (%)

3.6 (b)

Figure 3.6 Simulation results of (a) output power v.s. operating frequency (b) PAE v.s. operating frequency.

•Output Power & PAE v.s. Vdd

1.0 1.5 2.0 2.5 3.0

0.5 3.5

0 5 10 15 20

-5 25

Vdd (V)

Pout (dBm)

3.7 (a)

1.0 1.5 2.0 2.5 3.0

0.5 3.5

-60 -40 -20 0 20 40

-80 60

Vdd (V)

PAE (%)

3.7 (b)

Figure 3.7 Simulation results of (a) output power v.s. supply voltage (b) PAE v.s. supply voltage.

Chapter 4

Behavior Model

To do the RF/Baseband co-simulation of the proposed on-chip Class-E PA with polar transmitter the behavior model is needed. In order to reduce the time of circuit simulation and system verification, behavior models are used in circuit simulation and RF/Baseband co-simulation.

4.1 Behavior Model of Class-E PA

In the modeling flow from [20], the RF modules can be divided into three parts:

input interface, output interface and G_m stage. We developed the behavior models of each part. Then circuit simulation and system simulation will be accomplished by these behavior models. In this chapter, the behavior model of Class-E PA without driver stage is for efficient and accurate RF/Baseband co-simulation. The modeling flow starts form the impedance networks and the switched-mode transistor.

4.1.1 Input and Output Matching

•Capacitor

Figure 4.1 (a) shows the capacitor model in UMC design kits documents and Figure 4.1 (b) is it equivalent circuit. The capacitor can be represented by series R, L and C.

Figure 4.2 shows the s-parameter simulation results of the behavior model and transistor level.

L Figure 4.1 Capacitor of (a) UMC model (b) it equivalent circuit.

2 4 6 8

Figure 4.2 Capacitor’s SP simulation results of behavior model and transistor level.

•Inductor

Figure 4.3 (a) shows the inductor model in UMC design kits documents and Figure 4.3 (b) is it equivalent circuit. The inductor can be represented by series R and L with parallel C. Figure 4.4 shows the s-parameter simulation results of the behavior model and transistor level.

L Figure 4.3 Inductor of (a) UMC model (b) it equivalent circuit.

2 4 6 8

Figure 4.4 Inductor’s SP simulation results of behavior model and transistor level.

•Input Matching

Figure 4.5 (a) and (b) shows the schematic and equivalent circuit of input matching.

Similarly, use the method above the behavior model of input matching can be achieved by capacitors, inductors and resistances. Figure 4.6 shows the s-parameter simulation results of the behavior model and transistor level.

L

Figure 4.5 Input matching of (a) schematic (b) it equivalent circuit.

2 4 6 8

•Output Matching

Figure 4.7 (a) and (b) shows the schematic and equivalent circuit of input matching.

Similarly, use the method above the behavior model of output matching could be achieved by capacitors, inductors and resistances. Figure 4.8 shows the s-parameter simulation results of the behavior model and transistor level.

Pin

Figure 4.7 Output matching of (a) schematic (b) it equivalent circuit.

2 4 6 8

4.1.2 Switched-Mode Transistor

Figure 4.9 Using ADS switch mode to be the switched-mode transistor model.

Because the operation of the transistor M1 is like a switch, it can not be modeled by a simple Gm stage. Hence, we use the switch model provide in ADS at first. Figure 4.10 shows the design procedure of the switched-mode transistor. Here, we have three thresholds, 0.3 V, 0.8 V and 1.8 V. When Vgg1 < 0.3 V and 0.8V < Vgg1 < 1.8 V, the ADS switch can be used to model it, as shown in Step 1. When Vgg1 > 1.8 V, the transistor’s operation region might be in the triode-region. Therefore, the turn on

resistance equation in triode-region MOSFET can be used to model it, as shown in Step 2. When 0.3 V < Vgg1 <0.8 V, we modify the parameter in step 1 to fit it, as shown in Step 3. Finally, we combine Step1 ~ Step 3, as shown in Step 4, to accomplish the behavior model of the switch-mode transistor. The comparisons of circuit simulation are shown in Figure 4.11.

-1 0 1 2

100 200 300 400 500 600 700

100 200 300 400 500 600 700

0 800

2.2E9 2.4E9 2.6E9 2.8E9

2.0E9 3.0E9

Figure 4.11 Comparisons of circuit simulation between transistor level and behavior model.

4.2 RF/Baseband Co-Simulation

For applying in a polar transmitter, the behavior model of the Class-E PA becomes

a three-port circuit, as shown in Figure 4.12. In order to do RF/Baseband co-simulation a simplified polar transmitter is presented, as shown in Figure 4.13.

And the behavior model used in RF/Baseband co-simulation excludes the transistor M2. Figure 4.14 shows the schematic of behavior model without transistor M2.

Because of RF/Baseband co-simulation in transistor level costs a lot of time, more the half month. Therefore, instead of using real passive components from UMC FDK model, inductors and capacitors, the ideal passive components in ADS to do RF/Baseband co-simulation. In other words, only the switched-mode transistor behavior model is used in RF/Baseband co-simulation.

Pin

Figure 4.12 The three-port circuit.

RF_Signal RF_Signal RF_Signal RF_Signal

RF_Signal Push into Info to read loc al information

Note:

Uplink Transmitter EVM Measurement WMAN OFDM:

WMAN_OFDM_UL_TxEVM.dsn

WMAN UL Signal Source RF

MeasEqn

n=if(0==fmod(Bandwidth,1750000)) then 8.0/7 elseif(0==fmod(Bandwidth,1500000)) then 86.0/75 elseif(0==fmod(Bandwidth,1250000)) then 144.0/125 elseif(0==fmod(Bandwidth,2750000)) then 316.0/275 elseif(0==fmod(Bandwidth,2000000)) then 57.0/50 else 8.0/7 endi EqnVar W MAN 802.16-2004

Design Information NetlistInclude MAC_Header={0XA2, 0X48, 0X22, 0X4F, 0X93, 0X0E}

PilotPN_Phase=PilotPN_Phase

Figure 4.13 Schematic of simple polar transmitter in ADS.

Behavior Model exclude M²

Vg1 Inc ludeFiles[6]=c or e_rf_v 112.lib.s cs tt Inc ludeFiles[5]=L130E_HS12_V241.lib.scs tt Inc ludeFiles[4]=pad_r f_v 112.lib.s cs typ Inc ludeFiles[3]=mimcaps _rf_v112.lib.sc s typ Inc ludeFiles[2]=io_r f_v 112.lib.s cs tt Inc ludeFiles[1]=l_cr 20k_rf_v111.lib.s cs ty p Inc ludePath= /home/dada/RFDE/UMC013FDK/Models /Spec tre

NETLIST INCLUDE

Figure 4.14 Schematic of behavior model without transistor M2.

The simulation results of RF/Baseband co-simulation are shown in Figure 4.15.

The conditions are 14 MHz bandwidths and 2.5GHz carrier frequency. Three different modulation signals are considered in the RF/Baseband co-simulation. The results show the root-mean-squared error (RMSE) is about 0.125 dB.

RF/Baseband Co-Simulation

-16.5 -16 -15.5 -15 -14.5 -14

16QAM 1/2 QPSK 1/2 64QAM 2/3

RMSE = 0.125 dB

E V M ( d B )

Transistor Level Behavior Model

Figure 4.15 Comparisons of RF/Baseband co-simulation.

4.3 Comparisons of Simulation Time

After finishing the circuit simulation and RF/Baseband co-simulation, the

simulation time comparisons are presented. Figure 4.16 shows the comparisons of the circuit simulation time, the simulation time of the proposed behavior model are less than transistor level. Figure 4.17 shows the comparisons of the simulation time of the RF/Baseband co-simulation, the behavior model could save about 93% simulation

time compared with the transistor level. Therefore, the proposed behavior model could save a lot of simulation time.

15.25

HB HB_Pin HB_Vdd HB_Freq TRAN LSSP

Transistor Level Behavior Model

Figure 4.16 Comparisons of circuit simulation time.

174926.1

Figure 4.17 Comparisons of simulation time of RF/Baseband simulation.

Chapter 5

Conclusions and Future Works

5.1 Conclusions

This thesis presents an on-chip Class-E PA implemented in UMC 0.13-µm

CMOS technology. Instead of the RF choke, the proposed design uses the finite dc-feed inductor technique for suitable implement in a single chip. In order to obtain higher output power, increasing the supply voltage (VDD) by the cascode topology is successful. The efficiency could be improved by tuning out the parasitic capacitor between two transistors, M1 and M2. The proposed Class-E PA achieves power added efficiency (PAE) of 48.4 % while delivering 21 dBm output power with the input driving power of -3 dBm at 2.5 GHz. In the design band, 2.3 GHz ~ 2.7 GHz, PAE is still above 44 %. The simulation time of RF/Baseband co-simulation could be reduced about 93% by the proposed behavior model.

5.2 Future Works

For the future works, the behavior model of the Class-E PA can be further

improved for the RF/Baseband co-simulation. And it also can be used in investigating

the effect of the loading network of the Class-E PA on polar transmitter to try to find out what kind of loading network of Class-E PA is suitable for polar transmitter.

Appendix 1

Analysis of Ideal Class-E PA with Finite DC-Feed Inductor

In [22], one of the first attempts was made to study finite dc-feed inductor. Some other relevant papers include [23] [24]. All these papers have something in common, the procedure of obtaining final circuit component values is either long, complex and iterative, and doesn’t provide a direct insight into the circuit design, or is too simplistic and not exactly. Practically, the design of the Class-E PA with finite dc-feed inductor is a transcendent problem from the mathematical point of view.

Therefore, the designer needs to iteratively figure out the system of equations for a certain set of input parameters to gain the final circuit component values. If any of the input parameters is changed, the calculation must be repeated from the beginning.

Thus, it is a tedious and extremely impractical procedure. The [8] propose another approach to this problem. The system of transcendent equations is numerically solved for a certain number of discrete points of an input parameter, and the obtained results are interpolated by the Lagrange polynomial. The polynomial interpolation provides adequate accuracy and can be used for any value of the input parameter on that

segment, if it performs with enough density of points on the segment of interest. In other words, it obtains clear and directly usable design equations for the Class-E PA.

The design parameters of the Class-E PA have presented in equations (1.1), (1.2) and (1.3). These equations are base on the Lck is RF choke. But in case of the Class-E PA with finite dc-feed inductor, these equations don’t hold anymore [8]. At the beginning of the design procedure, the designer could choose a value of inductance that he would like to use for the finite dc-feed inductor. Therefore, the reactance of this inductor is known, and it is given by

ck

dc

L

X = ω

(A.1)

On the other hand, an ideal Class-E PA provides a 100% DC-to-RF efficiency.

Therefore, the DC resistance that the circuit presents to the supply source is also known from the PA specifications, and is simply given as

out dd

dc

P

R V

2

=

(A.2) Depending on the

dc dc

R

X

ratio, the circuit parameters R, B and X will change their

value from those given in equations (1.1), (1.2) and (1.3) for the RF choke based Class-E PA. These three parameters have calculated by numerically solving the transcendent circuit equations for a number of different values of

dc dc

R

X

ratio. The

results of these calculations are given in Table A.1 [8].

Table A.1 Class-E PA elements as function of the

dc dc

R

X

ratio [8].

Figure A.1 Effect of the finite DC-feed inductor on the Class-E PA elements [8].

In order to obtain explicit design equations for the Class-E PA component values, [8] have used the Lagrange polynomial interpolation of the numerically obtained results. Finally, the new equations for Class-E power amplifier with finite dc-feed inductor are presented in the following equations.

If 1

<

(

= z

)

<

5 results in a higher load resistance in comparison to the case of RF choke. This effect makes the design of low-loss matching networks easier, since the designer typically needs to transform a standard 50 Ohm termination to the load resistance of several

Ohms. Furthermore, the excessive inductance X is also lower, and the shunt susceptance B is increased. This increase of the shunt susceptance is particularly useful, as it extends the maximum frequency limitation of the device imposed by its output capacitance.

Appendix 2

Behavior Model of Switched-Mode Transistor

•Step 1 – Ideal switch in ADS

ON Resistance

-1 0 1 2

-2 3

100 200 300 400

0 500

Vgg1

Id (mA)

Transistor Level Behavior Model

Figure A.2 Simulation results and Verilog-A code of step 1.

•Step 2 – Modify ON resistance at region of 0.3(V) < Vgg1 < 0.8(V),

where Vgg1 is Vbias1

-1 0 1 2

•Step 4 – Combine step 1, step 2 and step 3

-1 0 1 2

-2 3

100 200 300 400

0 500

Vgg1

Id (mA)

Transistor Level Behavior Model RMSE = 0.003 mA

Figure A.5 Simulation results and Verilog-A code of step 4.

Bibliography

[1] Thomas H. LEE, “The Design of CMOS Radio-Frequency Integrated Circuits,”

second edition, Cambridge University Press 1998.

[2] Frederick H. Rabb, Peter Asbeck, Steve Cripps, Peter B. Kenington, Zoya B.

Popovich, Nick Pothecary, John F. Sevic and Nathan O. Sokal, “RF and Microwave Power Amplifier and Transmitter Technologies – Part 2,” High Frequency Electronics, May 2003.

[3] Mazzanti, A.; Larcher, L.; Brama, R.; Svelto, F., ”Analysis of Reliability and Power Efficiency in Cascode Class-E PAs,” Solid-State Circuits, IEEE Journal of Volume 41, Issue 5, May 2006 Page(s):1222–1229

[4] N.O Sokal and A.D. Sokal, “Class E-A new class of high-efficiency tuned single-ended switching power amplifiers,” IEEE, JSSC, vol. SC-10, pp. 168-176, June 1975.

[5] FREDERICK H. REBB, “Idealized Operation of the Class E Tuned Power Amplifier,” IEEE, Transactions on Circuits and Systems, Vol. 24, pp. 725-735, Dec. 1977.

[6] Mihai Albulet, “RF Power Amplifiers,” Noble Publishing Corporation, 2001.

[7] Raab, F. H. “Effects of Circuit Variations on the Class E Tuned Power Amplifier,” IEEE JSSC, vol. SC-13 (April 1978): 239-247.

[8] D. Milosevic, J. van der Tang and A. van Roermund, “Explicit Design Equations for Class-E Power Amplifiers with Small DC-feed Inductance,” Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on Volume 3, 28 Aug.-2 Sept. 2005 Page(s):III/101 - III/104 vol. 3

[9] C. Yoo and Q. Huang, “A Common-Gate Switched 0.9-W Class-E Power Amplifier with 41% PAE in 0.25-μm CMOS,” JSSC, vol. 36, no. 5, May 2001.

[10] B. Razavi, “RF Microelectronic,” NJ, USA: Prentice-Hall PTR, 1998.

[11] L. R. Kahn, “Single-Sideband Transmission by Envelope Elimination and

Restoration,” Proc. IRE, Vol.40, pp. 803-806, July 1952.

[12] D. Su and W. Sander, “An IC for Linearizing RF Power Amplifiers Using Envelope Elimination and Restoration,” IEEE JSSC, Vol. 31, pp. 2252-2258, Dec. 1998.

[13] H. L. Kraus, C. W. Bostian, and F. H. Raab, “Solid State Radio Engineering,”

John Wiley & Sons, Inc., 1980.

[14] Nagle, P.; Burton, P.; Heaney, E.; McGrath, F.; “A Wide-Band Linear Amplitude Modulator for Polar Transmitter Based on the Conpect of Interleaving Delta Modulation,” Solid-State Circuits, IEEE Journal of Vol. 37, Issue 12, Dec.2002 Page(s):1748-1756.

[15] C.C. Ho, C.W. Kuo, C.C. Hsiao, Y.J. Chan, “A Fully Integrated Class-E CMOS Amplifier with a Class-F Driver Stage,” IEEE RFIC Symposium, June 2003.

[16] P. Luengvongsakorn, A. Thanachayanon, “A 0.1-W CMOS class-E power amplifier for Bluetooth applications,” Digital Object Identifier, Page(s): 1348-1351 Vol.4, TENCON 2003.

[17] H.S. Oh, T. Song, E. Yoon, C.K. Kim, “A Power-Efficient Injection-Locked Class-E Power Amplifier for Wireless Sensor Network,” IEEE Microwave and Wireless Components Letters, vol. 16, no. 4, April 2006.

[18] Munir M. El-Desouki, M. Jamal Deen and Yaser M. Haddara, “A Low-Power CMOS Class-E Power Amplifier for Biotelemetry Applications,” Microwave Conference, 2005 Oct. European

[19] UMC Design Kits document, L130E_HS12_V241.pdf

[20] C. D. Hung, W. S. Wuen, Mei-Fen Chou, and Kuei-Ann Wen, “A Unified Behavior Model of Low Noise Amplifier for System-Level Simulation,”

accepted by European Conference on Wireless Technology (ECWT 2006), Manchester, UK, Sep. 2006.

[21] UMC Design Kits document, L130E RFCMOS model v1.3p1.pdf

[22] R.E. Zulinski and J.W. Steadman, “Class E Power Amplifiers and Frequency Multipliers with Finite DC-Feed Inductance,” IEEE Trans. Circuits and Systems, vol. CAS-34, no. 9, pp. 1074-1087, September 1987.

[23] D.K. Choi and S.I. Long, “Finite DC Feed Inductor in Class E Power Amplifiers-A Simplified Approach,” 2002 IEEE MTT-S Microwave Symposium Digest, vol. 3, pp. 1643-1646, June 2002.

[24] M. Iwadare and S. Mori, K. Ikeda, “Even Harmonic Resonant Class E Tuned Power Amplifier without RF choke,” Electronics and Communications in Japan, Part 1. vol.79, no. 1, 1996.

Vita

姓名 : 吳家岱 性別 : 男 籍貫 : 桃園縣

生日 : 民國七十二年四月三十日

地址 : 桃園縣龍潭鄉中興村中興路 388 號

學歷 : 國立交通大學電子工程研究所碩士班 2005/09~2007/06 私立中原大學電機工程學系 2001/09~2005/06

桃園國立陽明高級中學 1998/09~2001/06

論文題目 : RF CMOS Class-E Power Amplifier Design

射頻互補金氧半 E 類功率放大器設計

在文檔中 射頻互補金氧半E類功率放大器設計 (頁 47-0)