Chapter 2 System Platform
2.3 Channel Model
There are many imperfect effects during transmitted signals through channel, such as Additive White Gaussian Noise (AWGN), carrier frequency offset (CFO), multipath, and so on. The block diagram of channel model is shown in Figure 2-4.
Figure 2-4: Block diagram of channel model
2.3.1 Additive White Gaussian Noise
Wideband Gaussian noise comes from many natural sources, such as the thermal vibrations of atoms in antennas, "black body" radiation from the earth and other warm objects, and from celestial sources such as the sun. The AWGN channel is a good model for many satellite and deep space communication links. On the other hand, it is not a good model for most terrestrial links because of multipath, terrain blocking, interference, etc. The signal distorted by AWGN can be derived as
( ) ( ) ( )
r t =s t +n t (2.3) Where ( )r t is received signal,
( )
s t is transmitted signal, ( )
n t is AWGN.
2.3.2 Multipath
Because there are obstacles and reflectors in the wireless propagation channel, the transmitted signal arrivals at the receiver from various directions over a
8
multiplicity of paths. Such a phenomenon is called multipath. It is an unpredictable set of reflections and/or direct waves each with its own degree of attenuation and delay. Multipath is usually described by two sorts:
A. Line-of-sight (LOS): the direct connection between transmitter and receiver.
B. Non-line-of-sight (NLOS): the path arriving after reflection from reflectors.
Multipath will cause amplitude and phase fluctuations, and time delay in the received signals. When the waves of multipath signals are out of phase, reduction of the signal strength at the receiver can occur. One such type of reduction is called the multipath fading; the phenomenon is known as “Rayleigh fading” or “fast fading.”
Besides, multiple reflections of the transmitted signal may arrive at the receiver at different times; this can result in inter symbol interference (ISI) that the receiver cannot sort out. This time dispersion of the channel is called multipath delay spread which is an important parameter to access the performance capabilities of wireless systems. For a reliable communication without using adaptive equalization or other anti-multipath techniques, the transmitted data rate should be much smaller than the inverse of the RMS delay spread. A representation of Rayleigh fading and a measured received power-delay profile are shown in Figure 2-5.
0 100 200 300 400 500
0 0.1 0.2 0.3 0.4 0.5 0.6
Time (ns)
Received Power
Instantaneous Impulse Response of TGn cnahhel E
Figure 2-5: Instantaneous impulse responses
2.3.3 System Clock Offset
9
The clock drift means the different between the sampling frequency of the digital to analog converter (DAC) and the analog to digital converter (ADC). Because of sampling frequency offset, even if the initial sampling point is optimized, the following sampling points will still slowly shift with time. This model is using compress sinc waveform to cause the clock drift effect, and its effect can be written as
( s) preADC( s)*sin ( s n)
s
nT T
R nT R nT c
T
= − Δ (2.4)
where RpreADC represents the ADC original output signal,Δ represents shift Ts sampling period and to get (R nT signal by convoluting the ADC original output s) signal and shifted sinc waveform. 錯誤! 找不到參照來源。6 shows the clock drift model effect. Initial can samples at optimum sampling points, then slightly incorrect sampling instants will cause the SNR degradation.
Figure 2-6: The SCO effect of 16-QAM modulation under SCO 50 ppm
10
Chapter 3
Timing Synchronization
3.1 Introduction
Timing synchronization plays an important role in the receiver design of OFDM.
The ADC is the first stage of baseband, so it dominates the receiving signal to noise ratio (SNR). To get the highest input SNR, the ADC is hoped to sample at the eye open position where it has the maximum signal power. However, there are symbol timing offset, sampling phase shift, sampling clock offset (SCO), and carrier frequency offset (CFO), that constitutes timing synchronization errors, so timing synchronization is necessary. The duties of the synchronization include packet detection, frame synchronization, timing synchronization, and frequency synchronization. The synchronization flow is shown in Figure 3-1. In this thesis, we will focus on timing synchronization. The FD synchronizer contains three parts:
Coarse SCO tracking, sampling phase acquisition, and pilot tracking for residual SCO.
Figure 3-1: The frequency domain timing synchronization flow
11
3.2 Coarse Sampling Clock Offset Tracking
3.2.1 Introduction
After RF down conversion and with SCO (δ) effect, all preambles and received datum (Rφ,k) are sampled by using a fixed clock phase (Φ) which may be not the ideal sampling phase, where k is the received datum index, as shown in Figure 3-2.
Figure 3-2: Received signals with phase error Φ
The phase error of received datum r[n] contains an initial constant phase offset (Φ0) between the transmitter and the receiver and the phase shift has constant increment proportional to subcarrier index (k) and SCO (δ) as the symbol index (n) increases.
[ ] = ( r) = ( ( + ) ) = (n⋅ t t+ t)
r n r nT r n 1 δ T r T n Tδ (3.1)
where T and t Tr are the transmitter and receiver sampling period, and n Tδ t is the sampling timing offset at the nth symbol signals.
In frequency domain, the received datum with the effect due to the sampling clock offset as shown in Eq. 3.2.
2
n,k n,k n,k
[ ; ] = X H δ +W
s u
j πnk T
R n k e T (3.2)
In the following chapter described two steps to find the SCO. The first step, the parallel cross-correlation is utilized to detect the symbol boundary of the received signal. The second step, the cross-correlation power of two STFs is utilized to
12
determine the SCO.
3.2.2 Parallel Cross-correlation
To consider the first position of the received STF, the parallel cross-correlation [13] is utilized to search for the locations of the STF which is corresponded to with the input signal, as shown in Figure 3-3.
Figure 3-3: The symbol boundary detection architecture
If the c = {c(0), c(1),…, c(N-1)} is Short Training Field (STF) with N samples.
To calculate the parallel cross-correlation of the received signal ( [ ; ]R n k ) and the known STF buffer ( [ ; ]c i k ) to be reference, the boundary correlation buffer (BCB) is designed by the ideal STF with cyclic shift like the Eq. 3.3.
1 2 3
2 1
STF(1) STF(2) STF(3) STF(N-2) STF(N-1) STF(N) ( ) STF(N) STF(1) STF(2) STF(N-3) STF(N-2) STF(N-1)
( ) STF(N-1) STF(N) STF(1) 4) 3) STF(N-( )
13
The frequency domain parallel cross-correlation power ( ( )P i ) can be obtained by
1
Due to the received signals are the most likely to the ideal STF with cyclic shift (ˆi) which the cross-correlation power (P i ) is the maximum. Then, the first ( )ˆ position of the received signals is determined as shown in Eq. 3.6.
{ }
ˆ arg max ( )
i = N P i (3.6)
Where the ideal STF with cyclic shift (C i k ) is the most likely to the received [ ; ]ˆ datum.
3.2.3 Coarse Sampling Clock Offset Tracking
The received signals are sampled by ideal sampling phase which the cross-correlation power is the maximum. However, the SCO results that the phase shifts (φn) has constant increment proportional to subcarrier index (k) and SCO (δ) as the symbol index (n) increase. From the relation between the cross-correlation power of the nth symbol (P in( )ˆ ) and the phase error (φn), it is clear that SCO causes cross-correlation power attenuation and phase shift in the received signals.
Hence, the proposed algorithm utilizes the relation between the correlation power and the phase error to estimate the phase error caused by SCO. SCO is estimated according to the phase differences between two adjacent symbols. Figure 3-4 show the proposed coarse SCO tracking flow.
C(i, k)ˆ
Figure 3-4: The flow of proposed sampling clock offset estimation
14
The algorithm includes 4 steps:
Step 1:
Utilize three ideal correlation powers to find an equation in two variables represented the relation between the cross-correlation power and the phase error. For enhance the similarity between the relation and the equation, we find four equations from ideal correlation powers, and average the coefficient of four equations,
ˆ 2
( )
P i =aφ +bφ+ c (3.7)
Where n is the received symbol index; ˆi is the cyclic shift of ideal STF.
Step 2:
Determine the phase error (φn) by substituting the correlation power into equation.
Estimate the SCO (δ) by utilizing the phase differences between two adjacent symbols divide the sampling interval, where Ts is the period of one symbol.
*
15
3.3 Sampling Phase Acquisition
3.3.1 Frequency Domain Timing Acquisition
This section introduces 1x sampling rate timing synchronization scheme [12].
After the parallel cross-correlation and the coarse SCO tracking, the symbol boundary is known, and the majority of SCO is compensated. However, the following signals are sampled by using a fixed clock phase which may be not the ideal sampling phase. The received datum with initial phase error (Φ0) can be obtained by Eq. 3.11.
( ; 0) = ( ) ( - ( + 0) ) and s 0∈ , | 0| 0.5≤
r n Φ x t δ t n Φ T Φ R Φ (3.11)
Where x(t) is the received signals before RF down conversion; δ(t) is the delta function; Φ0 is the sampling error; k is the subcarrier index. Then, the FFT is utilized to get the received signal in frequency domain.
- 2 the phase error. Due to the received signals which have the maximal cross-correlation power are sampled at the optimal phase.
The cross-correlation powers are utilized as timing detection (TD). The TD can be obtained by Eq.3.13.
ˆ 0
16
Figure 3-5: The proposed timing detection
The ADCM is utilized to control A/D to sample at different phase, as shown in Figure 3-6. The first STF is sampled at the initial phase [ ]φ0 th. Then, the phase controller adjusts the sampling clock with +π-phase changes by ADCM. After that the second STF is sampled at the phase [φ π0+ ]th.
Up-sampling 1st STF
Down-sample at initial phase Φ0
Next STF Up-sampling 2nd STF
Down-sample
Figure 3-6: The block diagram of frequency domain timing acquisition
The frequency domain timing acquisition determines the phase error (Φ0) on the relation between the TD and the phase error. The one of STF C i[ˆ−1; ]k and
[ˆ 1; ]
C i+ k which is closed to the received signals R k( ; )φ0 with phase error (Φ0) have the larger cross-correlation power than the other. When the phase error
0 [0 ~ ]
φ ∈ π means the STF C i[ˆ+1; ]k is more closed to R k( ; )φ0 than the STF
17 determine the phase shift as shown as Eq. 3.15.
( ) 1 determine the phase shift as shown as Eq. 3.16.
_ 2
Although the SCO in the received signals has been estimated and compensated using STF, still some residual SCO may exist. Residual SCO results in a slowly gradual phase shifts that are proportional to subcarrier indices. When the receiver operates for a long duration, the phase shifts still cause the sampling error and ICI, because the subcarriers are not orthogonal. The residual SCO estimation is inevitable in the OFDM systems.
The conventional SCO estimation methods [14] utilize the information of phase
18
differences between two pilots in two adjacent symbols to estimate the SCO.
However, the accuracy of SCO estimation using pilots is base on the CFR and the SNR. Therefore, the following method is tracking the gradual phase shifts Φ and maintaining the sampling phase by utilizing the ADCM to control A/D in low SNR rather than estimating the SCO accurately.
3.4.2 Pilot Tracking
The normalized sampling error is defined as Eq. 3.17 where Tr and T are the t transmitter and receiver sampling period respectively. From Eq. 3.2, the effect of received datum caused by residual SCO is obtained by Eq. 3.18.
r t
The proposed scheme is estimate the phase error by tracking the phase differences θ between the received pilots and the ideal pilot n k, X with the same n k, subcarrier index, the architecture as shown as Figure 3-7.
R(n; k )1
Figure 3-7: The architecture of pilot tracking scheme
19 symbol, as shown as Eq. 3.19. For decrease the effect of noise, the pilot tracking scheme averages the phase differences Δθn k,Δ each eight symbols.
After pilot tracking scheme, the sampling phase of ADC is expected that the sampling phase error is less than
8
As a result, the pilot tracking scheme estimates the phase differences Δθn k,Δ continually. When the phase differences ,
n k 8
adjust the A/D sampling phase 8
−π changes in following received signals.
Similarly, when the phase differences ,
n k 8
adjust the A/D sampling phase 8
+π changes in following received signals.
Therefore, the pilot tracking scheme maintains that the sampling phase error of ADC is less than
8 π .
20
3.5 Compensation
φn
φ0
8 φ π Δ = ±
Figure 3-8: The block diagram of compensation
There are various schemes to compensate SCO, such as utilizing the interpolation techniques to resample in discrete-time domain, or rotating the FFT outputs in frequency domain, or utilizing ADPLL, ADDLL to recover ADC sampling. In the proposed algorithm, we compensate sampling phase offset and SCO in time domain with the multiphase technique which are implemented by all-digital clock management (ADCM).
After sampling phase acquisition, the algorithm outputs estimation phase Φ0 to phase control to adjust the A/D sampling phase. Then, SCO estimation algorithm outputs a value of normalized sampling clock offset, as shown as Eq. 3.16, so we need a phase translator to get the phase offset φn correspond with the value of SCO, as shown in Eq. 3.22, where n is the data index and M is the number of multiphase.
r n t
n r t t
nT nT
nT nT n T n M
φ
φ δ δ
− =
= − = ⋅ ⋅ = ⋅ ⋅ (3.22)
In the aspect of pilot tracking, pilot tracking will output phase 8
±π to phase
control according to the relation between phase differences and Eq. 3.21. Finally, phase control combines the three phase shift to ADCM.
21
Chapter 4
Simulation Result
We use simulation to evaluate the receiver’s performance with the AWGN, multipath fading and sampling clock offset.
4.1 Simulation Platform
MATLAB is chosen as simulation language, due to its ability to mathematics, such as matrix operation, numerous math functions, and easily drawing figures. The major parameters are shown in TABLE IV.
Table 4-1 Simulation parameters
Parameter Value
MCS Set 20
Antenna No. 1
Modulation 16 QAM
Coding Rate 3/4
PSDU Length 2048 Bytes Carrier Frequency 60 GHz
Bandwidth 2.64 GHz
IFFT / FFT Period 48.48ns(128-FFT) Table 4-2: Simulation parameters
22
4.2 Simulation Result
As mention before, the multiphase generator is used to generate 16 phases between one clock cycles. In other word, the phase error 16 means that signal is delay one cycle, and the phase error 0 means that sign is at ideal phase. With different initial phase error and SNR=5, after timing synchronizer, the final phase errors are convergence into 2 phases, as shown in Figure 4.1.
Figure 4.1: PDF of sampling phase error
Figure 4.2 shows the root mean square error of sampling phase. No synchronization means without timing acquisition to fix the unknown phase error.
Those initial phase is random to generate and its RMS is about 4.5~4.8 (phase), one phase offset means the phase difference with
8
π in this simulation. The value of
RMS is decreasing with the increasing of SNR and converges to 1.3 phases after timing acquisition with 400 ppm SCO.
23
16-QAM Packet No=2000 PSDU=2048 bytes TGad Channel
SNR(dB)
RMSE
Ideal with SCO=0 ppm This work with SCO=0 ppm This work with SCO=400 ppm No sync with SCO=0 ppm
Figure 4.2: The root mean square error of sampling phase
The ideal synchronization at 1% PER, SNR is about 12.7-dB under the TGad channel. So we determine the residual SCO after SCO estimation when SNR = 12.7-dB. Figure 4.3 shows the root mean square error SCO estimation and compensation. From the simulation result, SCO estimate error are about 17-ppm of SCO = 0-ppm and 19-ppm of SCO = 400-ppm after the SCO estimation.
8 9 10 11 12 13 14 15 16
35 16-QAM Packet No=2000 PSDU=2048 bytes TGad Channel
SNR(dB)
RMSE(ppm)
SCO estimation with SCO=0 ppm SCO estimation with SCO=400 ppm Ideal SCO estimation with SCO=0 ppm
Figure 4.3: The root mean square error of after coarse SCO tracking
The required packet-error rate (PER) is 1% in 802.11ad. After timing acquisition, SCO estimation and pilot tracking scheme for residual SCO, the performance compare with perfect synchronization at 1% PER, SNR losses are about
24
16-QAM Packet NO=1000 PSDU Length=2048 bytes TGad Channel
SNR(dB)
PER
Ideal with SCO=0 ppm This work with SCO=0 ppm This work with SCO=400 ppm No sync with SCO=400 ppm
Figure 4.4: The system performance
The required packet-error rate (PER) is 1% in 802.11ad. Figure 4.5 displays the offset tolerance of the FD synchronizer include timing acquisition, SCO estimation and pilot tracking scheme with various SNR which can be as high as -300~400 ppm, much larger than the ±20 ppm in 802.11ad standard.
-700 -600 -500 -400 -300 -200 -1000 0 100 200 300 400 500 600 700
16-QAM Packet NO=1000 PSDU Length=2048Bytes TGad Channel
PER
Figure 4.5: The offset tolerance of the FD synchronizer
25
Chapter 5
Hardware Implementation
A frequency-domain synchronizer for 128-FFT OFDM systems is implemented.
Figure 5.1 shows the block diagram, and figure 5.2 shows the architecture of hardware implementations, and the input are the received data after 128-FFT. In the architecture of timing synchronizer, the algorithms are described in chapter3.
Figure 5.1: Module block diagram
Figure 5.2(a): Part I. buffer, correlation, angle estimation
Figure 5.2(b): Part II. SCO estimation
26
Carrier frequency Symbol interval Sample rate Δ =f ×
Figure 5.2(c): Part II. CFO estimation
Figure 5.2(d): Part II. Timing acquisition
Hardware Specification
Application IEEE 802.11ad
Sample Rate 2.64 GHz
Symbol Rate(After 128-FFT) 20.625 MHz
Pipeline Clock 12 ns
Technology 65 nm CMOS
Table 5-1: Hardware specification
Module Name Gate Count Power
Data Buffer 41.5k 2.4294mW
Correlation 75k 1.2233mW
Angle 25k 0.5214mW
SCO Estimation 7.5k 0.2614mW
CFO Estimation 4k 0.0624mW
Timing Acquisition 5k 0.0987mW
Summary 158k 4.5966mW
Table 5-2: Synthesis report
27
Chapter 6
Conclusion and Future Work
This thesis, based on the architecture and the preamble structure of IEEE 802.11ad standard, investigate the frequency-domain timing synchronizer include timing acquisition, SCO estimation and pilot tracking scheme. Performances are measured under the TGad channel. At 1% PER and SCO tolerance range is -300~400-ppm, the SNR loss is only 0.8~1.4 dB in frequency-selective fading. From simulation results, the frequency-domain synchronizer has wide SCO tolerance.
We can improve the frequency-domain synchronizer by reducing complexity, the number of preamble and enhancing the accuracy of SCO estimation. In the thesis, we only consider the multipath and AWGN, and timing error. However, timing synchronization is in the first stage of receiver, there will be many several kinds of effects which are not improved yet. Hence, we have to improve the FD synchronizer again the tolerance of these effects in the future.
[12] [13] [18] [19] This work Architecture Interpolator Phase in Freq. Interpolator Interpolator Non-PLL ADCM
(ADCM) Required Format Pilot Preamble Preamble + Pilot Pilot Preamble + Pilot
Sampling Rate N/A N/A 4x 4x 1x
Cycle Count N/A N/A N/A 100 symbols 92 symbols
(Include 6 preamble) Tolerant
Range ±20ppm 400ppm ±200ppm ±100ppm -300 ~400 ppm
Table 6-1: Features of the different timing recovery
28
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