Chapter 4 Simulation Result
4.1 Simulation Platform
MATLAB is chosen as simulation language, due to its ability to mathematics, such as matrix operation, numerous math functions, and easily drawing figures. The major parameters are shown in TABLE IV.
Table 4-1 Simulation parameters
Parameter Value
MCS Set 20
Antenna No. 1
Modulation 16 QAM
Coding Rate 3/4
PSDU Length 2048 Bytes Carrier Frequency 60 GHz
Bandwidth 2.64 GHz
IFFT / FFT Period 48.48ns(128-FFT) Table 4-2: Simulation parameters
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4.2 Simulation Result
As mention before, the multiphase generator is used to generate 16 phases between one clock cycles. In other word, the phase error 16 means that signal is delay one cycle, and the phase error 0 means that sign is at ideal phase. With different initial phase error and SNR=5, after timing synchronizer, the final phase errors are convergence into 2 phases, as shown in Figure 4.1.
Figure 4.1: PDF of sampling phase error
Figure 4.2 shows the root mean square error of sampling phase. No synchronization means without timing acquisition to fix the unknown phase error.
Those initial phase is random to generate and its RMS is about 4.5~4.8 (phase), one phase offset means the phase difference with
8
π in this simulation. The value of
RMS is decreasing with the increasing of SNR and converges to 1.3 phases after timing acquisition with 400 ppm SCO.
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16-QAM Packet No=2000 PSDU=2048 bytes TGad Channel
SNR(dB)
RMSE
Ideal with SCO=0 ppm This work with SCO=0 ppm This work with SCO=400 ppm No sync with SCO=0 ppm
Figure 4.2: The root mean square error of sampling phase
The ideal synchronization at 1% PER, SNR is about 12.7-dB under the TGad channel. So we determine the residual SCO after SCO estimation when SNR = 12.7-dB. Figure 4.3 shows the root mean square error SCO estimation and compensation. From the simulation result, SCO estimate error are about 17-ppm of SCO = 0-ppm and 19-ppm of SCO = 400-ppm after the SCO estimation.
8 9 10 11 12 13 14 15 16
35 16-QAM Packet No=2000 PSDU=2048 bytes TGad Channel
SNR(dB)
RMSE(ppm)
SCO estimation with SCO=0 ppm SCO estimation with SCO=400 ppm Ideal SCO estimation with SCO=0 ppm
Figure 4.3: The root mean square error of after coarse SCO tracking
The required packet-error rate (PER) is 1% in 802.11ad. After timing acquisition, SCO estimation and pilot tracking scheme for residual SCO, the performance compare with perfect synchronization at 1% PER, SNR losses are about
24
16-QAM Packet NO=1000 PSDU Length=2048 bytes TGad Channel
SNR(dB)
PER
Ideal with SCO=0 ppm This work with SCO=0 ppm This work with SCO=400 ppm No sync with SCO=400 ppm
Figure 4.4: The system performance
The required packet-error rate (PER) is 1% in 802.11ad. Figure 4.5 displays the offset tolerance of the FD synchronizer include timing acquisition, SCO estimation and pilot tracking scheme with various SNR which can be as high as -300~400 ppm, much larger than the ±20 ppm in 802.11ad standard.
-700 -600 -500 -400 -300 -200 -1000 0 100 200 300 400 500 600 700
16-QAM Packet NO=1000 PSDU Length=2048Bytes TGad Channel
PER
Figure 4.5: The offset tolerance of the FD synchronizer
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Chapter 5
Hardware Implementation
A frequency-domain synchronizer for 128-FFT OFDM systems is implemented.
Figure 5.1 shows the block diagram, and figure 5.2 shows the architecture of hardware implementations, and the input are the received data after 128-FFT. In the architecture of timing synchronizer, the algorithms are described in chapter3.
Figure 5.1: Module block diagram
Figure 5.2(a): Part I. buffer, correlation, angle estimation
Figure 5.2(b): Part II. SCO estimation
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Carrier frequency Symbol interval Sample rate Δ =f ×
Figure 5.2(c): Part II. CFO estimation
Figure 5.2(d): Part II. Timing acquisition
Hardware Specification
Application IEEE 802.11ad
Sample Rate 2.64 GHz
Symbol Rate(After 128-FFT) 20.625 MHz
Pipeline Clock 12 ns
Technology 65 nm CMOS
Table 5-1: Hardware specification
Module Name Gate Count Power
Data Buffer 41.5k 2.4294mW
Correlation 75k 1.2233mW
Angle 25k 0.5214mW
SCO Estimation 7.5k 0.2614mW
CFO Estimation 4k 0.0624mW
Timing Acquisition 5k 0.0987mW
Summary 158k 4.5966mW
Table 5-2: Synthesis report
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Chapter 6
Conclusion and Future Work
This thesis, based on the architecture and the preamble structure of IEEE 802.11ad standard, investigate the frequency-domain timing synchronizer include timing acquisition, SCO estimation and pilot tracking scheme. Performances are measured under the TGad channel. At 1% PER and SCO tolerance range is -300~400-ppm, the SNR loss is only 0.8~1.4 dB in frequency-selective fading. From simulation results, the frequency-domain synchronizer has wide SCO tolerance.
We can improve the frequency-domain synchronizer by reducing complexity, the number of preamble and enhancing the accuracy of SCO estimation. In the thesis, we only consider the multipath and AWGN, and timing error. However, timing synchronization is in the first stage of receiver, there will be many several kinds of effects which are not improved yet. Hence, we have to improve the FD synchronizer again the tolerance of these effects in the future.
[12] [13] [18] [19] This work Architecture Interpolator Phase in Freq. Interpolator Interpolator Non-PLL ADCM
(ADCM) Required Format Pilot Preamble Preamble + Pilot Pilot Preamble + Pilot
Sampling Rate N/A N/A 4x 4x 1x
Cycle Count N/A N/A N/A 100 symbols 92 symbols
(Include 6 preamble) Tolerant
Range ±20ppm 400ppm ±200ppm ±100ppm -300 ~400 ppm
Table 6-1: Features of the different timing recovery
28
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