The circuit level simulation of BIST circuit also using HSPICE. The accumulator outputs are digital signal and we transfer the binary code into the decimal. Thus, the simulation results can be observed easily. Figure 6.11 shows the comparison of the accumulator output (in decimal) and the VCO control voltage. The BIST circuit is able to track the clock frequency of the SSCG. The accumulator outputs are between 0 and 30, presented as 0UI and 3UI.
Figure 6.11: The VCO control voltage vs. accumulator output
Figure 6.12 shows the chip layout of the SSCG and the BIST circuit. The chip area is 990um by 990um. The chip is implemented in TSMC 0.18 um CMOS 1P6M technology. Different to the SSCG, we can use logic analyzer to measure the BIST results. The digital signal of the BIST results can be measured easily.
Chapter6Built-in-Self-Test Circuit for SSCG
Figure 6.12: Layout of SSCG and BIST circuit
Table 6.1 shows the performance summary of the SSCG and the BIST circuit chip. The power consumption of the BIST circuit is 1.53mW and the core area of the BIST circuit is 150um by 250um.
Table 6.1: Performance summary of the SSCG and BIST chip SSCG center frequency 1.2 GHz
Technology TSMC 0.18um CMOS
Supply Voltage 1.8V
SSCG 57mW Power Consumption BIST 1.53mW
SSCG 500um×500um
Core area BIST 150um×250um
SSCG + BIST chip area 990um×990um
SSC BIST
Chapter 7 Conclusions
In this thesis, we have designed a spread spectrum clock generator and its Built-in-Self-Test circuit for the Serial-ATA system. The SSCG uses a fractional-N frequency synthesizer to achieve spread spectrum function with triangular waveform modulation. The SSCG consists of a conventional PLL, an address generator, a sigma-delta modulator, a controller and a multiplexer. Fractional-N PLL can achieve high resolution with high operation frequency. But, one major disadvantage is the generation of high tones at multiples of the channel spacing. The use of digital sigma-delta modulation technique in the fractional-N PLL can eliminate spurs. Using phase modulation to spread the spectrum can reduce the phase jump of the SSCG.
The SSCG circuit has been implemented in TSMC 0.18 um 1P6M CMOS technology. The measurement results show that the non spreading clock has a peak-to-peak jitter of 48 ps, a RMS jitter of 7.226ps, and a peak amplitude reduction of 21.633 dB in the spread spectrum mode.
In order to measure the frequency variation of SSCG, we have proposed a BIST circuit for the SSCG in this thesis. The BIST circuit consists of a multi-phase phase detector, a phase shifted detector and an accumulator. The BIST circuit can detect the frequency variation of the SSCG and show the waveform of triangular modulation of the SSCG. The BIST methodology for the SSCG that we proposed is an all digital design to minimize the hardware and power overhead.
Bibliography
Bibliography
[1] “Intel®IXP4XX Product Line of Network Processors and IXC1100 Control Plane Processor: Spread-Spectrum Clocking to Reduce EMI,” Sep. 2003.
[2] “Spread Spectrum Timing for Hard Disk Drive Applications,”
http://www.cypress.com, November 2000.
[3] http://www.fulcrum.ru/Documents/CDROMs/NS/htm/nsc00596.htm.
[4] S. Bolger and S. O. Darwish, “Use Spread-spectrum Techniques to reduce EMI,”
EDN; Boston, Vol.43, May 21, 1998.
[5] K. Hardin et al. “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions,” in Proceedings of the 1994 IEEE International Symposium on Electromagnetic Compatibility, pp. 227-231, 1994.
[6] F. Lin and D. Y. Chen, “Reduction of Power Supply EMI Emission by Switching Frequency Modulation,” in The VPEC Tenth Annual Power Electronics Seminar, Virginia Power Electronics Center, Blacksburg, Virginia, September 20-22,1992.
[7] Serial ATA Workgroup “SATA: High speed Serialized AT Attachment,” Revision 1.0, 26-May-2004.
[8] Heredia, N.J., “Spread spectrum clock-an EMC solution for new generation portable computers,” Electromagnetic Interference and Compatibility, 2002.
Proceedings of the International Conference. pp. 146-151, 2002.
[9] “Jitter in PLL-Based System: Causes, Effects, and Solutions,”
http://www.cypress.com, July 1997.
[10] M. T. Zhang, “Notes on SSC and Its Timing Impacts,” http://www.intel.com, February 1998.
[11] B. Goldberg, “The Evolution and Maturity of Fractional-N PLL Synthesis,”
Microwave Journal, pp. 124-134, Sep. 1996.
[12] Behzad Razavi, RF Microelectronics, Pretice-Hall, Inc., 1998.
[13] Roland E. Best, Phase-Locked Loops Theory Design, Simulation, and Applications, McGraw-Hill international editions, 1993.
[14] Behzad Razavi, Design of analog CMOS integrated circuits, McGraw-Hill international editions, 2001.
[15] S. –O. Lee, M. Yoh, J. Lee and I. Ryu, “A 17Mw, 2.5GHz fractional-N frequency synthesizer for CDMA2000,” in Proc. ESSCIRC’01, 2001.
[16] Steven R. Norsworthy, Richard Schreier and Gabor C. Temes, Delta-Sigma Data Converters, IEEE press, 1997.
[17] T. P. Kenny, T. A. D. Riley, N. M. Filiol and M. A. Copeland, “Design and realization of a digital ΔΣ modulator for fractional-N frequency synthesis,＂
IEEE transactions on vehicular technology, vol. 48, no. 2, pp. 510-521, Mar. 1999.
[18] R. M. Gray, “Quantization noise spectra,” IEEE Trans. Of information theory, vol. 36, no. 6, pp. 1220-1244, Nov. 1990.
[19] Woogenun Rhee, Multi-bit Delta-sigma Modulation Technique for Fractional-N Frequency Synthesizers, Ph.D. thesis, University of Illinois at Urbana-Champaign, 2001.
[20] M. Kozak and I. Kale, “A pipelined noise shaping coder for fractional-N frequency synthesis,” IEEE Trans. Instrumentation and Measurement, vol. 50, pp.
1154-1160, Oct. 2001.
[21] H. H. Chang, I. H. Hua and S. J. Liu, “A spread-spectrum clock generator with triangular modulation,” IEEE J. Solid-State Circuits, Vol.38, No.4, April, 2003 [22] M. Kokubo, T. Kawamoto, T. Oshuma, T. Noto, M. Suzuki, S. Suzuki, T.
Hzyasaka, T. Takahashi and J. Kasai “Spread-spectrum Clock Generator for Serial ATA using Fractional PLL controlled by ΔΣ Modulator with Level Shifter,＂
IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 160-590, 2005.
Bibliography
[23] H. Mair and L. Xiu, “An Architecture of High-Performance Frequency and Phase Synthesis,” IEEE J. Solid-State Circuits, vol. 35, pp. 835-846, June. 2000.
[24] H. R. Lee, O. Kim, G. Ahn and D. K. Jeong, “A low-jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18 μ m CMOS,＂ IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 162-590, 2005.
[25] Shi-Dai Mai, “Multi-module synchronization methodology” Master Degree dissertation of National Central University 2002.
[26] J. Yuan and C. Svensson, “High speed CMOS circuit technique,” IEEE Journal of Solid-State Circuits, Vol. 24, Feb,1989.
[27] William O. Keese, “An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charpe Pump Phase-Locked Loops” National Semiconductor Application Note, May 1996.
[28] W. Rhee, B.–S. Song and A. Ali, “A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator” IEEE J. Solid-State Circuits, vol.
35, pp. 1453-1460, Oct. 2000.
[29] C. H. Park and B. Kim, “A Low-Noise, 900-MHz VCO in 0.6-μm CMOS” IEEE J. Solid-State Circuits, vol. 34, pp. 586-591, May 1999.
[30] W. T. Chen, J. C. Hsu, H. W. Lune and C. C. Su, “ A spread spectrum clock for SATA-II” IEEE international symposium on circuit and systems, vol. 3, pp.
2643-2646, May 2005.