適用於Serial-ATA之展頻時脈產生器及其內建自我測試電路

國 立 交 通 大 學

電 機 與 控 制 工 程 學 系 研 究 所

碩 士 論 文

適用於

Serial-ATA 之

展頻時脈產生器及其內建自我測試電路

A Spread Spectrum Clock Generator and

Built-in-Self-Test Circuit for Serial-ATA

研 究 生：周楙軒

指導教授：蘇朝琴 教授

展頻時脈產生器及其內建自我測試電路

A Spread Spectrum Clock Generator and

Built-in-Self-Test Circuit for Serial-ATA

研 究 生：周楙軒 Student：Maohsuan Chou

指導教授：蘇朝琴 Advisor：Prof. Chauchin Su

國 立 交 通 大 學

電機與控制工程學系研究所

碩 士 論 文

A Thesis

Submitted to Department of Electrical and Control Engineering College of Electrical Engineering and Computer Science

National Chiao Tung University in partial Fulfillment of the Requirements

for the Degree of Master

in

Electrical and Control Engineering September 2006

Hsinchu, Taiwan, Republic of China

適用於

Serial-ATA 之

展頻時脈產生器及其內建自我測試電路

學生：周楙軒 指導教授：蘇朝琴 博士

國立交通大學電機與控制工程學系研究所

摘要

隨著對高速傳輸速率需求的不斷提升，高速時脈信號所造成的電磁干擾 (Electro-Magnetic Interference, EMI)成為不可忽視的問題。在常見的外部儲存規

格 Serial AT Attachment (Serial-ATA)中，系統要求資料傳輸時的時脈頻率具有

5000 ppm 的展頻量與 30~33 kHz 之三角波調變率。展頻技術即是利用對時脈信 號頻率做調變以有效降低電磁干擾。

在本論文中，我們提出一個符合 Serial-ATA 規格並適用於 6Gbps 資料發送 器之展頻時脈產生器(Spread Spectrum Clock Generator, SSCG)及其內建自我測試 (Built-in-Self-Test, BIST)電路。我們使用一個具備三階三角積分調變器的除小數 頻率合成器來實現展頻時脈產生器，使用數位式三角積分調變技術可將量化雜訊 調變到高頻以減少 spur 現象。為了減少展頻時脈產生器的相位跳動，我們採用 相位調變的方式來達到展頻的效果。展頻時脈產生器的內建自我測試電路是用數 位的方式偵測展頻時脈產生器的頻率變動，藉由此測試電路可以簡單的測試出展 頻時脈產生器是否正常操作。 我們使用TSMC CMOS 0.18 μm 製程實現了一個 1.2 GHz 10 個 phases，具 有5000 ppm、30 kHz 三角波調變的展頻時脈產生器及其內建自我測試電路。在 非展頻情況所量測到的時脈抖動peak-to-peak jitter 為 48 ps；RMS jitter 為 7.226 ps。在展頻模式下，頻譜上的時脈峰高能量降低了 21.633 dB。

索引詞彙─除小數頻率合成器、展頻時脈產生器、內建自我測試電路、鎖相迴路、 三角積分調變器

A Spread Spectrum Clock Generator and

Built-in-Self-Test Circuit for Serial-ATA

Student：Maohsuan Chou Advisor：Prof. Chauchin Su

Department of Electrical and Control Engineering

National Chiao Tung University

ABSTRACT

As operating at high frequencies, currents and voltages present in the circuits and the signal traces lead to a great Electro-Magnetic Interference (EMI). In Serial AT

Attachment (Serial-ATA), one of the popular external storage specifications, it

requires a wide spreading of 5000 ppm at a 30~33 kHz triangular modulation rate. The Spread Spectrum Clock Generator (SSCG) is a special technique of frequency modulation to reduce EMI effectively.

In this thesis, we propose a SSCG for 6Gbps transceiver and its Built-in-Self-Test (BIST) circuit for Serial-ATA specification. We use a fractional-N frequency synthesizer with a digital third-order MASH 1-1-1 sigma-delta modulator to accomplish the spread spectrum function. The use of digital sigma-delta modulation technique in the fractional-N frequency synthesizer can eliminate spurs. Using phase modulation to spread the spectrum can reduce the phase jump of the SSCG. The BIST circuit for SSCG is a digital approach to detect the frequency variation of the SSCG, it can tests if the SSCG work or not effectively and precisely.

The SSCG which has 1.2 GHz 10 phases, a 5000 ppm down spread and a 30 kHz triangular modulation rate. The BIST circuit are implemented using TSMC CMOS 0.18 μm technology. The measurement results show that the non spreading clock has a peak-to-peak jitter of 48 ps, a RMS jitter of 7.226 ps, and a peak amplitude reduction of 21.633 dB in the spread spectrum mode.

Index Terms － fractional-N frequency synthesizer, spread spectrum clock generator, building-in-self-test, phase-locked loop, sigma-delta modulator

誌

謝

碩士班兩年的時光一轉眼即將結束，回首過去這兩年在交大生活的點點滴滴，辛苦 卻充滿樂趣。當初做研究一切的挫折和磨練，都是讓自己成長的契機，能有這些成果， 要感謝許多在我身旁的人、事、物，因為你們，我的研究生活才能如此多彩多姿。 本論文得以順利完成，首先要感謝我的指導教授 蘇朝琴 教授。老師孜孜不倦追求 學問的熱忱，是我欽佩的好榜樣；老師教導我的，不只是專業領域的知識，還有待人處 事應有的態度，他讓我了解到「遇到困難時，必須以勇敢、積極的態度去面對它並克服 它，千萬不能有逃避的想法。」老師這兩年來的啟蒙與指導，點點滴滴感謝在心頭。 感謝我親愛的母親和妹妹，他們源源不絕又不求回報的愛是我最堅實的依傍。母親 一直支持著我，做我的後盾，讓我可以專心完成我的學業。她開明的態度和智慧給了我 許多引導和啟發，都是我終身受用的寶藏。 感謝玟君，陪我一起走過了這兩年的喜怒哀樂。每當我煩惱或憂愁的時候，她除了 聆聽我喋喋不休的抱怨，還有給我溫暖的支持與鼓勵，讓我有堅持下去的動力。 當然也要感謝學長們兩年來的照顧。謝謝鴻文，給予許多晶片製作經驗上的指導； 謝謝丸子，費心的建置實驗室裡的工作站及電腦設備，讓我在設計晶片時能無後顧之 憂；謝謝仁乾，在我有疑問的時後都會熱心指導我、在我灰心喪氣時，他的鼓舞增加了 我對自己的信心；謝謝盈杰，在我心煩時陪我打球，舒緩了研究上的壓力，還要感謝昱 輝、阿達、瑛佑、Ku、Cgu、阿銘等諸位學長的細心指導。 感謝我的同學及學弟們：宗諭、智琦、小冠、匡良、順閔、忠傑、教主、祥哥、Snoopy、 方董、小馬、議賢、威翔、村鑫、存遠、皇如，每位都在生活和課業上給了我數說不盡 的照顧及幫助，大家的友誼豐富了我在918 的生活，留下令人難忘的美好回憶。 周楙軒 08/30/2006

List of Contents

TITLE PAGE...I ABSTRACT...II LIST OF CONTENTS...V LIST OF TABLES...VII LIST OF FIGURES ... ...VIII

Chapter 1 ...1

Introduction...1

1.1 Motivation ...1

1.2 Basics of Serial Link ...2

1.3 Thesis Organization...3

Chapter 2 ...5

Basics of Spread Spectrum Clocking ...5

2.1 The Fundamental Theory of SSC ...5

2.2 SSC Requirement in Serial-ATA ...8

2.3 Time Domain Impacts of SSC...9

Chapter 3 ...13

Fractional-N Phase-Locked-Loop with ΣΔ modulator...13

3.1 Phase-Locked Loop Fundamentals...13

3.2 Phase-Locked Loop Linear Model ...16

3.3 Types of Noise Sources in PLL ...17

3.4 Fractional-N Frequency Synthesis...19

3.5 Sigma-Delta Modulator...21

3.6 MASH 1-1-1 Sigma-Delta Modulator...23

Chapter 4 ...25

Spread Spectrum Clock Generator Implementation...25

4.1 Implementation of SSCG ...25

List of Contents

Chapter 5 ...42

Simulation and Measurement Results ...42

5.1 SSCG Behavior Simulation...42

5.2 SSCG Circuit Level Simulation ...45

5.3 Testing Setup ...47

5.4 Measurement Results...49

5.2 Summary and Comparisons...52

Chapter 6 ...53

Built-in-Self-Test Circuit for SSCG...53

6.1 Introduction ...53

6.2 Architecture of BIST Circuit for SSCG...54

6.3 BIST Circuit Behavior Simulation ...58

6.4 Circuit Level Simulation and Layout ...60

Chapter 7 ...62

Conclusions...62

List of Tables

TABLE 4.1: State table of the FSMSA 37

TABLE 4.2: Resolution between control signals and output of the MUX 40

TABLE 5.1: Performance summary of the SSCG chip 52

TABLE 5.2: Performance comparison of SSCGs 52

List ofFigures

List of Figures

Figure 1.1: Serial link transceiver architecture 3

Figure 2.1: Spread fundamental frequency comparison 6 Figure 2.2: The effect of frequency modulation on the frequency spectrum 6 Figure 2.3: Spectra of frequency-modulated sine wave 7

Figure 2.4: Spectra of pulse train waveform 8

Figure 2.5: Spread spectrum requirement for Serial-ATA 9

Figure 2.6: Time domain behavior of SSC 9

Figure 2.7: Graphical representation of cycle-to-cycle jitter 10 Figure 2.8: Graphical representation of long-term jitter 11

Figure 3.1: Simple phase-locked loop 14

Figure 3.2: Waveform in a PLL 14

Figure 3.3: Block diagram of a typical PLL 15

Figure 3.4: Linear model of PLL 16

Figure 3.5: Noise sources in a PLL 17

Figure 3.6: Transfer function of noise sources 18

Figure 3.7: A fractional-N frequency synthesizer with divider controller 19

Figure 3.8: Sawtooth phase error 20

Figure 3.9: Spurious noise in VCO output spectrum 20 Figure 3.10: Block diagram of first-order (a) ΣΔ modulator, (b) DPA representation 21 Figure 3.11: Linear model of first-order sigma-delta modulator 22 Figure 3.12: Quantization noise of second to fourth ΣΔ modulator 23 Figure 3.13: Third-order MASH 1-1-1 ΣΔ modulator 24

Figure 4.1: Types of SSCG architecture 26

Figure 4.2: System architecture of spread spectrum clock generator 27 Figure 4.3: Circuit schematic of (a) PFD (b) TSPC D flip-flop of PFD 28

Figure 4.4: Timing diagram of PFD 28

Figure 4.5: Circuit schematic of charge pump 29

Figure 4.6: Waveform of charge pump 29

Figure 4.8: Open loop response bode plot 31

Figure 4.9: Schematic of third-order loop filter 32

Figure 4.10: Circuit schematic of VCO 34

Figure 4.12: Digital realization of MASH 1-1-1 ΣΔ modulator 36 Figure 4.13: The input range and output spreading of MASH 1-1-1 ΣΔ modulator 36

Figure 4.14: State diagram of the FSM 38

Figure 4.16: Architecture of (a) 2-to-1 MUX (b) 5-to-1 MUX 39

Figure 4.17: Waveform for the phase changed 40

Figure 4.18: TSPC type D flip-flop 41

Figure 5.1: SIMULINK model of the SSCG system 43

Figure 5.2: SSCG behavior simulation 43

Figure 5.3: Bode plot of open-loop response 44

Figure 5.4: FFT of SSCG at non-SSC mode and SSC mode 44

Figure 5.5: Waveform of two type SSCGs 45

Figure 5.6: FFT comparison of two type SSCG 45

Figure 5.7: Tuning characteristic of VCO with corner model variation 46 Figure 5.8: Eye diagram of VCO output at non-SSC mode 46

Figure 5.9: Control voltage of VCO at SSC mode 47

Figure 5.10: Micrograph of die 47

Figure 5.11: Photograph of testing board 48

Figure 5.12: Instruments for testing the SSCG chip 48 Figure 5.13: Measured jitter of SSCG output at non-SSC mode 49

Figure 5.14: Spectrum of SSCG output 49

Figure 5.15: Spectrum of VCO output at non-SSC mode 50

Figure 5.16: Spectrum of VCO output at SSC mode 51

Figure 6.1: Linearity issue of triangular modulation of SSCG 54

Figure 6.2: Architecture of BIST circuit 54

Figure 6.3: The architecture of MPD 55

Figure 6.4: Waveform of MPD 55

Figure 6.5: The architecture of PSD 56

Figure 6.6: The resolution & samples vs. sampling frequency 57

Figure 6.7: The architecture of accumulator 58

Figure 6.8: SIMULINK model of the BIST system 58

Figure 6.9: The VCO frequency vs. accumulator output 59 Figure 6.10: The accumulator output for T₁ of (a) 2000ns (b) 500ns 59 Figure 6.11: The VCO control voltage vs. accumulator output 60

Figure 6.12: Layout of SSCG and BIST circuit 61

Chapter1Introduction

Chapter 1

Introduction

1.1 Motivation

As the increasing demand for higher data transmitting rate, Serial AT

Attachment (Serial-ATA) is one of the popular external storage specifications. High

speed serial link technology is applied in optical communication, PCI Express and USB recently. Using serial link technology has many advantages including low cost, high speed and pin reduction. Serial-ATA is used with high transmission rate up to 3 Gbps and extends up to 6 Gbps in the next generation.

As operating at high frequencies, currents and voltages present in the circuits and the signal traces lead to a great Electro-Magnetic Interference (EMI). EMI is caused by the radiated emission of unwanted radio frequency signals that pollute

managed radio spectrum. In the United States, the Federal Communications

Commission (FCC) regulates the amount of EMI an electronic device may emit to

ensure that electronic devices do not interfere with each other.

Many EMI reduction techniques can be classified into two. One is to enclose the EMI from emitting and another is to reduce the EMI at the source. The reduction methods include Printed Circuit Broad (PCB) layout techniques, metal shielding, and passive components. Another popular technique, Spread Spectrum Clocking (SSC), belongs to the latter which can reduce the amplitude at each clock harmonic to meet EMI restriction [1]. Ideally, the EMI reduction is done on chip without using heavy shielding materials in order to be low cost and portable. Serial-ATA systems adopt the SSC technique to reduce EMI problem. The Spread Spectrum Clock Generator (SSCG) is a special technique of frequency modulation to reduce EMI effectively.

CMOS technology has been growing very fast in recent years. Design of

integrated circuits (ICs) becomes so complex and gate counts become so large.

Undoubtedly, faster and more complex test equipments are required to achieve test specifications and test functions. An innovative method to simplify the test equipment is to move test functions onto the chip itself, which is called Built-in-Self-Test (BIST).

In this thesis, we accomplish a SSCG for 6Gbps transceiver for Serial-ATA specification and its BIST circuit. The BIST circuit for SSCG is a digital approach to detect the frequency variation of SSCG, it can tests if the SSCG work or not effectively and precisely.

1.2 Basics of Serial Link

Figure 1.1 shows a general purpose serial link transceiver architecture. The low- speed parallel digital signals are to be transferred to far-end. The phase-locked loop (PLL), based on a low frequency reference clock, generates appropriate clock phases

Chapter1Introduction

and applies these clock phases to the multiplexer (MUX). The MUX transfers these parallel input data to a high speed serial output data. Since the driving capability of the MUX output is small, so it is enlarged stage by stage by the driver. When signal is transmitted through the channel, the frequency and phase may drift due to external noise and the amplitude will decay as well. The receiver front end enlarges the signal amplitude. Then the Clock and Data Recovery (CDR) finds the optimal sampling phase and retimes the signal. The De-MUX transfers the serial signals back to the parallel ones.

Figure 1.1: Serial link transceiver architecture

1.3 Thesis Organization

This thesis comprises seven chapters. Chapter 1 introduces the motivation of this thesis and thesis organization. In Chapter 2, we will introduce the spread spectrum theory, how it can reduce EMI problem, and the Serial-ATA requirements for SSCGs. In Chapter 3, we introduce the frequency synthesizer including PLL and the fractional-N concept. The most important part is to describe the digital sigma-delta modulator. TX data RX data SSCG MUX De-MUX CDR receiver driver channel

In Chapter 4, we will introduce the different types of SSCGs. We accomplish a SSCG using a conventional PLL consists of a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a frequency divider. Then we will introduce address generator that generates the triangular waveform for frequency modulation, a third-order MASH 1-1-1 sigma-delta modulator, a multiplexer and a controller that control the VCO output phases to frequency divider for frequency modulation.

In Chapter 5, we will show the simulation and measurement results of the SSCG. The chip is implemented in TSMC 0.18 um 1P6M CMOS technology. In Chapter 6, a BIST circuit for SSCG is proposed. The BIST circuit for SSCG is a digital approach to detect the frequency variation of SSCG, it can tests if the SSCG work or not effectively and precisely. And that can be implemented with little area and power overhead. Finally, conclusion will be described in Chapter 7.

Chapter2Basics of Spread Spectrum Clocking

Chapter 2

Basics of Spread Spectrum Clocking

Faster operating speeds of electrical devices today result in more EMI at higher frequencies. Lots of methods have been proposed to reduce EMI. Commonly used EMI reduction solutions include: shielding, pulse shaping, slew-rate control [2], low voltage differential clocking [3], staggering the outputs [4], layout technique, and

spread spectrum clocking (SSC). SSC is a popular technique to reduce EMI for Serial-ATA (Serial-ATA) requirement. In this chapter, we discuss the fundamental

theory of SSC including the basic properties and the effects on the original timing.

2.1 The Fundamental Theory of SSC

SSC is a special technique of frequency modulation to reduce EMI effectively. As shown Figure 2.1 [5], by spreading the clock frequency slightly, the energy is spread out as well. This reduces the maximum peak energy under the same total amount of energy. Only a small amount of variation in frequency is needed to obtain several decibels of energy reduction. Otherwise, it would take a lot of expensive shielding to achieve the similar results. As a result, SSC is an effective and low cost technique to meet EMI restriction.

Figure 2.1: Spread fundamental frequency comparison

To obtain the details of spread spectrum, we analyze that how frequency modulation can lead to spread spectrum. Figure 2.2 shows the effect of frequency modulation on the frequency spectrum, where f is the carrier frequency, _c f is the _m

modulating frequency, and Δ is the amplitude of frequency change. As can be seen f

frequency domain of the frequency-modulated sinusoidal waveform, sideband harmonics are generated, and the magnitude at center frequency is reduced compared to un-modulated signal. The frequency difference between each two adjacent sideband harmonics is f . _m

Figure 2.2: The effect of frequency modulation on the frequency spectrum frequency domain

frequency domain

time domain time domain

frequency-modulated sinusoidal waveform sinusoidal waveform ( ) sin 2 _c A t =A π f t A t( )=Asin 2π f_c[1 (+ Δf sin 2π f t_m ) / ]f_c c f A 1 A 2 A 3 A fm c m f + f f_c f_c− f_m Non-SSC SSC

Chapter2Basics of Spread Spectrum Clocking

The extent of distribution and the magnitude of the resultant spectrum depend on the modulation index β ≡ Δf f/ _m [6]. Figure 2.3 shows the actual spectra for several β values. The larger the β values, the more evenly distributed are the spectrum.

Figure 2.3: Spectra of frequency-modulated sine wave

There are two important characteristics of a frequency modulated signal according to Carson’s Rule:

(1) Total power of a signal is unaffected by the frequency modulation. The total power of a signal is equal to the summation of the square of each harmonic amplitude. Referring to Figure 2.3, this means

2 2 2 2

1 2 3

A = A + 2(A + A +...). (2-1)

(2) 98% of the total power of a frequency modulated signal is contained inside the bandwidth β_T , where B = 2(β +1)f . This means the side-band _{T m}

harmonic frequency ranges from (f B /2) to _{c - T} (f_{c +}B /2) . where _T

T

B = 2 f(β +1)/βΔ . Ifβ  , the1 B = 2Δf_T .

As shown in Figure 2.4, if the un-modulated waveform is a pulse train, then it itself contains harmonics. Frequency modulation of the pulse train waveform distributes each of the switching harmonic components into sideband harmonic.

1 0.57 0.22 0.36 _0.14 0.01 0.78 0.43 0.11 0.22 0.37 0.47 0.04 0.01 0.37 0 β = β =1 2 β = β =3

Figure 2.4: Spectra of pulse train waveform

Notice that, the frequency difference between each two adjacent side-band harmonics is still f , and an ideal square wave is composed of infinite sinusoidal _m

components. For a frequency-modulated pulse train, the modulation index of each switching harmonicsβ_n is different, thenβ_n =nβ . where n is the number of switching harmonics of the un-modulated pulse train. Carson’s Rule applies to each harmonic, i.e., 2( 1) _m nT B = nβ+ f . (2-2) Ifβ  , then 1 nT T B =nB . (2-3) Thus, the higher harmonic number, the more is the spread-out power.

2.2 SSC Requirement in Serial-ATA

Figure 2.5 shows the Serial-ATA requirement for the 6Gbps transceiver system

[7]. The frequency varies with time, a down spreading of 5000 ppm and a 30~33 kHz

1 [1 ( sin 2 ) / ] c m c f + Δf π f t f 1 c f c f 2f_c m f m f c f nf_c

frequency domain frequency domain time domain time domain

…. ….

Chapter2Basics of Spread Spectrum Clocking

triangular modulation rate. The frequency deviation is 6 MHz so the lowest frequency is 1.194 GHz. Down spreading frequency modulation ensures the highest frequency is below the original frequency, 1.2 GHz. Typical, the modulation frequencies should be above the 30 kHz audio band but low enough to avoid system timing problems. Serial-ATA specification define the 30~33 kHz triangular modulation rate.

Figure 2.5: Spread spectrum requirement for Serial-ATA

2.3 Time Domain Impacts of SSC

SSC is a technique of frequency modulation. In frequency domain, the clock frequency is spreading; the energy is spread out as well. In time domain, the frequency varies periodically with time, so does the period of clock. As shown in Figure 2.6, the period of modulated signal varies with time and its change depends on the modulation profile. Due to the variation of modulated signal period, the impacts on timing are important [8].

Figure 2.6: Time domain behavior of SSC T F 1.2GHz 1.194GHz (-5000ppm) 30~33kHz SSC non-SSC time time (a) un-modulated signal (b) modulated signal

Despite of spreading of energies, the clock signal is still a square wave. Thus, we can define the cycle-to-cycle jitter and the long-term jitter of the SSC system.

A. Cycle-to-Cycle Jitter

Cycle-to-cycle jitter is the change in a clock’s output transition from its corresponding position in the previous cycle. Figure 2.7 shows a graphical representation of the cycle-to-cycle jitter [9].

Figure 2.7: Graphical representation of cycle-to-cycle jitter

The period difference between the maximum and minimum frequencies in a SSC system is

1 1 (1 )

total

nom nom nom

T f f f δ δ Δ = − ≈ − , (2-4) where f_nom is the non-spread frequency, δ specifies the total amount of spreading as a relative percentage of f_nom.

The number of clock cycles that exist in the time interval that the modulated clock migrates from f_nom to (1−δ)f_nom can be found as

1 1 2 2 avg avg m m f N f f f = ⋅ ⋅ = , (2-5) where f_avg is the average frequency of the spread spectrum clock, f is the _m

modulation frequency. 1 2 1 2 3 2 jitter jitter j t t j t t = − = − Clock 1 t t2 t3

Chapter2Basics of Spread Spectrum Clocking

Because the modulation profile is symmetric, we can only consider the f_avg in half of the modulation period.

1 0.5

avg nom

f = ( - δ) f⋅ . (2-6)

We can rewrite Eq. 2-6 as

1 0.5 m m avg _nom f _f N = = ( - δ) 2f 2f . (2-7)

Combining Eq. 2-6 and Eq. 2-7, the cycle-to-cycle period change, i.e., the increase in cycle-to-cycle jitter due to SSC, can be expressed as

2 1 0.5 total m c-c ₂ nom T δ f T N - δ f Δ Δ = = ⋅ . (2-8) In our design, the spread spectrum clock generator with a down spreading of 5000 ppm and a 30 kHz modulation rate, the increase cycle-to-cycle jitter is

3 16 9 2 2 0.5% 30 10 2.08855 10 1 0.5 0.5% (1.2 10 ) c-c T ⋅ ⋅ − sec Δ = ⋅ = ⋅ − ⋅ ⋅ . (2-9) B. Long-Term Jitter

Long term jitter is defined that maximum change in a clock’s output transition from its ideal position. Figure 2.8 shows the graphical representation of long-term jitter [9].

Figure 2.8: Graphical representation of long-term jitter Cycle N

Cycle 0

According to the definition above, Eq. 2-4 can be viewed as the long-term jitter of a down-spreading clock signal. The amount of long-term jitter is positively proportional to the modulation amount, negatively proportional to the nominal frequency, and is unconcerned with the other modulation factors.

In our design, the spread spectrum clock generator with a down spreading of 5000 ppm and a 30 kHz modulation rate, the increase long-term jitter is

12 9 0.5% 4.1667 10 1.2 10 total nom T sec f δ − Δ ≈ = = ⋅ ⋅ . (2-10) For the examples above, we can find that the cycle-to-cycle jitter of SSC system can be ignored. The Serial-ATA specification define a 5000 ppm down-spreading at 30~33 kHz modulation rate, there are many clock cycles pass by the reference period. The long-term jitter of the spread spectrum modulated signal is tremendous [10].

Chapter3Fractional-N Phase-Locked Loop with ΣΔ modulator

Chapter 3

Fractional-N Phase-Locked-Loop

with ΣΔ modulator

The Phase-Locked Loop (PLL) has become an important technique to generate signals in radio and timing applications. Traditionally, fractional-N uses analog compensation mechanisms to suppress spurious signals. In recent years, there is an emerging activity for all-digital fractional-N implementation involving oversampling and noise shaping sigma-delta modulators (ΣΔ modulator). Several papers and products related to this technology have been published and put into market [11]. Since this method provides several advantages over the analog compensation method. It is the main architecture for today’s fractional-N PLLs. In this chapter, we discuss the PLL fundamental theory and the fractional-N mechanism.

3.1 Phase-Locked Loop Fundamentals

A Phase-Locked Loop (PLL) is able to lock the output phase of frequency to an input reference by means of negative-feedback loop. A simple PLL consisting of a

Phase Detector (PD), a Loop Filter (LF) and a Voltage Controlled Oscillator (VCO)

is shown in Figure 3.1. The PD served as an “error amplifier” in the feedback loop that is to minimize the phase differenceΔ between ( )φ φ_in t and ( )φ_out t . The loop is considered “locked” if Δ is constant with time, the result between the input and φ output frequency is equal [12].

Figure 3.1: Simple phase-locked loop

In the locked condition, all the signals in the loop have reached a steady state and the PLL as follows. The PD produces an output whose pulse width is proportional to Δ . The LF suppresses high frequency components in the PD output and φ generates the DC value to control the VCO frequency. The VCO then oscillates at a frequency equal to the input frequency with a phase difference equal to Δ . The φ typical waveform of PLL is shown in Figure 3.2.

Figure 3.2: Waveform in a PLL t t t t ( ) out t φ ( ) in t φ PD output LF output PD LF VCO ( ) in t φ _{( )} out t φ

Chapter3Fractional-N Phase-Locked Loop with ΣΔ modulator

From a frequency perspective, if the input frequency w is momentarily _in

greater than the output frequency w , ( )_out φ_in t will accumulate phase faster than ( )

out t

φ and the PD generates increasingly wider pulses. These pulses make the higher DC voltage at the output of the LF, then the VCO frequency increasing.

The above analysis provides the tracking capabilities of a PLL. It is important to note that the loop locks only after two conditions have been satisfied:

(1) w is equal to _out w _in

(2) The phase difference Δ has settled to proper value. φ

If the two frequencies become equal at a point in time but Δ does not φ establish the required control voltage for the VCO, the loop must continue transient temporarily and makes the frequencies unequal again.

Figure 3.3 shows a block diagram of a typical PLL. The internal feedback signal “F ” from the divider is compared to the external reference signal “_div F ” by Phase _ref Frequency Detector (PFD). PFD generates lead or lag message to Charge Pump (CP).

The CP will charge or discharge the loop filter to vary the VCO output frequency according to the phase difference detected by the PFD. Then the VCO oscillates at a frequency equal to the N times input frequency with a phase difference. Finally, the frequency of F can be adjusted according to synchronous the input signal and _div

out

F will become N ×F in steady state. _ref

Figure 3.3: Block diagram of a typical PLL

PFD CP LF VCO divider ÷N ref F out F div F

3.2 Phase-Locked Loop Linear Model

We can use a linear approximation to gain intuition and understand the trade-off in the PLL design. Figure 3.4 shows a linear model of PLL [13]. The model is to provide the overall transfer function for the phase. The PFD with charge pump and has a gain K_PFD is represented simply. The LF can be represented with S domain transfer function Z_LF( )s . K_VCO is gain of the VCO with unit of rad/s_{/ V . Since}

integration is a linear operation on the VCO’s output frequency, frequency divider is also divider the output phase by a factor of N.

Figure 3.4: Linear model of PLL The forward gain of the PLL is therefore derived as

out e PFD LF VCO K Z (s)K G(s)= s φ φ = . (3-1)

The reverse loop gain is

div out 1 H(s)= N φ φ = . (3-2)

Then, the close loop transfer function can be expressed as

PFD LF VCO out PFD LF VCO in K Z (s)K G(s) _s = = K Z (s)K 1+G(s)H(s) 1+ s N φ φ ⋅ . (3-3) - PFD&CP LF VCO ÷N div φ e φ KPFD φout in φ _{( )} LF Z s KVCO s

Chapter3Fractional-N Phase-Locked Loop with ΣΔ modulator

The order of PLL transfer function is determined by the loop filter. We consider a linear model charge-pump PLL and the loop filter transfer function as

LF

1

Z (s)= R+

sC. (3-4)

We can rewrite the close loop transfer function as

2 2 ₂ 2 PFD VCO out PFD VCO PFD VCO in PFD VCO n n K K (sRC +1) C H(s)= = K K K K s + s RC + NC NC K K (sRC +1) C = s + δω s +ω φ φ . (3-5) Now by using the control theory, the natural frequencyω and damping _n

factorδof the system can be derived as ω =_n KPFD VCOK

N C⋅ , 2 n

RC

δ = ω . (3-6)

3.3 Types of Noise Sources in PLL

Using above linear model, several noise sources can be added to the linear model to further examine the behavior of PLL, and the model with noise is shown in Figure 3.5. V s is associated with the PFD and the CP and also known as the _n1( ) reference noise. V s is introduced by the loop filter’s components and _n2( ) V s is _n3( ) the phase noise generated by the VCO.

Figure 3.5: Noise sources in a PLL - LF VCO ÷N PFD K KVCO s ( ) LF Z s ( ) in s φ φ_out( )s 1( ) n V s V s_n2( ) V s_n3( )

The H s , ₁( ) H s , ₂( ) H s represents transfer function of ₃( ) V s , _n1( ) V s , _n2( )

3( )

n

V s to the output phase φ_out( )s , respectively. They can be expressed as follows

1 1 ( ) ( ) ( ) n s PFD LF VCO _{PFD LF} out VCO PFD LF VCO PFD LF VCO K Z (s)K K Z (s)K s H s = K Z (s)K K Z (s)K V s 1+ S + s N N φ = = ⋅ , (3-7) 2 2 ( ) ( ) ( ) n s VCO out VCO PFD LF VCO PFD LF VCO K K s H s = K Z (s)K K Z (s)K V s 1+ S + s N N φ = = ⋅ , (3-8) 3 3 ( ) ( ) ( ) n s out PFD LF VCO PFD LF VCO 1 S H s = K Z (s)K K Z (s)K V s 1+ S + s N N φ = = ⋅ . (3-9)

The noise transfer function of the reference noise and the filter’s components are low pass while that of VCO phase noise is high pass. Figure 3.6 shows the frequency response of different noise sources. If the reference noise varies rapidly, then output phase does not fully track the variations. Physically, the “phase-lock” characteristics of PLL essentially suppress high frequency fluctuation in phase error and track the reference phase. On the other hand, VCO tends to accumulate its noise fluctuations and high pass them to the output. To achieve better noise suppression, a moderate loop bandwidth should be chosen with a trade-off between the VCO’s noise and the reference noise [14].

Figure 3.6: Transfer function of noise sources

2 ( ) ( ) out n s V s φ 1 ( ) ( ) out n s V s φ 3 ( ) ( ) out n s V s φ

Chapter3Fractional-N Phase-Locked Loop with ΣΔ modulator

3.4 Fractional-N Frequency Synthesis

When the finer frequency resolution is required, the lower reference frequency could result in narrow loop bandwidth and low switching speed [15]. A larger division ratio will also cause larger noise amplification from reference to the synthesizer output [12]. Using fractional-N frequency synthesis has the advantage of synthesize non-integer multiple output frequency with a fixed reference signal. Thus the reference frequency will not limit by the loop bandwidth as in integer frequency synthesizers. The idea comes form implementing a frequency divider that can divide the frequency from the VCO by an integer number plus a fractional part of it.

Figure 3.7: A fractional-N frequency synthesizer with divider controller

A fractional-N frequency synthesizer with a divide ratio controller is shown in Figure 3.7. This controller is simply realized by a Digital Phase Accumulator (DPA), and clocked by the reference frequency. The DPA accumulates its output with a divider ratio setting word L at each clock cycle. The dual-modulus divider splits _div

its input by N as the DPA is not overflowed. As soon as overflow signal from the DPA appears, the dual-modulus divider divides its input by N+1. On average, by a

÷N/N+1 DPA PFD VCO Fout ref F div L register overflow ＋ CP LF

fractional value between N and N+1 can be revised as div avg DPA L N N L = + , (3-10) where the L_DPA means the length of DPA. Hence, the dual-modulus divider can have a infinite frequency resolution theoretically when we increase the L_DPA.

However, this structure has a serious problem. It will result in sawtooth phase error in PFD. This periodic phase error will be the frequency modulated by the VCO and generates fractional spurs in the output spectrum. As shown in Figure 3.8, the periodical switch signal of the divider ratio will result in sawtooth phase error in PFD output.

Figure 3.8: Sawtooth phase error

This periodic phase error will be frequency modulated by the VCO and generates fractional spurs in the output spectrum. As shown in Figure 3.9, the resulting fractional spurs is typically only 20 or 30 dB below center frequency and will serious degrade the purity of output spectrum [12].

Figure 3.9: Spurious noise in VCO output spectrum Center frequency Fractional spurs Divider out ref. clock ÷N ÷N+1 t Phase error

Chapter3Fractional-N Phase-Locked Loop with ΣΔ modulator

In fact, the DPA can be viewed as the first-order sigma-delta modulator. Theoretically, the higher order sigma-delta modulator suppresses more fractional spurs. Details for sigma-delta modulator techniques will be discussed later.

3.5 Sigma-Delta Modulator

Sigma-delta modulator (ΣΔ modulator) is widely used for Analog-to-Digital converters (ADC) and Digital-to-Analog converters (DAC) applications. The ΣΔ

modulator leaves the average input unchanged and modulates the quantization noise to higher frequency [16]. In conventional sigma-delta DAC, the output of the modulator is followed by an analog low pass filter in order to remove quantization noise. Due to low pass characteristic of PLL, the out band quantization noise can be suppressed by higher order poles.

A first-order ΣΔ modulator is shown in Figure 3.10(a). The input signal feeds to the quantizer through an integrator, then the integrated output is quantized and fed back to subtract the input signal. The subtraction forms a negative feedback system and forces the quantized output to track the long term average of input signal. With the quantization set to two levels, an all digital ΣΔ modulator can be converted to the form given by Figure 3.10(b). Such a first-order ΣΔ modulator is also called DPA, which is described previous. DPA can totally replace the ΣΔ modulator in all digital applications such as DAC and fractional-N frequency synthesis [17].

Figure 3.10: Block diagram of first-order (a) ΣΔ modulator, (b) DPA representation D - n Q Vout in V in V out V register n Q - + (a) (b)

To analyze the first-order ΣΔ modulator, several assumptions must be made so that the linear model can be applied [18], and the linear model of a first-order ΣΔ modulator is shown in Figure 3.11. The quantization noise can be thought of as white noise that is uncorrelated to the input signal under linear assumption. Thus, the quantizer is simply equivalent to an adder that adds the quantization noise source to the integrated signal.

Figure 3.11: Linear model of first-order sigma-delta modulator In z domain, the transfer function of first-order ΣΔ modulator can be written as

1 1

( ) ( ) ( )(1 )

Y z ₌X z z_⋅ − ₊E z ₋z− _{, (3-11)}

where _z−1 _{term is referred to as STF (Signal Transfer Function) and 1 z−} −1 _{is NTF}

(Noise Transfer Function) in this modulator.

The absolute value of STF should be unity to track the input average value in the long term. It is known that an additional zero in the origin will make transfer function slope sharper by 20 dB/dec. Using more zeros at the origin can enhance the high-pass characteristics of ΣΔ modulator. The NTF of higher order ΣΔ modulator can be written as( - z )1 -1 m, where m is the order of modulator. After integration, the fluctuation in frequency is converted to phase domain and represented as phase noise. The detail mathematical calculation is refer to [19], and the power spectrum density of NTF can be written as 2 2 2 (m-1) s s (2π) f L(f)= sin(π ) 12f f ⎡ ⎤ ⋅ ⎢ ⎥ ⎣ ⎦ , (3-12) where f is oversampling rate and m is order of ΣΔ modulator. _s

i X Yi i e i W D -

Chapter3Fractional-N Phase-Locked Loop with ΣΔ modulator

The phase noise generated by quantization noise of ΣΔ modulator is plotted with second-order, third-order and fourth-order structures as shown in Figure 3.12. The improvement in Signal-to-Noise Ratio (SNR) is significant especially when higher

order ΣΔ modulator is used.

Figure 3.12: Quantization noise of second to fourth ΣΔ modulator

With oversampling and noise shaping characteristics, ΣΔ modulators are quite suitable for fractional-N synthesis applications. With higher order modulation, the quantization noise is pushed more out of band and a higher SNR can be gained at a given oversampling ratio.

3.6 MASH 1-1-1 Sigma-Delta Modulator

Higher order ΣΔ modulator can suppress more fractional spurs effectively, but they tend to become “unstable”. The single-loop higher order ΣΔ modulator architecture offers a higher flexibility in terms of noise shaping; however, it has instability problem and is more complex. The Multi-Stage-Noise-Shaping (MASH)

modulator is another structure that can achieve high order noise shaping by cascade several first-order modulators. It can solve instability problem and can be designed easily. Figure 3.13 shows a typical third-order MASH 1-1-1 ΣΔ modulator that is formed by cascading three first-order ΣΔ modulators [20].

Figure 3.13: Third-order MASH 1-1-1 ΣΔ modulator

The quantization error of the first modulator is fed to the second modulator and the second modulator’s quantization error is fed to the third. The equations of the individual modulators can be written as

-1 1 1 -1 2 1 2 -1 3 2 3 Y (z)= X(z)+ E (z) (1- z ) Y (z)= -E (z)+ E (z) (1- z ) Y (z)= -E (z)+ E (z) (1- z ) ⋅ ⋅ ⋅ , (3-13) where E (z) ,₁ E (z) and₂ E (z) each represents the quantization noise of the three ₃

modulators. Combination of above equations, the transfer function of MASH 1-1-1 ΣΔ modulator is 2 3 -1 -1 1 2 3 -1 3 1 1 1

Y(z)= Y (z)+Y (z) ( - z )+Y (z) ( - z ) = X(z)+ E (z) ( - z )

⋅ ⋅

⋅ . (3-14) The quantization error of third-order modulator is noise shaped by placing three zeros at the origin.

1 z− 1 z− 1 z− 1 z− 1 z− 1 Y 1 E 2 Y 2 E 3 Y 3 E X Y

Chapter4Spread Spectrum Clock Generator Implementation

Chapter 4

Spread Spectrum Clock Generator

Implementation

4.1 Implementation of SSCG

There are many types of Spread Spectrum Clock Generator (SSCG) in the literature [21], [22], [23], [24]. Figure 4.1 shows the different approaches of SSCG. The first type modulates the VCO directly. Using another charge pump to generate the triangular wave in to the low pass filter and modulating the PLL output clock. Due to the process variation, this analog approach may need calibration to sure 5000 ppm spread amounts. The second type modulates the divider in a PLL to modulate the output frequency of PLL. The third type combines the multiphase circuits to achieve the spread-spectrum function. This approach needs multiphase and has large load, so the power consumption is very large. Finally, the forth type modulates the PLL output phases to the divider. The phase jump of it is less than type II, and the power consumption is lower than type III. In this thesis we accomplish the SSCG based on this architecture. Details for SSCG architecture of our design will be discussed latter.

Figure 4.1: Types of SSCG architecture ssc F ref F PFD CP LF VCO divider MUX (4) ssc F ref F PFD CP LF VCO divider frequency and (3) phase synthesizer ssc F ref F PFD CP LF VCO divider (2) ssc F ref F PFD CP LF VCO divider (1)

Chapter4Spread Spectrum Clock Generator Implementation

4.2 Spread Spectrum Clock Generator Architecture

A building block of the accomplished SSCG is shown in Figure 4.2. The SSCG is based on a fractional-N PLL using sigma-delta modulation technique. The address generator is used to produce a 30 kHz triangular modulation rate and a 5000 ppm frequency deviation of the SSCG. It is the control signal of the ΣΔ modulator. The controller receives the signals from ΣΔ modulator to control the multiplexer for select the suitable phase to divider. When the VCO output phases deliver to the divider be changed that is equivalent to change the divider ratio. Hence, when we modulated the VCO output phases and make the equivalent divider ratio is triangular modulation it will generate a triangular modulation profile on the loop filter to achieve our goal.

Although the power consumption of this architecture is larger but the phase jump is lower [24], and the modulation profile will be more smoothly. The behavior simulation results of the modulation divider type SSCG and the modulation VCO phases type SSCG will show in chapter 5.

Figure 4.2: System architecture of spread spectrum clock generator

„ Phase Frequency Detector

The Phase Frequency Detector (PFD) is composed of two D-flip flops (DFF) and a NOR gate, as shown in Figure 4.3 (a) [25]. When the outputs of two DFFs are

Generator divider ÷60 VCO Controller LF CP PFD MUX 20MHz 1.2GHz modulator ΣΔ 10 Address

both active, the two DFFs will be reset. The two transmission gates of PFD are used to balance the timing. The True Single Phase Clock (TSPC) type DFFs of the PFD are used at high speed operation as shown in Figure 4.3 (b).

Figure 4.3: Circuit schematic of (a) PFD (b) TSPC D flip-flop of PFD

The conventional PFD generates phase jitter since it does not have sufficient turn on time to change the control voltage when phase difference is within the dead zone. The advantage of this PFD is that it has no deadzone. Figure 4.4 is the timing diagram of this PFD. For in-phase inputs of F and _ref F , the charge pump will see _fb

both “UP” and “DOWN” pulses for the same short period of time. If there is a phase difference between F and _ref F , the distinction between the widths of UP and _fb

DOWN pulses will be proportional to the phase differences of the inputs.

U

Figure 4.4: Timing diagram of PFD

(a) (b) D CLK DOWN Q UP DOWN CLK CLK Q CLK D rst rst ref F fb F Q UP rst

in phase out of phase DOWN UP fb F ref F

Chapter4Spread Spectrum Clock Generator Implementation

„ Charge Pump

The charge pump (CP) is used to convert the logic states of the PFD into analog signals suitable for controlling the VCO. The architecture of CP is shown in Figure 4.5 [26], it consists of two current source, four current switches and an operational

amplifier (OP-amp). The unity gain buffer will maintain the voltage of intermediate

node to the same as the output node when the switch is off. Thus the charge in-jection will never occur when the switch is turned on. In this way, voltage glitches on the loop filter due to charge sharing can be eliminated.

Figure 4.5: Circuit schematic of charge pump

Figure 4.6 is the waveform of the CP. The PFD generates lead or lag message to the CP. The CP will charge or discharge the loop filter to vary the VCO output frequency according to the phase difference detected by PFD.

Figure 4.6: Waveform of charge pump

UP DOWN Buffer Bias UP DOWN Vout UP DOWN Vout lead lag

„ Loop Filter

The design of the loop filter determines most of the specifications of the PLL. Extra poles and zeros in the loop transfer function influence the noise and dynamic performance of the loop. The parameter of the loop filter should be carefully designed. As shown in Figure 4.7, we consider second-order loop filter to design type-II current mode charge pump PLL system.

Figure 4.7: Schematic of second-order filter The impedance of second-order filter in Figure 4.7 is

2 2 2 2 1 1 2 2 1 2 1 1 1 1 1 sR C + Z(s)= R + // = sC sC s(C +C ) sR (C //C )+ ⎡⎛ ⎞ ⎤ ⋅ ⎢⎜_⎜ ⎟_⎟ ⎥ ⎢_{⎝ ⎠} ⎥ ⎣ ⎦ . (4-1) Then, we can define the time constants which determine the pole and zero frequencies of the filter

1 2( 1// 2)

T =R C C , T₂=R C_{2 2}. (4-2) Generally, we can design the loop filter using open loop gain bandwidth ω_p and phase margin φ_p to determine the passive component values [27]. High phase margins provide with stable system and can decrease peaking response of the loop filter at the expense of degrading the lock time of the PLL. In general, the phase margin is chosen between 45 and 60 degrees. Choosing the loop bandwidth too small will yield a design with improved reference spurs and RMS phase error, but will increase the locking time. In general, the suggested method of choosing the loop

to VCO CP out 2 C 1 C R2

Chapter4Spread Spectrum Clock Generator Implementation

bandwidth is to choose it so that it is sufficient to meet the lock time requirement with sufficient phase margin.

Locating the point of minimum phase shift at the unity gain frequency of the open loop response as shown in Figure 4.8 ensures loop stability.

Figure 4.8: Open loop response bode plot The formulas for T₁ and T₂ are shown in Eq. 4-3.

1 sec _p tan _p p T φ φ ω − = , ₂ 1 2 1 p T T ω ⋅ = . (4-3) Then, we can achieve passive component values as

2 2 2 1 1 2 2 1 1 ( ) 1 ( ) p PFD VCO p p T K K T C T N T ω ω ω + ⋅ = + ⋅ , (4-4) 2 1 ( ) 2 2 1 T C C T ⋅ = − , (4-5) 2 2 2 T R C = , (4-6) where K_PFD, K_VCO, N are gain of the PFD, gain of the VCO and the divider ratio.

The out-band quantization noise from ΣΔ modulator will be suppressed by the low-pass characteristic of the PLL. But ΣΔ modulator will introduce current switching

p φ 0dB Frequency -90 -180 p ω G(s)H(s) Phase G(s)H(s) ∠ Gain

noise in the divider and CP at the reference rate. This may cause unwanted FM sidebands at RF output. As shown in Figure 4.9, an additional pole of third-order loop filter can be added to suppress the reference spur.

Figure 4.9: Schematic of third-order loop filter The added attenuation from the low-pass filter is

ATTEN = 20 log [(2 ) 1]F_ref R C_{3 3} 2 + , (4-7) and we can define the additional filter time constant as

3 3 3

T =R C . (4-8) Then, in terms of the attenuation of the reference spurs added by the low pass pole the formulas for T can be expressed as ₃

10 2 3 10 1 (2 ) ATTEN ref T F π − = ⋅ . (4-9) In general, we can choose 1

3 ₁₀ C C = , then 3 3 3 T R C = .

The PLL becomes a higher order loop and stability is an important issue. So, one must be careful in determining the loop bandwidth of the system. A PLL needs a sufficiently large loop bandwidth to track the modulation rate of SSCG. But, we need to choose a small loop bandwidth to suppress the reference spur and the RMS phase error. In general, the loop bandwidth need to meet the RMS phase error to reduce jitter and it is sufficient to track the modulation rate. According to [28], the dynamic

2 C 1 C R2 3 R 3 C to VCO CP out

Chapter4Spread Spectrum Clock Generator Implementation

range of the Lth-order ΣΔ modulator should meet the following condition

2 2 1 2 3 2 1 ( ) 2 L PFD eff L n f L OSR f π + ⎛ ⎞ + ⋅ ⋅ _{> ⎜ ⎟} Δ ⎝ ⎠ , (4-10) whereOSR_eff , f_PFD, Δ are the oversampling ratio and the bandwidth of the PFD f_n

and the in-band noise respectively. So the approximate upper bound of the loop bandwidth is obtained as (1/2 1) 2 2 0.5 2 (2 ) c L rms PFD L L f θ f π − ⎡_{⎛ ⎞ +} ⎤ ⎢ ⎥ < _{⎜ ⎟} ⋅ ⋅ ⎢⎝ ⎠ ⎥ ⎣ ⎦ , (4-11) whereθ_rms[rms rad] is the in-band phase error.

In our design, when the reference frequency of PFD is 20 MHz, the upper bound of the bandwidth with a third-order ΣΔ modulator to have less than 10 _{RMS phase}

error is about 448 kHz.

„ Voltage Controlled Oscillator

In a conventional ring oscillator, the oscillation frequency is determined as

1/Nτ , where N is the number of stages and τ is the unit delay time of a delay cell.

Hence the frequency of the oscillator is decided by the delay time of one delay element. The maximum frequency of the VCO is limited by the delay time of the basic inverter delay cell. Using a dual-delay scheme to implement the VCO, high operation frequency and wider tuning range are achieved simultaneously [29]. Figure 4.10 shows the circuit schematic of the VCO, which includes a 5-stage ring oscillator for frequency tuning. The dual-delay cell of ring oscillator has both the negative skewed delay paths and the normal delay paths. The negative skewed delay paths decrease the unit delay time of the ring oscillator below the single inverter delay time. As a result, higher operation frequency can be obtained.

(a) 5-stage ring oscillator

(b) delay cell of ring oscillator Figure 4.10: Circuit schematic of VCO

„ Address Generator

The Serial-ATA (Serial-ATA) systems require the SSCG with a down spreading of 5000 ppm and a 30 kHz modulation rate. One can use address generator to determine the above required parameter. As shown in Figure 4.11, the address generator consists of an up/down counter and some logic gates [30]. The outputs of up/down counter are used to control the ΣΔ modulator and that produce a triangular waveform to make the frequency spreading. The more bit number of the up/down counter is used, the more accurate shape of triangular waveform will be. In this thesis, we use a 10 bit up/down counter to perform the address generator.

in2+ in2- in1-out- out+ in1+ vctrl in2+ in2- in1- out-out+ in1+ in2+ in2- in1- out-out+ in1+ in2+ in2- in1- out-out+ in1+ in2+ in2- in1- out-out+ in1+ in2+ in2- in1- out-out+ in1+

Chapter4Spread Spectrum Clock Generator Implementation

Figure 4.11: Architecture of address generator

„ Third-order MASH 1-1-1 Sigma-Delta Modulator

Higher order ΣΔ modulator can suppress more fractional spurs effectively, but they tend to become “unstable”. The single-loop architecture offers a higher flexibility in terms of noise shaping; however, it has instability problem and is more complex. The Multi-Stage-Noise-Shaping (MASH) modulator can solve instability problem and can be implemented using all digital architectures. Thus, it can be easily integrated into single chip and is insensitive to process variation.

By performing linear analysis on this model in section 3.6, the input/output relationship of this modulator can be found as follow

3

-1

3 1

Y(z)= X(z)+ E (z) ( - z )⋅ , (4-12) where X z( ) , Y z( ), and E z₃( ) are the Z-transform of the input, output and quantization noise from three stages respectively.

The quantization error of the third-order ΣΔ modulator is noise shaped by placing three zeros at the origin. The quantization error is shaped and pushed to high frequency and then the closed loop behavior of PLL will filter it out. Using DPA to realize MASH 1-1-1 architecture is shown in Figure 4.12. With the advantage of all digital implementation in synthesizer applications, there is no analog mismatch problem for MASH type modulator.

control 10 to ΣΔmodulator clk 10 bit logic up/down counter

Figure 4.12: Digital realization of MASH 1-1-1 ΣΔ modulator

The input range and output spreading for a MASH 1-1-1 ΣΔ modulator is shown in Figure 4.13 [28]. For a third-order MASH 1-1-1 ΣΔ modulator, it output has 8 levels. The output average is always between N and N+1, and the output average track the long term average of the input signal.

Figure 4.13: The input range and output spreading of MASH 1-1-1 ΣΔ modulator Input Output Output

N+4 N+3 N+2 N+1 N N-1 N-2 N-3

Average Levels Average Out In register - + register register register register -+ + 1 C C2 0 C

Chapter4Spread Spectrum Clock Generator Implementation

„ Controller

The controller receives the control signal from ΣΔ modulator and control the multiplexer for the phase selection. The controller is composed of a finite state

machine (FSM) and a barrel shifter. Due to that the MASH 1-1-1 ΣΔ modulator

output has 8 levels, as shown in Figure 4.13, it makes the phase shifted greatly. It may let the divider lose the rising edge of VCO output when phase changed. Thus, the SSCG won’t work successfully. The FSM makes the multiplexer shifted one phase at a time. The phase shifted one by one until complete the total phase shift. The FSM output signals control the data in the barrel shifter to rotate right, or left or hold the original value. When finishing the phase shift, the FSM will hold the data in the barrel shifter until it receives new control signal from the ΣΔ modulator for the phase shift.

The state table and state diagram of the FSM are show in Table 4.1 and Figure 4.14. The FSM receive the control signal from ΣΔ modulator and then change the state step by step to control the barrel shifter.

Table 4.1: State table of the FSM DSM output (Decimal number) present state next state Out (LRH) 4 A B 1 0 0 3 B C 1 0 0 2 C D 1 0 0 1 D E 1 0 0 0 E E 0 0 1 -1 F E 0 1 0 -2 G F 0 1 0 -3 H G 0 1 0

Figure 4.14: State diagram of the FSM

In fact, barrel shifter is a shifter register. In our design, we use a 3×10 barrel shifter in the controller which is shown in Figure 4.15. The 3-bit control signals from FSM are used to control the data in barrel shifter. The 10-bit data are used to control the multiplexer for phase selection and that are in one hot encoded. When FSM makes the data in barrel shifter rotated, the multiplexer changes the VCO output phases to the frequency divider.

Figure 4.15: The 3×10 barrel shifter

S1 Y10 DFF DFF DFF DFF S2 S3 Y9 Y2 Y1 Y10 Y9 Y1 Y9 Y8 Y10 Y2 Y1 Y3 Y1 Y10 Y2 A B C H G F E D

Chapter4Spread Spectrum Clock Generator Implementation

One of the ten DFFs in barrel shifter is a reset-to-one type DFF, and others are reset-to-zero type DFFs. The reset mechanism is used to control the SSCG in the non-SSC mode or the SSC mode. When reset ten DFF s, the output phase of the MUX is fixed and the SSCG is in the non-SSC mode. Otherwise the barrel shifter changes the output phase of MUX by the FSM control signals, and the SSCG is in the SSC mode.

„ Multiplexer

The multiplexer (MUX) is used to select the suitable phase to the divider from VCO and the controller outputs are used to contorl it. For our design, a 10-to-1 MUX is needed and we use a 2-to-1 MUX and two 5-to-1 MUXs to perform the 10-to-1 MUX as shown in Figure 4.16 [25]. The dummy PMOS of the MUX are used to avoid the leakge current effect of the NMOS. Table 4.2 shows the relation between control signals and output of the MUX. Figure 4.17 shows the waveform when the control signals of the controller make the MUX output shift one phase. As shown in Figure 4.17, changing the VCO output phase to the divider is equivalent to changing the divider ratio. Hence, we can spread the output frequency of VCO by changing the VCO phase to the divider.

Figure 4.16: Architecture of (a) 2-to-1 MUX (b) 5-to-1 MUX

C1 D1 D2 C2 (a) Out S1 P1 S2 P2 S3 S4 P4 S5 P5 Out (b) P3

Table 4.2: Relation between control signals and output of the MUX Control Signal 10 9 8 7 6 5 4 3 2 1 S S S S S S S S S S Output Phase 0 0 0 0 0 0 0 0 0 1 phase 1 0 0 0 0 0 0 0 0 1 0 phase 2 0 0 0 0 0 0 0 1 0 0 phase 3 0 0 0 0 0 0 1 0 0 0 phase 4 ……… …….

Figure 4.17: Waveform for the phase changed

„ Frequency Divider

In our design, a divide-by-60 divider is needed and we use a divide-by-3, a divide-by-4 and a divide-by-5 dividers to perform the division. The dividers are composed of DFFs and some simple logic gates. They are capable of dividing by these divisions. For operating at high speed, it is important to reduce the effective capacitance of internal and external nodes. It leads to the reduction of the propagation delay. The TSPC type DFFs have been widely used in many digital circuits because of it features of high operating speed and simple circuit requirement. Figure 4.18 shows the circuit schematic of the TSPC type DFF for the divider [26].

÷4 Original Signal Shift One Phase

Equivalent to ÷3.9

Chapter4Spread Spectrum Clock Generator Implementation

Figure 4.18: TSPC type D flip-flop D clk clk clk clk Q Q

Chapter 5

Simulation and Measurement Results

The spread spectrum clock generator using fraction-N PLL with ΣΔ modulator has many system design issues. We need to consider the stability problem, the loop bandwidth, and spreading ratio, etc. Hence, the system behavior simulation of SSCG is very important. In this chapter, we verify the spread spectrum clocking function from behavior simulation to circuit level simulation. Finally, we show the measurement results of our spread spectrum clock generator chip.

5.1 SSCG Behavior Simulation

We use SIMULINK to analyze the loop stability and verify the SSC function. Figure 5.1 shows the model of SSCG system which is based on a charge-pump PLL with a third-order loop filter. Figure 5.2 shows the SSCG behavior simulation. We can see a down spreading of 5000 ppm and a 30 kHz triangular modulation rate clearly.

Chapter5Simulation and Measurement Results

Figure 5.1: SIMULINK model of the SSCG system

Figure 5.2: SSCG behavior simulation

spread 5000ppm with 30 kHz triangular modulation

According to Eq. 4-11, we choose 400 kHz for the loop bandwidth and the phase margin is 60 degree. The open-loop response bode plot of this system is shown in Figure 5.3.

Figure 5.3: Bode plot of open-loop response

Figure 5.4 shows the FFT of SSCG at non-SSC mode and SSC mode. The peak amplitude reduction is about 20 dB. Figure 5.5 shows the comparison of two type of SSCGs. The triangular modulation waveform of modulation VCO phases type SSCG is smoother. The noise floor of this type is also lower as shown in Figure 5.6.

Chapter5Simulation and Measurement Results

Figure 5.5: Waveform of two type SSCGs

Figure 5.6: FFT comparison of two type SSCG

5.2 SSCG Circuit Level Simulation

The circuit level simulation of SSCG using HSPICE takes a significant amount of time but the results are more precise. Figure 5.7 shows the simulation of VCO tuning characteristics with corner model variation. The gain of VCO is about 400 MHz/V and the tuning range of the VCO is from 1.03 GHz to 1.37 GHz at TT corner. Figure 5.8 shows the eye diagram of VCO outputs at non-SSC mode and the

peak-to-peak jitter is 5.31 ps. Figure 5.9 shows the control voltage of VCO at SSC mode. We can see a frequency modulation by triangular waveform obviously. The voltage variation of VCO control voltage can be expressed as

6 15 400 / VCO f MHz V mV K MHz V Δ Δ = = = . (5-1) control voltage (V) 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 fr equency (Hz) 1.0e+9 1.1e+9 1.2e+9 1.3e+9 1.4e+9 1.5e+9 _TT FF SS SF FS

Figure 5.7: Tuning characteristic of VCO with corner model variation

Chapter5Simulation and Measurement Results

Figure 5.9: Control voltage of VCO at SSC mode

5.3 Testing Setup

Figure 5.10 shows the SSCG die photo. The chip area is 860um by 860um. The chip is implemented in TSMC 0.18 um CMOS 1P6M technology. Considering the speed and noise issues, the IC is un-packaged to reduce parasitic loading of the packages.

Figure 5.10: Micrograph of die

PFD &CP LF VCO di vi de r MUX SDM address controller gene rat or 15 mV 30 kHz