A building block of the accomplished SSCG is shown in Figure 4.2. The SSCG is based on a fractional-N PLL using sigma-delta modulation technique. The address generator is used to produce a 30 kHz triangular modulation rate and a 5000 ppm frequency deviation of the SSCG. It is the control signal of the ΣΔ modulator. The controller receives the signals from ΣΔ modulator to control the multiplexer for select the suitable phase to divider. When the VCO output phases deliver to the divider be changed that is equivalent to change the divider ratio. Hence, when we modulated the VCO output phases and make the equivalent divider ratio is triangular modulation it will generate a triangular modulation profile on the loop filter to achieve our goal.
Although the power consumption of this architecture is larger but the phase jump is lower [24], and the modulation profile will be more smoothly. The behavior simulation results of the modulation divider type SSCG and the modulation VCO phases type SSCG will show in chapter 5.
Figure 4.2: System architecture of spread spectrum clock generator
Phase Frequency Detector
The Phase Frequency Detector (PFD) is composed of two D-flip flops (DFF) and a NOR gate, as shown in Figure 4.3 (a) [25]. When the outputs of two DFFs are
Generator
both active, the two DFFs will be reset. The two transmission gates of PFD are used to balance the timing. The True Single Phase Clock (TSPC) type DFFs of the PFD are used at high speed operation as shown in Figure 4.3 (b).
Figure 4.3: Circuit schematic of (a) PFD (b) TSPC D flip-flop of PFD
The conventional PFD generates phase jitter since it does not have sufficient turn on time to change the control voltage when phase difference is within the dead zone. The advantage of this PFD is that it has no deadzone. Figure 4.4 is the timing diagram of this PFD. For in-phase inputs of F and ref F , the charge pump will see fb both “UP” and “DOWN” pulses for the same short period of time. If there is a phase difference between F and ref F , the distinction between the widths of UP and fb DOWN pulses will be proportional to the phase differences of the inputs.
U
Figure 4.4: Timing diagram of PFD
(a) (b)
Chapter4Spread Spectrum Clock Generator Implementation
Charge Pump
The charge pump (CP) is used to convert the logic states of the PFD into analog signals suitable for controlling the VCO. The architecture of CP is shown in Figure 4.5 [26], it consists of two current source, four current switches and an operational amplifier (OP-amp). The unity gain buffer will maintain the voltage of intermediate node to the same as the output node when the switch is off. Thus the charge in-jection will never occur when the switch is turned on. In this way, voltage glitches on the loop filter due to charge sharing can be eliminated.
Figure 4.5: Circuit schematic of charge pump
Figure 4.6 is the waveform of the CP. The PFD generates lead or lag message to the CP. The CP will charge or discharge the loop filter to vary the VCO output frequency according to the phase difference detected by PFD.
Figure 4.6: Waveform of charge pump
UP
DOWN
Buffer
Bias
UP
DOWN
Vout
UP DOWN
Vout
lead lag
Loop Filter
The design of the loop filter determines most of the specifications of the PLL.
Extra poles and zeros in the loop transfer function influence the noise and dynamic performance of the loop. The parameter of the loop filter should be carefully designed.
As shown in Figure 4.7, we consider second-order loop filter to design type-II current mode charge pump PLL system.
Figure 4.7: Schematic of second-order filter
The impedance of second-order filter in Figure 4.7 is
2 2 2
Then, we can define the time constants which determine the pole and zero frequencies of the filter
1 2( 1// 2)
T =R C C , T2=R C2 2. (4-2) Generally, we can design the loop filter using open loop gain bandwidth ωp and phase margin φp to determine the passive component values [27]. High phase margins provide with stable system and can decrease peaking response of the loop filter at the expense of degrading the lock time of the PLL. In general, the phase margin is chosen between 45 and 60 degrees. Choosing the loop bandwidth too small will yield a design with improved reference spurs and RMS phase error, but will increase the locking time. In general, the suggested method of choosing the loop
to VCO CP out
C2
C1 R2
Chapter4Spread Spectrum Clock Generator Implementation
bandwidth is to choose it so that it is sufficient to meet the lock time requirement with sufficient phase margin.
Locating the point of minimum phase shift at the unity gain frequency of the open loop response as shown in Figure 4.8 ensures loop stability.
Figure 4.8: Open loop response bode plot
The formulas for T1 and T2 are shown in Eq. 4-3.
Then, we can achieve passive component values as
2
The out-band quantization noise from ΣΔ modulator will be suppressed by the low-pass characteristic of the PLL. But ΣΔ modulator will introduce current switching
φp
noise in the divider and CP at the reference rate. This may cause unwanted FM sidebands at RF output. As shown in Figure 4.9, an additional pole of third-order loop filter can be added to suppress the reference spur.
Figure 4.9: Schematic of third-order loop filter
The added attenuation from the low-pass filter is
ATTEN = 20 log [(2 ) 1]Fref R C3 3 2 + , (4-7) and we can define the additional filter time constant as
3 3 3
T =R C . (4-8) Then, in terms of the attenuation of the reference spurs added by the low pass pole the formulas for T can be expressed as 3
The PLL becomes a higher order loop and stability is an important issue. So, one must be careful in determining the loop bandwidth of the system. A PLL needs a sufficiently large loop bandwidth to track the modulation rate of SSCG. But, we need to choose a small loop bandwidth to suppress the reference spur and the RMS phase error. In general, the loop bandwidth need to meet the RMS phase error to reduce jitter and it is sufficient to track the modulation rate. According to [28], the dynamic
C2
Chapter4Spread Spectrum Clock Generator Implementation
range of the Lth-order ΣΔ modulator should meet the following condition
2 and the in-band noise respectively. So the approximate upper bound of the loop bandwidth is obtained as
In our design, when the reference frequency of PFD is 20 MHz, the upper bound of the bandwidth with a third-order ΣΔ modulator to have less than 10 RMS phase error is about 448 kHz.
Voltage Controlled Oscillator
In a conventional ring oscillator, the oscillation frequency is determined as 1/Nτ , where N is the number of stages and τ is the unit delay time of a delay cell.
Hence the frequency of the oscillator is decided by the delay time of one delay element. The maximum frequency of the VCO is limited by the delay time of the basic inverter delay cell. Using a dual-delay scheme to implement the VCO, high operation frequency and wider tuning range are achieved simultaneously [29]. Figure 4.10 shows the circuit schematic of the VCO, which includes a 5-stage ring oscillator for frequency tuning. The dual-delay cell of ring oscillator has both the negative skewed delay paths and the normal delay paths. The negative skewed delay paths decrease the unit delay time of the ring oscillator below the single inverter delay time.
As a result, higher operation frequency can be obtained.
(a) 5-stage ring oscillator
(b) delay cell of ring oscillator Figure 4.10: Circuit schematic of VCO
Address Generator
The Serial-ATA (Serial-ATA) systems require the SSCG with a down spreading of 5000 ppm and a 30 kHz modulation rate. One can use address generator to determine the above required parameter. As shown in Figure 4.11, the address generator consists of an up/down counter and some logic gates [30]. The outputs of up/down counter are used to control the ΣΔ modulator and that produce a triangular waveform to make the frequency spreading. The more bit number of the up/down counter is used, the more accurate shape of triangular waveform will be. In this thesis, we use a 10 bit up/down counter to perform the address generator.
in2- in2+
Chapter4Spread Spectrum Clock Generator Implementation
Figure 4.11: Architecture of address generator
Third-order MASH 1-1-1 Sigma-Delta Modulator
Higher order ΣΔ modulator can suppress more fractional spurs effectively, but they tend to become “unstable”. The single-loop architecture offers a higher flexibility in terms of noise shaping; however, it has instability problem and is more complex.
The Multi-Stage-Noise-Shaping (MASH) modulator can solve instability problem and can be implemented using all digital architectures. Thus, it can be easily integrated into single chip and is insensitive to process variation.
By performing linear analysis on this model in section 3.6, the input/output relationship of this modulator can be found as follow
-1 3
3 1
Y(z)= X(z)+ E (z) ( - z )⋅ , (4-12) where X z( ) , Y z( ), and E z3( ) are the Z-transform of the input, output and quantization noise from three stages respectively.
The quantization error of the third-order ΣΔ modulator is noise shaped by placing three zeros at the origin. The quantization error is shaped and pushed to high frequency and then the closed loop behavior of PLL will filter it out. Using DPA to realize MASH 1-1-1 architecture is shown in Figure 4.12. With the advantage of all digital implementation in synthesizer applications, there is no analog mismatch problem for MASH type modulator.
control
Figure 4.12: Digital realization of MASH 1-1-1 ΣΔ modulator
The input range and output spreading for a MASH 1-1-1 ΣΔ modulator is shown in Figure 4.13 [28]. For a third-order MASH 1-1-1 ΣΔ modulator, it output has 8 levels. The output average is always between N and N+1, and the output average track the long term average of the input signal.
Figure 4.13: The input range and output spreading of MASH 1-1-1 ΣΔ modulator Input Output Output
Chapter4Spread Spectrum Clock Generator Implementation
Controller
The controller receives the control signal from ΣΔ modulator and control the multiplexer for the phase selection. The controller is composed of a finite state machine (FSM) and a barrel shifter. Due to that the MASH 1-1-1 ΣΔ modulator output has 8 levels, as shown in Figure 4.13, it makes the phase shifted greatly. It may let the divider lose the rising edge of VCO output when phase changed. Thus, the SSCG won’t work successfully. The FSM makes the multiplexer shifted one phase at a time. The phase shifted one by one until complete the total phase shift. The FSM output signals control the data in the barrel shifter to rotate right, or left or hold the original value. When finishing the phase shift, the FSM will hold the data in the barrel shifter until it receives new control signal from the ΣΔ modulator for the phase shift.
The state table and state diagram of the FSM are show in Table 4.1 and Figure 4.14. The FSM receive the control signal from ΣΔ modulator and then change the state step by step to control the barrel shifter.
Table 4.1: State table of the FSM DSM output
Figure 4.14: State diagram of the FSM
In fact, barrel shifter is a shifter register. In our design, we use a 3×10 barrel shifter in the controller which is shown in Figure 4.15. The 3-bit control signals from FSM are used to control the data in barrel shifter. The 10-bit data are used to control the multiplexer for phase selection and that are in one hot encoded. When FSM makes the data in barrel shifter rotated, the multiplexer changes the VCO output phases to the frequency divider.
Figure 4.15: The 3×10 barrel shifter
S1
DFF Y10
DFF
DFF
DFF
S2 S3
Y9
Y2
Y1
Y10 Y9 Y1
Y9 Y8 Y10
Y2 Y1 Y3
Y1 Y10 Y2
A B
C
H G F
E D
Chapter4Spread Spectrum Clock Generator Implementation
One of the ten DFFs in barrel shifter is a reset-to-one type DFF, and others are reset-to-zero type DFFs. The reset mechanism is used to control the SSCG in the non-SSC mode or the SSC mode. When reset ten DFF s, the output phase of the MUX is fixed and the SSCG is in the non-SSC mode. Otherwise the barrel shifter changes the output phase of MUX by the FSM control signals, and the SSCG is in the SSC mode.
Multiplexer
The multiplexer (MUX) is used to select the suitable phase to the divider from VCO and the controller outputs are used to contorl it. For our design, a 10-to-1 MUX is needed and we use a 2-to-1 MUX and two 5-to-1 MUXs to perform the 10-to-1 MUX as shown in Figure 4.16 [25]. The dummy PMOS of the MUX are used to avoid the leakge current effect of the NMOS. Table 4.2 shows the relation between control signals and output of the MUX. Figure 4.17 shows the waveform when the control signals of the controller make the MUX output shift one phase. As shown in Figure 4.17, changing the VCO output phase to the divider is equivalent to changing the divider ratio. Hence, we can spread the output frequency of VCO by changing the VCO phase to the divider.
Figure 4.16: Architecture of (a) 2-to-1 MUX (b) 5-to-1 MUX
C1
Table 4.2: Relation between control signals and output of the MUX Control Signal
10 9 8 7 6 5 4 3 2 1
S S S S S S S S S S Output Phase 0 0 0 0 0 0 0 0 0 1 phase 1 0 0 0 0 0 0 0 0 1 0 phase 2 0 0 0 0 0 0 0 1 0 0 phase 3 0 0 0 0 0 0 1 0 0 0 phase 4
……… …….
Figure 4.17: Waveform for the phase changed
Frequency Divider
In our design, a divide-by-60 divider is needed and we use a divide-by-3, a divide-by-4 and a divide-by-5 dividers to perform the division. The dividers are composed of DFFs and some simple logic gates. They are capable of dividing by these divisions. For operating at high speed, it is important to reduce the effective capacitance of internal and external nodes. It leads to the reduction of the propagation delay. The TSPC type DFFs have been widely used in many digital circuits because of it features of high operating speed and simple circuit requirement. Figure 4.18 shows the circuit schematic of the TSPC type DFF for the divider [26].
÷4 Original Signal
Shift One Phase Equivalent
to ÷3.9
Chapter4Spread Spectrum Clock Generator Implementation
Figure 4.18: TSPC type D flip-flop D clk
clk clk
clk
Q Q
Chapter 5
Simulation and Measurement Results
The spread spectrum clock generator using fraction-N PLL with ΣΔ modulator has many system design issues. We need to consider the stability problem, the loop bandwidth, and spreading ratio, etc. Hence, the system behavior simulation of SSCG is very important. In this chapter, we verify the spread spectrum clocking function from behavior simulation to circuit level simulation. Finally, we show the measurement results of our spread spectrum clock generator chip.