**2.2 Stability Analysis of the Multiphase Converter with the PRCB Technique**

**2.2.3 System Stability Analysis**

In spite of the disturbance of input voltage and load current, eventually, the equivalent model of the PRCB technique with the TM current balance is depicted in Fig. 12. Except for the voltage loop, the TM current balance loop as well as the cross coupling loop are also included. The voltage loop is defined as (15).

( ) ( ) ( ) ( )

*v* *c* *MV* *vd*

*T s* =*G s F G* *s H s* (15)

*In the current balance loop, the two-phase inductor currents are sensed by the R**i** and hold *
*by the sample-and-hold circuits to generate the signals, V*_{SH1}*(s) and V*_{SH2}*(s). The sensing and *
sampling effect will introduce a pair of complex RHP zeros at half of the switching frequency
[28]. The transform function can be expressed as (16).

2

22

Fig. 12. Equivalent model of dual-phase buck converter with the PRCB technique and the TM current balance.

*The difference of the V**SH1**(s) and the V**SH2**(s) will be amplified by operational *

*transconductance amplifier A*_{OTA}*(s) to obtain the current balance control voltages, V*_{IC1}*(s) and *
*V**IC2**(s). The V-to-I converter G**V-I**(s) converts the V**IC1**(s) and the V**IC2**(s) to the current balance *
*control currents, the I*_{C1}*(s) and the I*_{C2}*(s), respectively, which can adjust the d*_{1}*(s) and the d*_{2}*(s), *
respectively. The duty-to-current transform function is derived in (17) for each phase.

( )

The characteristic of current loop is the crucial of the TM current balance technique.

Ideally, a stable current loop will not have influence on the output voltage. Furthermore, the

23

operation of current balance loop is independent of load current but relies on the difference of the dual-phase inductor currents. Therefore, the output can be regarded as shorted ground. The duty-to-current transform function is modified as (18).

0

Since the TM current balance scheme is based on the average current balance control, the small signals in two phases are the same in magnitude and opposite in phase [34]. That is,

1 2

ˆ ˆ

*SH* *SH*

*V* = −*V* , _{V}^{ˆ}_{IC}_{1}= −_{V}^{ˆ}_{IC}_{2}, _{I}^{ˆ}_{C}_{1}= −_{I}^{ˆ}_{C}_{2} , _{d}^{ˆ}_{1}_{= −}_{d}^{ˆ}_{2}, and _{I}^{ˆ}_{L}_{1}_{= −}_{I}^{ˆ}_{L}_{2} . Consequently, the two loops in
dual-phase operation become symmetric and thus are added as shown in Fig. 13. Thus, the
TM current balance loop gain is derived as (19).

( ) 2 ( ) ( ) ( ) ( ) ( )

Fig. 13. Small signal model of the TM current balance loop.

Ideally, the inductor current is controlled by its own current balance control signal.

However, the inductor current in one phase will be affected by the change in duty cycle of another phase inevitably [47]. Therefore, the cross coupling effect has to be taken into consideration in system stability analysis. The cross coupling duty-to-current transform function can be derived as (20).

24

And the cross coupling loop can be defined as (21).

( ) ( ) ( ) ( ) * ^{cc}*( ) ( )

*cc* *OTA* *V I* *MC* *MV* *id* *i* *e*

*T* *s* = −*A* *s G* _{−} *s F* *s F G* *s R H s* (21)

In the proposed structure, a compensation capacitor is located at the output of the
*operational transconductance amplifier. The added compensation pole not only ensures the *
*stability of current balance loop T**cb**(s) but also compensates the cross coupling loop T**cc**(s). *

*The bode plot of loops T*_{v}*(s), T*_{cb}*(s) and T*_{cc}*(s) is shown in Fig. 14. The DC gain and the phase *
*margin of the T**v**(s) are 91.9 dB and 51*^{∘ }*while the DC gains and the phase margins of the T**cb**(s) *
*and the T*_{cc}*(s) are (24.7 dB, 52*^{∘}) and (12.2dB, 86^{∘}), respectively. With the stabilized loops, the
system stability is assured.

**Bode Diagram**

**Bode Diagram**

25

Moreover, the voltage loop dominates the operation of the whole multi-phase system. In other words, the voltage loop gain is designed to be higher the current balance loop gain.

Bandwidths of both loops are desired as large as possible in general design to accelerate the transient response. However, the enlarged bandwidth of the current balance loop would slow down load transient response due to the lack of rapidly increasing inductor current. For instance, in case of light-to-heavy load variation, one of the phases must suddenly prolong the on-time to cope with the lack of energy. Consequently, it causes current unbalance inevitably.

Simultaneous, the current balance loop will start to pull down the unbalance inductor current.

Owing to the enlarged bandwidth, the suppression of energy provided to output will be reduced by the fast current balance loop. More switching cycles are needed to regulate output voltage. As a result, loop gain and bandwidth of the two loops have to be carefully designed to meet the specification.

26

**Chapter 3 **

**C** ^{IRCUIT } **I** **MPLEMENTATION** **3.1 Current Sensing Circuit **

^{IRCUIT }

For current balance, the inductor current information of each phase needs to be detected to
modulate the individual duty cycles. The simplest way to achieve current sensing is to
implement an auxiliary resistor in series with the power switch. It induces large power
dissipation so as to deteriorate the power conversion efficiency [47]-[48]. Therefore, Fig. 15
shows the utilized current sensing circuit with the replica current flowing through the sensing
*switch [10]. The power transistor M** _{P}* conducts the inductor current during its turn-on period.

*The common-gate amplifier, which is composed of M**2**-M**5*, can ensure the near
*source-to-drain voltages between the M*_{P}* and the sensing MOSFET M** _{S1}*. Thus, the sensing

*current I*

*sen*

*as the replica of the inductor current depends on the aspect ratio between the M*

*P*

*and the M** _{S1}*.

*The I**sen** flows through the M**6** and the sensing resistor R**S* to carry out the current sensing
*signal V*_{S}*. Besides, to enhance the current sensing accuracy, the M** _{7}*, which has the same aspect

*ratio as the current mirror structure, the M*

*2*

*and the M*

*3*, is added to provide a compensative

*current, I*

*. Moreover, the sensing speed of the proposed current sensing circuit can be improved since the common-gate gain stage derives large operation bandwidth since no compensation component is demanded in this structure [49].*

_{B}27

Fig. 15. The current sensing circuit.

**3.2 Current Balance Circuit **

Current balance mechanism in the multiphase structure can ensure equivalent current
driven capability of each phase. As shown in Fig. 16, the proposed current balance circuit,
which contains the current matching unit and the voltage averaging element, is used to adjust
the saw-tooth signal generated by the pseudo-ramp generator circuit, as well as the duty
*cycles for matched inductor current levels. The sensing signals, V**S1** and V**S2*, derived from the
current sensing circuits will be sent into the current matching unit. The sample-and-hold (SH)
*circuit is activated to obtain the voltages, V**SH1** and V**SH2*, for representing the average inductor
current level of each phase.

To get an accurate current balance, the voltage averaging element is used to derive the
*average value V** _{avg}* for the phase current distribution. That is, a high-gain operational
transconductance amplifier (OTA) is realized to reflect the current difference between the
average value and each of the phases. The voltage difference will be amplified to generate the

*current balance control signals, V*

*IC1*

*and V*

*IC2*

**. V***IC1*

*and V*

*IC2*are converted to the difference

*injection currents I*

_{C1}*and I*

*, respectively, which are injected into the pseudo-ramp generator for current balance. Since the high-gain OTA is chosen to enhance the current balance*

_{C2}28

*accuracy, the capacitor C**c* is used to stabilize the current-loop operation. As a result, both of
the on-chip and off-chip mismatch issues will be well compensated through the current
balance control scheme. Only one controller is utilized to achieve high accuracy and area and
conversion efficiency in the proposed PRCB technique.

**R**_{1}

Fig. 16. Current balance circuit.

**3.3 Pseudo-Ramp Generator **

*Fig. 17(a) shows the schematic of the pseudo-ramp generator. A fixed frequency signal V**clk*

*is derived through the fixed frequency generator composed of M*_{1}*-M*_{7}* and the capacitor C** _{1}*.

*The reference voltages V*

*H*

*and V*

*L*are derived from the bandgap circuit to determine the

*frequency of V*

_{clk}*with the bias current I*

_{B}*. Thus, the V*

*can be used to control the switches,*

_{clk}*M*

*9*

*and M*

*10*

*, to generate the saw-tooth signal V*

*SAW*through the charging and discharging of

*C*

*for achieving the PRCB technique.*

_{ramp}*Suppose the dual-phase inductor currents are well balanced, the I**C1** and the I**C2* must be

29

*equal. That is, each of the ramps of V**SAW* is identical so as to realize the same duty cycle for
the dual-phase operation. However, once the current unbalance operation occurs, the current
*balance circuit will detect the current difference between the two phases to modulate the I**C1*

*and the I*_{C2}* and thus to modify the V*_{SAW}*. By alternatively injecting the I*_{C1}* and the I** _{C2}*, the odd

*and even ramps in the V*

*SAW*will be changed to adaptively adjust the duty cycles as well as the dual-phase inductor currents. The compensated current injection is also controlled by the

*signal V*

*MODE*to properly generate the pseudo-ramp signal for different operation modes.

The timing diagram of the pseudo-ramp generator circuit is depicted in Fig. 17(b).

*Moreover, a frequency divider is implemented to carry out the two phase clocks, V**ck1** and V**ck2*,
*for the dual-phase operation. The V*_{ck1}* and the V** _{ck2}*, indicate the beginning of the switching
cycle of phase 1 and phase 2, respectively. Consequently, the phase control logic can produce
individual duty cycle for each power stage.

Fixed frequency

30

### V

clk### V

ck1### V

ck2### V

SEL### V

MODE### V

SAW1 0

(b)

Fig. 17. The pseudo-ramp generator. (a) Schematic (b) Time diagrams

**3.4 Phase Control Logic **

Fig. 18 shows the implementation and the operation of phase control logic. Fig.18(a)
shows the schematic of phase control logic, which is composed of the duty generator unit and
*the mode transition unit. The signals V**clk**, V**ck1**, and V**ck2* are generated from the pseudo-ramp
*generator. The V*_{ck1}* and the V** _{ck2}* are used to indicate phase 1 and phase 2, respectively, because

*there is only one saw-tooth signal to determine the duty cycle. The V*

*PWM*is the resultant duty

*determination derived from the comparison of the V*

_{SAW}*and the V*

*in the proposed*

_{C}*pseudo-ramp operation. The V*

*ck1*

*and the V*

*ck2*

*can activate the D*

*1*

*and the D*

*2*, respectively. In

*the meanwhile, the rising edge of the V*

*is used to reset the duty cycles and thus wait for the next triggering. The operation time diagram is depicted in Fig. 18(b).*

_{PWM}The mode transition unit is used to decide the operation mode according to the duty cycle.

*With a continuously increasing duty cycle in the Mode I, the D**1** or the D**2* would overlap with
*the V*_{ck2}* or the V*_{ck1}*, respectively. Thus, the V*_{M1}* or the V** _{M4}* will indicate the exceeding duty

*cycle of 50 %. The overlapping of the D*

*1*

*and the V*

*ck2*

*(or that of the D*

*2*

*and the V*

*ck1*) represents that the duty cycle in the Mode I has taken over the full period of one physical

*ramp in the V*

*SAW*. Once it occurs, the operation mode will transit from the Mode I to the Mode II in order to obtain the sufficient duty cycles in the PRCB technique.

31

On the other hand, if the duty cycle is continuously decreasing in the Mode II, it would
*enter the boundary region of duty determination. When both the D*_{1}* and the D** _{2}* do not cover

*the entire period of the V*

*ck2*

*and the V*

*ck1*, respectively, the duty cycle is smaller than 50 %. To ensure the proper pseudo-ramp operation, the operation mode will change from the Mode II to the Mode I. Detailed flow chart of the mode transition operation is shown in Fig. 18(c).

D Q

32

**V**

_{ck1}**V**

**ck2**

**V**

_{MODE}_{1} **V**

_{1}

_{PWM}**D**

_{1}**D**

_{2}**0** **1**

**V**

_{SAW}^{V}

^{V}

^{C}**Duty cycle** **Duty cycle**

**V**

_{SET}(b)

### Start

Mode I or Mode II

IL1 Odd-Ramps
I_{L2} Even-Ramps

IL1 Even-Ramps
I_{L2} Odd-Ramps

VM1=1 VM4=1 VM2=1 VM3=1

Switch to Mode II (VMODE=0)

Switch to Mode I (VMODE=1)

YES YES

NO NO

### Mode I (V

MODE### =1)

### Mode II (V

MODE### =0)

### Mode transition unit

(c)

Fig. 18. (a) Implementation of the phase control logic. (b) Time diagram of the phase control logic. (c) Flow chart of the mode transient operation.

33

**Chapter 4 **

**E** **XPERIMENTAL ** **R** ^{ESULTS}

^{ESULTS}

**4.1 Chip Micrograph and Design Specification **

The proposed multiphase DC-DC buck converter with the PRCB technique was fabricated in 0.25 μm CMOS process. Dual power stages are embedded in the test chip for verification.

The utilization of off-chip inductors and capacitors are 4.7 μH and 47 μF, respectively. The
chip micrograph is shown in Fig. 19 with an active silicon area of 3.91 mm^{2}. Power stages of
phase 1 and phase 2 are placed closed to bond pads. The single controller is implemented in
the middle of the chip so as to minimize the mismatches issues for both power stages. The key
design specifications are listed in Table III.

### 2300 μm

### 1700 μ m

### Power stage

## Phase 1

### Controller Power stage

## Phase 2

Fig. 19. Chip micrograph.

34

TABLE III: Design specification of the PRCB multiphase voltage buck converter

Technology 0.25m μm CMOS process

Inductor / DCR 4.7 μH/ 100 mΩ (nominal)

Capacitor /ESR 47 μF/ 50 mΩ (nominal)

Switching Frequency 600 kHz

Input Voltage (VIN) 3.3 V – 5 V

Output Voltage range (V_{OUT}) 0.8 V – 3 V (V_{IN} = 3.3 V)
Load Current range (I_{Load}) 0 mA – 2000mA

Current balance improvement (%) Min. 83%

Power conversion efficiency Max. 88 %

Chip size 3.91 mm^{2}

**4.2 Steady-State Operation Results **

*Fig. 20 shows the measured steady-state operation. With the input voltage V**IN* of 3.3 V, the
*nominal output voltage V**OUT* is 2 V. The switching frequency is 600 kHz. The mismatch from
the size of power MOSFETs and the DCR of inductors between each phase results in current
unbalance. The proposed pseudo-ramp operation can generate the proper duty cycles for the
dual-phase operation with a 12 mV output voltage ripple. Besides, the current balance
mechanism achieves the current matching. Fig. 21 shows the measured steady-state operation
with the load current of 500 mA. The pseudo ramp can decide the correct duty cycles so as to
guarantee the output voltage regulation. The current difference between the dual phases is
reduced to 1.9 mA, which can verify the operation of the proposed current balance
mechanism in the PRCB technique.

35

**V**

_{OUT}**I**

**L1**

**I**

**L2**

**12mV**

**Dual phase current matching**

**Steady-state operation**

**I**

_{load}**=0mA**

*Fig. 20. Measured steady-state operation result with the V**IN* of 3.3 V.

**Steady-state operation**

**V**

_{OUT}**V**

_{MODE}**I**

_{L1}**I**

**L2**

**w/i current balance ΔI**

**L**

**=|I**

**L1**

**-I**

**L2**

**|=1.9mA**

**I**

_{Load}**=500mA**

*Fig. 21. Measured steady-state operation result with I** _{Load}* of 500mA.

**4.3 Load Transient Response **

Fig. 22 shows the measured load transient response with the load changes between 0 mA and 550 mA. The voltage drop and overshoot are about 70 mV and 40 mV, respectively. The current balance mechanism is achieved in the period of load transient response as well.

36

**Load transient response**

**V**

**OUT**

**V**

_{MODE}**I**

_{L1 }**&** **I**

_{L2}_{I}

_{I}

**Load**

**=0mA between 550mA**

**Duty=40%**

**70mV**

**40mV**

Fig. 22. Measured load transient response with the current balance mechanism.

The mode transition operation is shown in Fig. 23 The operation mode would be changed from the Mode I to the Mode II during the load transient period so as to enlarge the duty cycles to derive extra energy. In Fig. 23(a), the load current steps from 0 mA to 550mA and the recovery time is long since the mode transition function is closed for comparison. The second experiment result as shown in Fig. 23(b), which shows a shorter recovery time, is taken to examine the load transient improvement with the mode transition function opened.

Thus, as shown in the experimental results, the mode transition operation can help minimize the voltage drop and shorten the transient response time to enhance the load transient operation. The operation mode may be switched back to the Mode I once the load transient period is terminated. However, the DBP mechanism helps define a hysteretic region to avoid the abnormal mode transitions triggered by switching noise. Therefore, the converter will keep operating in the Mode II until the surplus energy is detected at the output.

37

**Load transient response**

**V**

_{OUT}**V**

_{MODE}**I**

_{L1 }**&** **I**

_{L2}**I**

_{Load}**=500mA**

**Duty=40%**

(a)

**Mode switch improves **
**transient response**

**Load transient response**

**V**

**OUT**

**V**

**MODE**

**I**

_{L1 }**&** **I**

_{L2}**I**

_{Load}**=500mA**

**Duty=40%**

**50 **μs

(b)

Fig. 23. Experimental results of load transient response (a) without mode switching strategy and (b) with the mode switching strategy.

**4.4 Line Transient Response **

As described in the foregoing sections, Mode I and Mode II are used for duty cycle smaller and larger than 50%, respectively. To show the relation between the variations of duty cycle, caused by the input voltage, with the mode transition operation, the line transient response of

38

the proposed circuit has been taken. Fig. 24 presents the experimental result of the line
transient response. While input voltage is changing between 2V and 2.5V, for getting the same
*output voltage, the mode transient operation will change the mode signal V**MODE* to cooperate
with the variations of input voltage. For instance, to keep the output voltage of 1.1V, the duty
*cycle is 55% when the input voltage is 2V. At this time, V**MODE* is high for the operation of
*mode II. When the input voltage changes to 2.5V, the duty cycle of 44% makes V** _{MODE}* to be
low for the operation of mode I.

**V**

_{OUT}**I**

_{L1 }**&** **I**

_{L2}**V**

_{MODE}**Line transient response**

**V**

_{IN}**2.5V**
**2V**

Fig. 24. Measured line transient response

**4.5 Current Balance Performance Analysis **

The statistic summaries of the current balance performance of the Mode I and the Mode II are reported in Fig. 25 (a) and (b), respectively. Owing to mismatch, the difference inductor current of two phases increases dramatically as the increment of load current. With the PRCB technique, the current difference is kept smaller than 10 mA over the whole load range. The current balance improvement percentage, which is the decrement percentage of the difference of inductor current, is over 95% at mostly load conditions. However, the worst case is about 83% at very light load since the offset voltage existing at the input of the OTAs in Fig. 16.

39

**Difference of inductor current W/O current balance**
**Difference of inductor current W/I current balance**

**Current balance improvement persentage**

**Difference of inductor current W/O current balance**
**Difference of inductor current W/I current balance**

**Current balance improvement persentage**

Fig. 25. Statistic summary of the current balance mechanism in the proposed PRCB technique. (a) Operating in the Mode I. (b) Operating in the Mode II.

**4.6 Power Conversion Efficiency **

Fig. 26 shows the power conversion efficiency. If the load current is smaller than 30mA, the processor can change the converter to the single-phase operation for high efficiency. The efficiency improvement can be 5%. However, the converter with the dual-phase operation has better efficiency at heavy loads. A peak efficiency of 88 % is derived with the load of 1150 mA. Improved efficiencies are 5% and 10% compared to dual-phase operation without current balance function and single-phase operation, respectively.

**Efficiency (%)**

**Dual-phase operation W/I current **
**balance**

**Dual-phase operation W/O current balance**

**5%** **5%**

**10%**

Fig. 26. Power conversion efficiency.

40

**Chapter 5 **

**C** **ONCLUSION AND ** **F** ^{UTURE } **W** ^{ORK}

^{UTURE }

^{ORK}

**5.1 Conclusion **

The proposed PRCB technique for the voltage-mode multiphase DC-DC buck converter is
presented with single controller to achieve the area-efficient solution. The pseudo-ramp
operation can use only one physical saw-tooth to generate two individual control duties for
the dual-phase operation. In addition, the current balance mechanism also forms a
current-loop, which can dynamically adjust each of duty cycles, to ensure the identical driving
capability in the multiphase structure. Moreover, the mode transition operation is activated
when the point of duty cycle determination is around 50 % so as to prevent the unwilling
mode transitions and help enhance the load transient response. Experimental results
demonstrate the different mode operation with the distinct duty cycles. The current in each
phase is well balanced under both light load and heavy load conditions with an improvement
**of 83 % in current balance. **

41

**5.2 Future Work **

This thesis proposes a pseudo-ramp current balance technique to achieve single controller for multiphase operation in voltage-mode DC-DC buck converter. In this work, the operation of dual-phase is unchangeable under light load and heavy load conditions. To get the best efficiency solution under different load current, the number of the operating phase should be decided by the controller. For instance, while the load current is light, only one phase is used. On the other hand, when the load current is large, more phases should be used to cope with. Furthermore, since the current balance tends to slow down the load transient response for accurate current balance, how to improve the transient response with proper current balance performance is good topic of research.

42

**R** ^{EFERENCES}

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*Circuits and Systems (MWSCAS), pp, 5-8, 2008. *

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