The proposed classification based fault detection and isolation scheme is a general methodology. Modifying the warning signal generation criteria to meet individual machine’s needs, this fault detection scheme is not limited to the ion implanter. The simplicity of the HCT based fault isolation scheme made HCT worthwhile especially when its accuracy can be remedied by the warning signal generation criteria when applying to the ion implanter. Due to the efficient learning capability of HCT and the 0.05 seconds classification time for classifying the recipe of a working wafer, the proposed fault detection and isolation scheme can work on line and real-time.
Chapter 3
Reducing Overkills and Retests in Wafer Testing Process
3.1 Introduction
The wafer fabrication process is a sequence of hundreds of different process steps, which results in an unavoidable variability accumulated from the small variations of each process step. Chips are tested multiple times throughout the design and manufacturing process to ensure the integrity of the chip design and the quality of the manufacturing process.
Semiconductor testing of chips is required at various stages during the fabrication process.
Wafer probing, or testing chips while they are still in semiconductor wafer form is critical to both engineering and production test. A typical wafer is 8 inches or 200 mm in diameter and usually contains 600 to 15,000 chips. Wafer probing establishes a temporary electrical contact between test equipment, such as an Agilent analyzer, and each individual die (or chip) on a wafer to determine whether each chip meets design and performance specifications. The test transmits electrical signals to the chip and analyzes the signals that return. Wafer probing ensures that the chip manufacturer avoids incurring the significant expense of assembling and packaging chips that do not meet specification by identifying flaws early in the manufacturing process.
Although there exist techniques such as the Statistical Process Control (SPC) [22] for monitoring the operations of the wafer probes, the probing errors may still occur in many aspects and cause some good dies being over killed; consequently, the profit is diminished.
Thus, reducing the number ofoverkills is always one of the main objectives in wafer testing process. The key tool to identify or save overkills is retest, which is an additional wafer probing. However, retest is a major factor for decreasing thethroughput. Thus, the overkill and the retest possess inherent conflicting factors, because reducing the former can gain more profit, however, at the expense of increasing the latter, which will degrade the
throughput and increase the cost.
There may be different testing procedures in different chip manufacturers. But, no matter what testing procedures are used, the decision for carrying out the retest should be based on whether the number of good dies and the number of bins2 in a wafer exceed the correspondingthreshold values. Deciding whether to go for a retest is a decision problem. In current wafer testing process, this decision is made based on whether the number of good dies and the number ofbins in a wafer exceed the corresponding threshold values. Manually adaptive adjustments of the threshold values based on engineering judgment, three-sigma limit [23] or a looser six-sigma limit are currently used in some semiconductor manufacturing companies. Consequently, determining these threshold values so as to minimize the overkills under a tolerable level of retests is the main theme of the stochastic optimization problem considered here. What implies is that drawing a fine line for deciding whether to go for a retest to save possible overkills is an important research issue in this stochastic optimization problem of the wafer testing process.
Various techniques such as the weighting objective method, hierarchical optimization method, trade-off method, global criterion method, and method of distance functions and min-max method described in [24] can be used to solve stochastic optimization problems.
Considering the economic situation regarding throughput requirement, it would be most beneficial for us to use the trade-off method [25] to solve the current problem. That is to minimize the overkills subject to a tolerable level of retests provided by the decision maker.
The purpose of this chapter is using a systematic approach to determine these threshold values. We first formulate a stochastic optimization problem on the threshold values. Since the formulated stochastic optimization problem consists of a huge decision-variable space, this makes the problem becomes a hard optimization problem. Thus, to cope with the
2Abin denotes a type of circuitry-defect in a die. There are various types of bins, and a die of any type of bin is considered to be a bad die.
enormous computational complexity, we propose an ordinal optimization theory based two-level algorithm to solve the formulated problem for a good enough solution. This computationally intractable problem is most suitable for the application of our OO theory based two-level algorithm to seek for good enough threshold values.
We organize this chapter in the following manner. In Section 3.2, we formulate a stochastic optimization problem on the simulated wafer testing procedures. In Section 3.3, we will present the proposed OO theory based two-level algorithm and justify its performance using simulations. In Section 3.4, we will present the application of the OO theory based two-level algorithm to reduce overkills and retests in semiconductor wafer testing process. In Section 3.5, we will show the test results of applying the proposed algorithm on two real cases and demonstrate the solution quality by comparing with a vast number of randomly generated solutions and competing methods. Finally, we will make a conclusion in Section 3.6.