This study has demonstrated a high performance gate-first epitaxial Ge n-MOSFET on Si. Using high-κ LaAlO3, this study achieved good device performance of a record small SS and high mobility at high Eeff among reported gate-first Ge n-MOSFETs, as well as the very low IOFF for low power application and a small 1.6 nm EOT. The self-aligned, gate-first TaN/LaAlO3/Ge/Si n-MOSFETs had the advantage of simple processing and compatibility with current VLSI lines.
Process
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
-2.0 -1.5 -1.0 -0.5 0.0
TaN/LaAlO3/Ge/Si n-MOS capacitors after550oC RTA.
(a)
(b)
(c)
Fig. 2.3 Cross-sectional TEM of (a) TaN/HfAlO/Ge/Si capacitor, (b) control TaN
HfAlO
Ge
5nm Si
4.0 nm
TaN
Si HfAlO
5nm
4.0 nm TaN
Si HfAlO
5nm
4.0 nm
TaN
5nm
LaAlO3
Ge Si
4.0nm
0 1 2 3
0.0 0.1 0.2 0.3 0.4 0.5 0
100 200 300 400
500 This work
Reference Reference Reference Reference
eff(cm2 /V-sec)
Eeff (MV/cm)
Fig. 2.5 Electron mobility vs. effective electric field of TaN/LaAlO3/Ge/Si n-MOSFET and other published data for comparison.
10
010
110
210
310
410
-110
010
110
210
3nMOSFET, V
g=V
t+1.2V and 850C TaN/LaAlO3on Ge/Si
V
t
Time (sec)
50 mV
Fig. 2.6 Vt shift of TaN/LaAlO3/Ge/Si n-MOSFET stressed at 85oC for 1 hour.
Chapter 3
Interfacial Layer Dependence on Device Property of High-TiLaO Ge/Si N-Type
Metal-Oxide-Semiconductor Capacitors at Small Equivalent-Oxide Thickness
3.1. Introduction
Germanium (Ge) has attracted much attention for Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) [3-1]-[3-14] application due to both higher electron and hole mobilities than Silicon (Si). However, the difficult challenges are
the high leakage current of small energy bandgap (EG) Ge and the poor interface property with high dielectric-constant () material. To lower the leakage current, we
pioneered the defect free Ge-on-insulator (GOI or GeOI) [3-1] structure, and the leakage current decreases with decreasing the Ge body thickness [3-5]. Nevertheless, the degraded interface property is still a tough challenge especially for the Ge n-type
MOSFET (n-MOSFET) [3-6]-[3-12] at a small equivalent oxide thickness (EOT). The interface property is highly dependent on high- dielectrics, where Al2O3 [3-1] and
La2O3 [3-8]-[3-11]show lower interface trap density than HfO2. This is related to the different Metal-Oxygen-Ge and defect formations [3-11] after a rapid-thermal anneal (RTA). To improve the interface, several passivation methods have been proposed
such as plasma nitridation,[3-4]-[3-8] NH3 treatment, SiH4 annealing and interfacial GeO2 layer [3-8]-[3-10], [3-12]-[3-14] at larger EOT, but small EOT less than 1 nm is needed for 32 nm node and beyond. In this paper, we have applied the ultra-thin GeO2
and SiO2 interfacial layers [3-15] into high- TiLaO [3-16] epitaxial-Ge/Si n-type MOS (n-MOS) capacitors, where the ultra-thin body Ge of 5 nm is directly grown on Si to reach low leakage current. The TiLaO gate dielectric has the merits of unique negative flat-band voltage (Vfb) from La2O3 [3-17] and the much higher by adding TiO2 [3-16]. Such negative Vfb is needed for low threshold voltage (Vt) MOSFET. The control TaN/TiLaO/Ge/Si n-MOS capacitor without the ultra-thin GeO2 or SiO2
interfacial layer showed poor EOT and large Vfb degradation after a 550oC RTA, which is required to activate ion-implanted source-drain in the MOSFET. Such degradations are related to interface reaction and oxygen vacancy formation
[3-18]-[3-19] that are much improved by inserting the ultra-thin GeO2 or SiO2 [3-15]
interfacial layer. However, the high-TiLaO Ge/Si n-MOS capacitor with interfacial
GeO2 showed much poorer capacitance-voltage (C-V) hysteresis than that using SiO2
at a smaller EOT less than 1 nm. This is due to the Ge out-diffusion and intermixing of high-TiLaO/GeO2 as observed by cross-sectional Transmission Electron
Microscopy (TEM) and Secondary Ion Mass Spectroscopy (SIMS).
3.2. Experimental procedure
After RCA cleaning, a 200 nm undoped Si buffer, 5 nm Ge and 1.5 nm Si
capping layer were epitaxial grown on 6-in p-type Si substrate (10 ohm-cm) by ultra-high-vacuum chemical-vapor-deposition (HUVCVD). After removing the native oxide of Si-capping layer, various thick GeO2 or SiO2 and 5 nm high- TiLaO [3-16]
were deposited by physical vapor deposition (PVD) and followed by post-deposition annealing (PDA) at 400oC in oxygenambient to improve gate dielectric quality. Here the ultra-thin Si capping is used to prevent Ge oxidation and process loss, where no interfacial Si was found by cross-sectional TEM after device process. Then a 50 nm TaN was deposited and patterned to form the metal gate. The formed gate stack was applied by a 550oC RTA that is needed for Ge n-MOSFET fabrication. Finally, Aluminum (Al) was deposited on wafer backside to form the MOS capacitors. For comparison, control device without GeO2 or SiO2 interfacial layer was also made. The fabricated gate stack was examined by SIMS, TEM, X-ray Photoelectron Spectroscopy (XPS) and C-V measurements to investigate the physical, chemical bonding and electrical properties, respectively.
3.3. Results and discussion
Figure 3.1 shows the measured C-V characteristics of high- TiLaO Ge/Si
n-MOS capacitors with or without the interfacial GeO2 or SiO2 layer. For device
without the inserted GeO2 or SiO2 layer, both the capacitance density and Vfb were severely degraded. Such V
fb roll-off at high temperature was previously reported due to the interface reaction between high- and semiconductor [3-19]. In contrast, the
capacitor with GeO2 or SiO2 layer shows much improved V
fb roll-off even after a 550oC RTA. Besides, the needed negative Vfb of -0.48 V is obtained and important for low Vt Ge n-MOSFET. However, the device with GeO2 interfacial layer shows poorer C-V hysteresis of 93 mV at 1.1 nm EOT than the much improved 19 mV hysteresis at
smaller 0.81 nm EOT for device using SiO2 interfacial layer, by taking account of quantum-mechanical effect with parameters of Ge [3-7]. The C–V hysteresis and negative Vfb value are among the best reported data for Ge n-MOS capacitors at the smallest EOT and after a 550oC RTA [3-1]-[3-14],to our best knowledge.
We have used TEM to study the better electrical performance for device using interfacial SiO2 layer. Figures 3.2(a) and 3.2(b) show the TEM images of TaN/TiLaO/GeO2/Ge/Si n-MOS structure before and after a 550oC RTA. Sharp GeO2 interfacial layer of 0.76 nm thickness was found for as-deposited sample but becomes
blurred after the 550oC RTA. The high- layer is also thicker after the 550oC RTA, where intermixing of high- TiLaO and GeO2 is observed. The thicker high- layer
explains the lower capacitance density after a 550oC RTA. In strong contrast, sharp SiO2 interface shown in Fig. 3.2(c) is still preserved even after the 550oC RTA.
We have further used SIMS to study the large difference for devices with different interfacial GeO2 and SiO2. Figures 3.3(a) and 3.3(b) show the measured SIMS profiles of TaN/TiLaO on Ge/Si structure with interfacial GeO2 and SiO2 layers,
respectively. Severe Ge out-diffusion was found for device structure with interfacial GeO2 layer after a 550oC RTA, while much improved Ge out-diffusion was achieved using ultra-thin SiO2 interfacial layer even at a smaller 0.81 nm EOT.
The degraded interface property with ultra-thin interfacial GeO2 was also examined by XPS. Figure 3.4 shows the Ge 2p3 XPS spectra of TiLaO/GeO2/Ge/Si n-MOS structure before and after the 550oC RTA. The as-deposited sample shows a strong Ge peak at 1217.4 eV, and a small higher energy side peak is attributed to Ge-O bonds of GeO2 [3-20]. However, this Ge-O peak becomes much weaker for the sample after the 550oC RTA. This is consistent with the largely thinned GeO2 and intermixed TiLaO/GeO2 interface found from cross-sectional TEM and the large Ge out-diffusion measured by SIMS. The thinner interfacial GeO2 after the high temperature 550oC RTA may be related to the measured reaction at 758~589K [3-21]:
GeO2(s) + Ge(s) 2 GeO(g) (2)
In contrast, the interface reaction between ultra-thin SiO2 layer and Ge is unfavorable due to the much higher bond enthalpy of SiO2 (800 kJ/mol) than GeO2 (659 kJ/mol) [3-22].
3.4. Conclusion
In conclusion, we have studied the high- TiLaO on Ge/Si MOS structure with
GeO2 and SiO2 interfacial layers. Low EOT of 0.81 nm, small C-V hysteresis of 19 mV and needed negative V are obtained using ultra-thin SiO interfacial layer. The
device with ultra-thin interfacial GeO2 shows inferior device performance of larger EOT and poor C-V hysteresis, which is due to the severe Ge out-diffusion through GeO2 from SIMS profile, thicker gate dielectric from TEM observation and thinned interfacial GeO2 after a 550oC RTA from TEM and XPS analysis.
-3 -2 -1 0 1 2 0.0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
C (
F /c m
2)
Voltage (V)
TiLaO/SiO
2 on Ge/Si TiLaO/GeO
2 on Ge/Si TiLaO on Ge/Si Solid: 450oC RTA; Open: 550oC RTA
100KHz Frequency
Fig. 3.1. C-V characteristics of TaN/TiLaO Ge/Si n-MOS capacitors with or without the inserted GeO2 and SiO2 interfacial layer and after 450 or 550oC RTA.
The device size is 100-mx100-m.
(a)
(b)
(c)
Fig.3.2. Cross-sectional TEM images of TaN/TiLaO/GeO2/Ge/Si n-MOS capacitors (a) before and (b) after 550oC RTA. (c) TaN/TiLaO/SiO2/Ge/Si n-MOS capacitors after 550oC RTA.
0 1000 2000 3000 4000
Fig. 3.3. SIMS profile of TaN/TiLaO Ge/Si n-MOS structure with inserted (a) GeO2 and (b) SiO2 interfacial layer before and after 550oC RTA.
12107 1215 1220 1225 1230 1235 8
9 10 11 12 13 14
Ge-Ge
as-deposited 550oC RTA
Intensity (C/S)
Binding Energy x103
Ge-O
TaN/TiLaO/GeO
2 on Ge/Si
Fig. 3.4. The Ge 2p3 XPS spectra of TiLaO/GeO2/Ge/Si structure before and after 550oC RTA.
Chapter 4
High Performance of Ge n-MOSFETs Using SiO2 Interfacial Layer and TiLaO Gate Dielectric
4.1. Introduction
The Ge channel MOSFETs [4-1]-[4-11] have attracted much attention due to higher bulk electron and hole mobilities than Si counterparts. Nevertheless, the technical challenges for Ge MOSFETs are severe, which include the integration of defect-free Ge on Si substrate, the large leakage current of small energy bandgap (EG) Ge and the poor electron mobility at high effective electric field. The integration of defect-free Ge on Si was demonstrated by us using wafer-bonded Ge-on-insulator (GOI or GeOI) technology [4-1]. The leakage current of small EG Ge MOSFET is also lowered by thinning Ge body thickness in GOI [4-5]. However, the electron mobility degradation at high effective field is still a severe issue, which is especially important for MOSFET at small equivalent-oxide thickness (EOT). In order to improve the mobility, many interface passivation methods have been proposed such as NH3 surface treatment, SiH4 annealing [4-4], Si capping layer [4-6], [4-9] and GeO2 interfacial layer [4-7]-[4-8]. Unfortunately, these methods still got relative low mobility at high effective field. The SiOx interfacial layer has been used for Ge p-MOSFET [4-10], but the small EOT, low off-state leakage (I ) and good high
field mobility are still the major challenges for Ge n-MOSFET. In this paper, we report high mobility at high effective field for Ge n-MOSFETs with small capacitance-equivalent-thickness (CET), which was achieved by using higher TiLaO dielectric [4-12]-[4-13] and SiO2 interfacial layer. In contrast, much degraded CET and unwanted flat-band voltage (Vfb) shift were measured for control device without the SiO2 interfacial layer.
4.2. Experimental procedure
After standard clean, an undoped 200 nm Si buffer, undoped 5 nm Ge and undoped 1.5 nm Si capping layer were grown on p-type (100) Si wafers (5×1015 cm-3 doping) by ultra-high-vacuum chemical-vapor-deposition (HUVCVD) at 500oC and 5×10-4 torr. An ultra-thin 0.8 nm SiO2 was deposited by Physical Vapor Deposition (PVD) using Electron-Beam Evaporation at the room temperature and 2×10-6 torr pressure [3-14], where the native oxide of Si-capping layer was removed using dilute HF solution. Here the Si-capping is to prevent the thin Ge loss during process, since Ge can be oxidized by water and air similar to Si case and GeO2 is dissolvable by water. No Si-capping layer was found by cross-section TEM after process. A 5 nm thick TixLa1-xO (x~0.67) [3-12] with of 45 was deposited and followed by a 400oC post-deposition anneal (PDA) in an oxygen ambient for 5 min. Then a 200 nm TaN was deposited by PVD and patterned to form the metal gate. For comparison, the capacitors without SiO2 interfacial layer were also fabricated. After that, self-aligned
25 KeV As+ion implantation was applied at a 5×10
15
cm
-2
dosage and 550oC RTA.
From the X-Ray Diffraction (XRD) study, the TiLaO is amorphous after 550oC RTA.
Finally, non-alloyed Al contact metal was added. The fabricated devices were characterized by capacitance-voltage (C-V) and current-voltage (J-V) measurements.
4.3. Results and Discussion
In Fig. 4.1 we showed the C-V characteristics of TaN/TiLaO on Si-capped Ge/Si capacitors after 450~550oC RTA. These devices showed severe degradations of capacitance density, Vfb shift, and hysteresis after a 550oC RTA, which was related to interfacial layer formation as found by TEM. However, this temperature is required to activate the ion implanted dopants at source-drain of Ge MOSFET.
To address the interface reaction, we added an ultra-thin SiO2 interfacial layer between high- and Ge. Figures 4.2(a) and 4.2(b) showed the C-V and J-V
characteristics of the TaN/TiLaO/SiO2 on Ge/Si n-MOS devices. Much smaller unwanted Vfb shift and less interface states generation are reached than the devices without SiO2 interfacial layer shown in Fig. 4.1. The good high- and interface quality is also evident from the small C-V hysteresis of only 19 mV from -3 to 1 V sweep. Such large difference is due to the dense and strong bonding SiO2 to prevent the Ge out diffusion during the process, from SIMS measurements. Besides, a small 1.1 nm CET is obtained after 550oC RTA with 4 orders of magnitude lower leakage
Figures 4.3(a) and 4.3(b) show the respective Id-Vd and Id-Vg characteristics. Good transistor characteristics of relatively high drive current, small sub-threshold swing (SS) of 126 mV/dec and a record low IOFF leakage of 3.5×10-10 A/m [4-6]-[4-8] were measured simultaneously. This is due to the ultra-thin body (UTB) of conductive Ge channel on Si substrate that is well predicted by UTB GOI MOSFETs [4-5]. Such low leakage current is mandatory for future generation low power green transistor.
Figure 4 shows the electron mobility versus effective electric field, where the data was directly derived from measured Id-Vg curves [4-15]. Good high field mobility at 0.5 MV/cm is 201 cm2/V-s [4-6]-[4-8] at a small 1.1 nm CET. The good high field mobility is consistent with the needed negative Vfb, small C-V hysteresis and SS; here the SS of 126 mV/dec is one of the best reported data for Ge n-MOSFET in literature [4-1]-[4-11]. The good high field mobility is vital for MOSFET at a small EOT, where a still high 0.65 V drain voltage is needed even for 11 nm node technology according to ITRS.
4.4. Conclusions
We have demonstrated high performance epitaxial Ge n-MOSFET on Si using higher TiLaO and SiO2 interfacial layer.Good device performance is reached in terms of small CET, record low IOFF and the highest mobility at high effective electric field. Besides, this self-aligned and gate-first transistor has the advantages of simple processing and compatibility with current VLSI lines.
-2 -1 0 1 2 0.0
0.5 1.0 1.5 2.0 2.5 3.0
450oC RTA From -2V to 2V 450oC RTA From 2V to 2V 500oC RTA From -2V to 2V 500oC RTA From 2V to 2V
C
(
F/cm2)
Voltage (V)
TiLaO on Si-capped Ge/Si
100kHz frequency
550oC RTA From -2V to 2V 550oC RTA From 2V to 2V
Fig. 4.1. C-V and of the TaN/TiLaO on Si-Capped Ge/Si n-MOS capacitors after 450~550oC RTA.
-3 -2 -1 0 1 n-MOSFETs 450~550oC RTA. The inserted figure in (b) is the J-CET plot at 1 V above Vfb.
0.0 0.5 1.0 1.5 2.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0
100 200 300 400 500 600
700 J. H. Park et al
C. C. Yeo et al T. Takahashi et al Si Universal This Work
eff(cm2 /V-sec)
Eeff (MV/cm)
Fig.4. 4. The electron mobility as a function of effective electric field for the TaN/TiLaO/SiO2 on Ge/Si n-MOSFETs.
Chapter 5
High Field Mobility Metal-Gate/high-κ Ge
n-MOSFETs with Small Equivalent-Oxide-Thickness
5.1. Introduction
Recently, the high performance Metal-Oxide-Semiconductor field effect transistors (MOSFETs) with using high- materials such as La2O3 [5-2], Al2O3 [5-3],
[5-19], HfO2 [5-5] and mixed metal oxides have been proposed to replace the conventional SiO2 MOSFETs for EOT (equivalent oxide thickness) scaling. However, the scalable performance enhancement depends on channel length scaling, gate dielectric scaling and optimized strain engineering like SiGe source-drain and compressive contact etch stop layer (CESL). Ge channel is expected to additionally boost the mobility at thin EOT. Thus, much attention has been focused on Ge channel complementary metal oxide semiconductor field effect transistors (CMOSFETs) [5-1]-[5-22], which is due to 2-4 times higher electron and hole mobility than those of Si devices. Besides, the densities of states are ~ 50 times larger than III-V InGaAs substrate for higher drive current. However, the challenging issues of the small-bandgap-induced high leakage current, sensitive to process temperature and poor interface quality due to Ge out-diffusion are the major challenges.
To address these issues, the defect-free Ge-on-insulator (GOI or GeOI) [5-3] and
thin body Ge-on-Si [5-17], [5-18] are proposed. Nevertheless, the low electron mobility at high effective electronic field (Eeff) and poor equivalent-oxide thickness
EOT scaling are still the unsettled issues. The lower peak mobility could be attributed to the Coulomb scattering in the high- dielectric that was also found in high-κ/Si
[5-27], [5-29]. Such challenges become worst at gate-first process, where the high thermal budget degrades the mobility originated from interface reaction and Ge out-diffusion. Although several surface passivation approaches such as NH3 surface treatment and Si-capping on Ge channel [5-8], [5-10], [5-12], [5-21], [5-22] were proposed, high field mobility at small EOT still needs to be developed.
In this study, we reported the high-field mobility of Ge n-MOSFETs using TaN/La2O3/SiO2 gate stack. The La2O3 dielectric [5-2], [5-23], [5-24] with high-κ value and negative flat band voltage (Vfb) are important for n-MOSFET. The metal-gate/device show high field mobility of 258 cm2/Vs at 0.75 MV/cm with a
small 1.9-nm EOT. The results are ascribed to the SiO2 barrier layer and low thermal budget process to suppress the Ge out-diffusion into high-dielectric.
5.2. Experimental Procedure
We used a 2-in p-type Ge (100) wafers with a doping concentration of 51014
cm-3 in these experiments. After standard clean, 500 nm isolation oxides were deposited by Plasma-enhanced chemical vapor deposition (PECVD). Then active
areas were defined by lithography and wet etching. After that As+ was implanted at source and drain region at 25 KeV and a dosage of 51015 cm-2 and followed by a
550oC rapid thermal annealing (RTA) for dopant activation. A 0.8 nm thick SiO2 and 6 nm La2O3 were deposited by dual E-Gun evaporation system at a pressure of 2 x 10-6 torr and followed by a 400oC post-deposition anneal (PDA) in an oxygen ambient for 5 min to densify the gate dielectric quality. A 150-nm-thick TaN metal was deposited and patterned to form the gate electrode by a sputter system at a pressure of 9 x 10-7 torr. Finally, the Ge n-MOSFET was formed by adding 300-nm-thick Al metal contacts to source-drain by thermal evaporation coater and annealed at 400OC for 25 min in an N2 ambient. Figures 5.1 (a) and (b) show the schematic image and process flow. The fabricated devices were characterized by C-V and I-V measurements by HP4284A precision LCR meter and HP4156C semiconductor parameter analyzer, respectively. The devices were also analyzed by SIMS (Secondary ion mass spectroscopy), and cross-sectional transmission electron microscopy (TEM).
5.3. Result and Discussion
Figures 5.2(a) and 5.2(b) show the C-V and J-V characteristics of TaN/La2O3/SiO2/Ge devices. The increasing PDA temperature from 350 to 450oC improves the gate leakage current for several times, with only slight Vfb shift. The
slight EOT increase with increasing PDA temperature is related to interfacial layer formation. At 400oC PDA temperature, a capacitance density of 1.54 F/cm2 was
measured that gave an EOT of 1.9 nm from quantum-mechanical C-V (QM-CV) simulation using Ge material parameters. Besides, a low leakage current of 8105
A/cm2 was reached at 1 V above Vfb. The C-V curves spreading with different PDA were mainly attributed to interface reaction. Compared to 350oC and 450oC, the capacitor with an optimized 400oC PDA shows a corresponding thinner EOT of 1.9nm and lowest leakage current at 1 V above Vfb shift. The large leakage and small capacitance density caused by serious interface oxidation for over high-temperature 450oC explain the importance of thermal budget control during dielectric activation.
The combined effect of thicker interfacial layer and poor interface state may lead to the performance degradation on capacitance density and leakage current. Thus, an appropriate PDA temperature not only can effectively activate the defect-rich dielectric but also suppress the serious interface oxidation, especially for Ge substrate.
We further analyzed the gate stack on Ge substrate by SIMS and TEM. Figures 5.3 (a) and (b) show the SIMS depth profile and cross-sectional TEM image, respectively. No apparent Ge out-diffusion was found by SIMS that is important to reach mobility and low gate leakage for Ge MOSFET [5-22]. This is further confirmed by the sharp interface between La2O3/SiO2 and Ge as observed by
cross-sectional TEM. The sharp SiO2-like layer formation may result from intermixing effect near Si interface which can reduce the Ge out-diffusion into high-
cross-sectional TEM. The sharp SiO2-like layer formation may result from intermixing effect near Si interface which can reduce the Ge out-diffusion into high-