Results and Discussion

Fig. 2.1 (a) shows C-V characteristics of TaN/HfAlO/Ge/Si and control TaN/HfAlO/Si n-MOS capacitors after different RTA temperatures. Compared with control device on Si, the HfAlO dielectric on Ge had a lower capacitance density and lower unwanted flat-band voltage (V_fb) shift of ~0.7 V even at a low temperature 450^oC RTA. Increasing the RTA temperature to 550^oC led to severe C-V distortion by high density interface states and was accompanied by a greater V_fb shift. However, such annealing temperature was required for doping activation at the ion-implanted source-drain. The severe V_fb shift and interface trap generation at only 550^oC were related to the strong interface reaction shown in the cross-sectional TEM of following sections. Fig. 2.1 (b) showed the TaN/LaAlO₃/Ge/Si n-MOS capacitors after different

RTA temperatures. The negative Vfb is the unique characteristics of La2O3-containing high-κ gate dielectric [2-31]-[2-32]. Although similar Vfb shift and slightly lowered capacitance density were detected in TaN/LaAlO3/Ge/Si n-MOS capacitors, the C-V distortion and Vfb value were significantly better than TaN/HfAlO/Ge/Si device. An EOT of 1.6 nm was obtained from Quantum-Mechanical (QM) C-V simulation with Ge parameters [2-22].

Fig. 2.2 shows the measured gate dielectric leakage current of TaN/LaAlO3/Ge/Si and TaN/HfAlO/Ge/Si capacitors. A leakage current of 610^-4 A/cm² at -1 V was reached for TaN/LaAlO3/Ge/Si capacitor with a small 1.6 nm EOT that was 67 times lower than that of TaN/HfAlO/Ge/Si capacitor after the same 550^oC RTA with a larger 2.6 nm EOT. The poor current leakage with HfAlO gate dielectric was related to the much-degraded interface property by large EOT and V_fb shift as shown in Fig. 2.1(a). Although detailed mechanism is still under investigation, such degradation may have been related to the interface reaction of GeO₂ with HfO₂ to form volatile GeO [2-23]-[2-24] and charged oxygen-deficient GeO_x. This in turn generated interface charge [2-31], increased the Ge diffusion into HfO₂ and roughened the interface [2-23]-[2-24]. The poor interface and gate dielectric quality also degraded the leakage current of the gate capacitor. Fig. 2.2(b) shows the leakage current as a function of EOT, for TaN/LaAlO₃/Ge/Si capacitors with smaller EOT

down to 1.05 nm. The extrapolated leakage current at 1.0 nm EOT was >3 orders of magnitude lower than that of SiO2. This permitted the addition of interfacial GeO2 or SiO(N) [33] to reduce the remote phonon scattering from high-κ gate dielectric, similar to Intel’s device [2-34].

To grasp the large differences between capacitor using LaAlO3 and HfAlO gate dielectrics on Ge/Si, these high-κ capacitors were examined by cross-sectional TEM.

Figs. 2.3(a), 2.3(b) and 2.3(c) show cross-sectional TEM images of TaN/HfAlO/Ge/Si, control TaN/HfAlO/Si and TaN/LaAlO3/Ge/Si capacitors after the same 550^oC RTA, respectively. The HfAlO on Ge/Si had a thicker high-κ layer than HfAlO on Si, deposited side-by-side after the 550^oC RTA, suggesting a strong interface reaction or Ge out-diffusion between HfAlO and Ge/Si [2-23]-[2-24]. The thicker interfacial layer formed on Ge/Si than Si was not due to the oxygen diffusion since the same HfAlO gate dielectric was used and deposited side-by-side on Ge/Si and Si. The Ge out-diffusion [2-21] may have been due to the lower melting point of Ge than Si that, in turn, scaled with cohesive energy (372 kJ/mol for Ge and 446 kJ/mol for Si) to separate a single atom from the crystal lattice. However, the LaAlO₃ on Ge/Si showed very close high-κ thickness with the control HfAlO on Si, although a very thin interfacial layer was formed. This was consistent with the much smaller EOT and higher capacitance density than HfAlO on Ge. Since the only difference between

these two high-κ dielectrics was the addition of La2O3 or HfO2, this suggested a stronger reaction between HfO2 and Ge to enhance interface reaction or Ge out-diffusion. Although no data of Hf-Ge or germanide formation could be available in the literature, the bond enthalpy to group-IV Carbon was significantly higher for

and I_d-V_g characteristics, respectively. Small sub-threshold swing (SS) of 108 mV/dec and very low IOFF of 710^-10 A/μm were measured. This small IOFF leakage and good SS were vital for small E_G and high mobility new channel MOSFET used for low power Green Transistor application. Further improving I_ON/I_OFF may be reached by chemical interface passivation using H, S, or Se. It is noticed that the SS was one of the best-reported data for gate-first Ge n-MOSFET [2-1]-[2-24] that was even better than the TaN/TiLaO/SiO₂/Ge/Si n-MOSFET using SiO₂ interfacial layer at a smaller EOT of 0.81 nm. Here the SS is expressed as [2-32]:

where Cdep was the depletion capacitance density, Cit was the capacitance density from charged interface traps and Ci was the gate capacitance density. The improved SS at larger EOT was an indication of improved interface properties of LaAlO3 gate dielectric on Ge/Si compared with previous TiLaO/SiO2 with an ultra-thin SiO2

interfacial layer on Ge/Si [2-22].

Fig. 2.5 shows mobility as a function of Eeff. The mobility was calculated directly from the Id-Vg curves [35]. For comparison, the mobility data from related literatures were also plotted [2-10], [2-13]-[2-14], [2-22]. The lower peak mobility could be attributed to the remote phonon scattering in the high-κ dielectric that was also found in high-κ/Si MOSFET. Therefore, an ultra-thin SiO(N) [2-33] or GeO₂ [2-14]-[2-17], [2-19]-[2-20] interfacial layer was needed to further improve the peak mobility and I_ON/I_OFF. Although higher peak mobility values were published [2-10], [2-13]-[2-14], the mobility decreased rapidly with an increase in E_eff due to the interface scattering. However, the MOSFET was destined to operate at high E_eff due to the small 1 nm EOT used for 45~32 nm nodes [2-34]. In sharp contrast, the Ge n-MOSFET using LaAlO₃ showed the superior high field mobility of 218 cm²/Vs at 0.5 MV/cm that was one of the best reported high-field mobility data for gate-first Ge n-MOSFETs [2-1]-[2-24].

Fig. 2.6 shows the reliability of TaN/LaAlO₃/Ge/Si n-MOSFETs under

bias-temperature instability (BTI) testing. A small threshold-voltage shift (Vt) of 31

mV was measured at a 1.2 V gate overdrive (Vg-Vt) and 85^oC for 1 hr. Table 1 summarizes and compares the important device parameters of metal-gate/high-Ge

n-MOSFETs [2-10], [2-13]-[2-14], [2-17]-[2-20], [2-22]. The TaN/LaAlO3/Ge/Si n-MOSFET had superior high-field mobility of 218 cm²/Vs at 0.5 MV/cm, record low SS of 108 mV/dec, small 1.6 nm EOT, very low IOFF of 710^-10 A/μm, simple

gate-first process and useful for 12-in integration.