In this thesis, we already quantity has examined varied stress condition. We clearly know, the Tr /Tf dependence is well explained.
From C-V measurement, we can get the same degradation relation of tr and tf as I-V measurement. The C-V measurement of N-type is C-V curve slight out and P-type is capacitance increase in the depletion region. For P-type we find the linearity relationship between ΔLμ and ΔLc , therefore, the results of C-V measurement and I-V are constant. In addition, the degradation mechanism of N-type is similar hot carrier and P-type is channel length shortening.
The degradation of P-channel TFT devices is due to a different mechanism than that of the N-channel TFT devices. For N-channel, charge damage occurs at these voltages through a three-step mechanism that causes an energy enhancement resulting from a feedback mechanism, namely impact-ionization feedback through the drain-bulk junction. The explanation of the impact-ionization feedback effect is as follow:
Oxide
Drain Source
Substrate Buffer oxide
Poly-Si
□ Channel hot carrier
★impact ionization event
Fig. 5-1 Schematic illustration of the impact-ionization.
Channel electrons are injected into the drain where they gain enough energy to impact ionize, forming low-energy electron-hole pairs. The secondary electrons formed in this region leave through the drain, but the holes are then accelerated back into region C where they can once more gain enough energy to impact ionize forming more electron-hole pairs. Such circulation results in producing a lot of defect states and oxide charges, shown in Fig. 5-2.
High-field region
impact ionization Enough energy
Electron hole
Creating many defect states and
oxide charges
● Electron created by impact ionization
○ Hole created by impact ionization
Fig. 5-2 Schematic illustration of the mechanism causing the impact-ionization feedback effect.
For P-type devices, channel electrons are injected into the drain where they gain enough energy to impact ionize, forming low-energy electron-hole pairs. The secondary electrons trapped at interface between poly-Si and oxide. Besides, the extra hole current flows to drain, shown in Fig. 5-3.
● Hole created by impact ionization
○ Electron created by impact ionization
High-field region
impact ionization Enough energy
Electron hole
Trapped at interface between
poly-Si and oxide
Extra hole current flows to drain
Fig. 5-3 Schematic illustration of the mechanism causing the HEIP.
It was reported that the activation energy of electron to inject into the gate oxide is about 3.2 eV and that of hole is about 4.3 eV [29], which means that the probability of electron trapping is larger than hole trapping. But the trapped holes in gate oxide lead to the degradation of P-type TFT can be observed from our measurement of C-V curve’s shifting after stress. On the other hand, the hot holes are so few that the states creation in the P-type TFT is much less than that in the N-type TFT. Therefore, the electrical degradation of the P-type TFTs is very different from that of N-type TFTs.
The mobility degradation versus the index Π under different AC stress conditions for N-type and P-type are linearity. So, our measurement results are strongly supported by simulation.
The improvement of the reliability of poly-Si TFTs are the most important requirements in the realization of high-performance displays. Therefore, reliability testing is increasingly required. Besides the degradation mechanism under AC stress operation should be understood
in detail. In this thesis, the mobility degradation and the degradation behaviors of LTPS TFT’s C-V characteristics are investigated. In addition, most degradation mechanisms are discussed by I-V transfer characteristics rather than C-V transfer characteristics. Two kinds of degradation behaviors’ mechanism are discussed by I-V transfer characteristics and C-V transfer characteristics means of not only measurement result but also the simulation tool. We have successfully detected the universal linearity gives the index a potential modeling for reliability simulation and lifetime prediction of N-type and P-type poly-Si TFT circuitry.
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