We have demonstrated a top gate Poly-Si TFT with the light-shielding structure first. The proposed Full-Metal-Shielding TFT is free of photo leakage current under illumination for high image quality AMLCD application.
And then, we proposed the TFTs with split metal shielding layer to indicate the split location is the key factor to induce photo leakage current. So we can suggest that the critical region to induce photo leakage current of poly-Si TFT under illumination. Besides, it dependent of increasing drain bias. In the experiment, the critical region is very short and located in drain junction with low drain bias. The enhancement of the drain bias will extend the critical region. The photo leakage current will increase when the light beams go through the split that has a little distance to drain under a high drain bias.
In addition, the threshold voltage shift of the Full-Metal-shielding TFTs and Split -Metal-shielding TFTs rise with the increasing drain bias in dark state, which is explained by the coupling effect. In order to overcome this issue and investigate the generation mechanism of IPLC, Poly-Si TFT with the partial shielding metal located in junction and channel region is fabricated. The VTH of Poly-Si TFT with partial metal shielding layer is independent of increasing drain bias. Furthermore, the Drain-shielding TFT exhibits impressively low IPLC. But the shielding effect of the Source-shielding TFT and Channel-shielding TFT are rather poor. The IPLC of Drain-shielding TFT, Channel-shielding TFT and Source-shielding TFT are 4.1, 19.2 and 24.5 pA as brightness of back-light is 5610 nits. From the comparison of IPLC of Drain-shielding TFT, Source-shielding TFT and Channel-shielding TFT, the band diagram of Poly-Si TFT under illumination is proposed. Unfortunately, the shielding effect of Drain-shielding TFT would be suppressed as the high drain voltage. It is due to back channel effect.
We also study the electrical characteristic of poly-Si TFT with patterned metal shielding layer under illumination. The IPLCand S.S properties of Poly-Si are discussed in detail by two approaches. The Forward TFT exhibits the significantly high IPLC and the slightly modified S.S under illumination. By contrast, the IPLC in Reverse TFT is lower than that in Forward TFT at the same drain bias. The S.S under illumination is almost unchanged in reverse mode at low drain bias. However, a remarkable degradation in S.S is observed in Reverse TFT with high drain bias operation. The increased ratio of sub-threshold swing for this case is 64%.
Based on the results and proposed model, the causes of IPLC and degraded S.S in Poly-Si TFTs under illumination are demonstrated in this work.
Finally, we study the degradation mechanism of DC stress and AC stress under illumination. We propose a model of DC stress under illumination first. Since the light emitted from back-light is mainly absorbed at the interface between the poly-Si layer and the buffer layer, plenty of electron-hole pairs are generated in the bottom of poly-Si film. As the electron-hole pairs are generated, the electric field in the junction of channel and drain decrease. So the degree of the degradation of light stress is smaller than dark stress.
In AC stress experiment, we employed two kind of poly-Si TFTs to clarify the photo effect of AC stress. One is convention TFT, and the other is a new structure TFT with split metal shielding layer. The result of AC stress experiment with convention TFT is that the degradation is quite obvious when stress under illumination, owing to the high current density.
Although it is known that the impact ionization is dependent with current density and electric field, in this experiment, we suggest that the key factor is current density.
There is a different AC stress result when experiment with split metal shielding TFT.
The degradation is quite obvious when stress under darkness. Most of light beams are blocked to metal shielding layer, so the current density just raises a little. But the light beams go through the split to drain junction procured junction electric field decrease. In the experiment,
we suggest that the key factor is the electric field of drain junction, not current density. So the degradation is quite obvious when stress under darkness.
Reference
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Figures Convention TFT V
D=0.1V
Gate Voltage (V)
-15 -10 -5 0 5 10 15
Drain Current (A)
10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5
Dark 2160nits
I
PLCSS degraded
Fig.1.1.1 The ID-VG transfer curves of standard Poly-Si TFT.
Fig.2.1.1 The average grain size of polycrystalline silicon was found to be 280~300nm.
Fig.2.1.1 Pep1 Process Flow of LTPS PMOS TFT.
Fig.2.1.2 Pep2 Process Flow of LTPS PMOS TFT.
Fig.2.1.3 Pep3 Process Flow of LTPS PMOS TFT.
Fig.2.1.4 Pep4 Process Flow of LTPS PMOS TFT.
Fig.2.1.5 Process Flow of LTPS PMOS TFT.
Fig.2.1.6 Pep6,7 Process Flow of LTPS PMOS TFT.
Fig.2.2.1 Structure of shielding metal which was employed Molybdenum.
Fig.2.4.1 I-V/C-V instruments set up in the laboratory.
Fig.2.5.1 The typical TFT output characteristics.
Fig.2.5.2 Poly TFT Transfer Characteristics (ID-VG Curve).
Temperature=125
OC Stress Bias V
G= -30V W / L = 6 / 6
1/(V
GS-V
FB)
2(V
-2)
0.004 0.005 0.006 0.007 0.008 0.009 0.010 0.011
ln [I
DS/(V
GS-V
FB)]
Fig.3.1.1 The cross-sectional view of proposed TFT.
Full Shielding TFT V
D=0.1V
Fig.3.1.2 The ID-VG transfer curves of full shielding TFT.
Brightness (nits)
2000 2500 3000 3500 4000 4500 5000 5500
P h oto Le a k a ge C u rr en t (p A )
Fig.3.1.3 The photo leakage current of full metal shielding TFT and convention TFT.
Full-Metal-Shielding TFT under Dark State
Fig.3.1.4 The ID-VG relationships of Full-Metal-Shielding TFT.
Fig.3.1.5 Back channel effect of full shielding TFT.
Drain
Fig.3.2.1 Poly-Si TFT with split metal shielding layer, M1.
Drain
Fig.3.2.2 Poly-Si TFT with split metal shielding layer, M2.
Drain
Fig.3.2.3 Poly-Si TFT with split metal shielding layer, M3.
Drain
Fig.3.2.4 Poly-Si TFT with split metal shielding layer, M4.
Drain
Fig.3.2.5 Poly-Si TFT with split metal shielding layer, M5.
M1 Device under Dark State
Fig.3.2.6 The ID-VG relationships of M1 devices.
M2 Device under Dark State
Fig.3.2.7 The ID-VG relationships of M2 devices.
M3 Device under Dark State
Fig.3.2.8 The ID-VG relationships of M3 devices.
M4 Device under Dark State
Fig.3.2.9 The ID-VG relationships of M4 devices.
M5 Device under Dark State
Fig.3.2.10 The ID-VG relationships of M5 devices.
Dark State V
D=0.1V
Fig.3.2.11 The ID-VG relationship of M1 TFT and Full-Metal-Shielding TFT with the drain voltage is 0.1V under darkness.
Dark State V
D=9V
Fig.3.2.12 The ID-VG relationship of M1 TFT and Full-Metal-Shielding TFT with the drain voltage is 9V under darkness.
5620nits V
D=0.1V
Fig.3.2.13 The ID-VG relationship of M1 TFT and Full-Metal-Shielding TFT with the drain voltage is 0.1V under illumination.
5620nits V
D=9V
Fig.3.2.15 The photo leakage current model of M1 TFT.
Dark State V
D=0.1V
Gate Voltage (V)
-15 -10 -5 0 5 10 15
D ra in C u rr en t (A )
10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4
Full Metal M2
Fig.3.2.16 The ID-VG relationship of M2 TFT and Full-Metal-Shielding TFT with the drain voltage is 0.1V under darkness.
Dark State V
D=9V
Fig.3.2.17 The ID-VG relationship of M2 TFT and Full-Metal-Shielding TFT with the drain voltage is 9V under darkness.
5620nits V
D=0.1V
5620nits V
D=9V
Gate Voltage (V)
-15 -10 -5 0 5 10 15
D ra in C u rr en t (A )
10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3
Full Metal M2
Fig.3.2.19 The ID-VG relationship of M2 TFT and Full-Metal-Shielding TFT with the drain voltage is 9V under illumination.
Fig.3.2.20 The photo leakage current model of M2 TFT.
Dark State V
D=0.1V
Fig.3.2.21 The ID-VG relationship of M3 TFT and Full-Metal-Shielding TFT with the drain voltage is 0.1V under darkness.
Dark State V
D=9V
5620nits V
D=0.1V
Fig.3.2.23 The ID-VG relationship of M3 TFT and Full-Metal-Shielding TFT with the drain voltage is 0.1V under illumination.
5620nits V
D=9V
Fig.3.2.24 The ID-VG relationship of M3 TFT and Full-Metal-Shielding TFT with the drain voltage is 9V under illumination.
Fig.3.2.25 The photo leakage current model of M3 TFT.
Dark State V
D=0.1V
Gate Voltage (V)
-15 -10 -5 0 5 10 15
Drain Current (A)
10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4
Full Metal M4
Dark State V
D=9V
Fig.3.2.27 The ID-VG relationship of M4 TFT and Full-Metal-Shielding TFT with the drain voltage is 9V under darkness.
5620nits V
D=0.1V
Fig.3.2.28 The ID-VG relationship of M4 TFT and Full-Metal-Shielding TFT with the drain voltage is 0.1V under illumination.
5620nits V
D=9V
Gate Voltage (V)
-15 -10 -5 0 5 10 15
D ra in C u rr en t (A )
10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3
Full Metal M4
Fig.3.2.29 The ID-VG relationship of M4 TFT and Full-Metal-Shielding TFT with the drain voltage is 9V under illumination.
Fig.3.2.31 The ID-VG relationship of M5 TFT and Full-Metal-Shielding TFT with the drain voltage is 0.1V under darkness.
Dark State V
D=9V
Gate Voltage (V)
-15 -10 -5 0 5 10 15
D ra in C u rr en t (A )
10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2
Full Metal M5
Fig.3.2.32 The ID-VG relationship of M5 TFT and Full-Metal-Shielding TFT with the drain voltage is 9V under darkness.
5620nits V
D=0.1V
Fig.3.2.33 The ID-VG relationship of M5 TFT and Full-Metal-Shielding TFT with the drain voltage is 0.1V under illumination.
5620nits V
D=9V
Fig.3.2.35 The photo leakage current model of M5 TFT.
Fig.3.2.36 The IPLC extracted at a voltage |VG-VTH| of 7V as VD is 0.1V for TFT.
V
D=9V |V
G-V
TH|=7V
Fig.3.3.1 The partial metal shielding layer is located in channel region.
Drain
Drain
Fig.3.3.3 The partial metal shielding layer is located in source junction region.
Channel Shielding TFT under Dark State
Gate Voltage (V)
Fig.3.3.4 The ID-VG relationships of poly-Si TFT with partial metal shielding layer located in channel region.
Drain Shielding TFT under Dark State
Fig.3.3.5 The ID-VG relationships of poly-Si TFT with partial metal shielding layer located in drain junction region.
Source Shielding TFT under Dark State
Gate Voltage (V)
2160nits VD=0.1V
Fig.3.3.7 The ID-VG relationships of Poly-Si TFT with metal shielding layer. The drain voltage is 0.1V, and the illumination is 2160 nits.
2160nits VD=5V
Fig.3.3.8 The ID-VG relationships of Poly-Si TFT with metal shielding layer. The drain voltage is 5V, and the illumination is 2160 nits.
2160nits VD=9V
Fig.3.3.9 The ID-VG relationships of Poly-Si TFT with metal shielding layer. The drain voltage is 9V, and the illumination is 2160 nits.
2160nits VD=15V
V
D=0.1V |V
G-V
TH|=7V
Drain
Glass Gate
Source
Metal Shielding Layer Buffer Layer
LDD region S/D region
Gate Oxide 3µm
Fig.3.3.13 The band diagram of Source-shielding TFT under illumination.
Drain
Glass Gate
Source
Metal Shielding Layer Buffer Layer
LDD region S/D region
Gate Oxide 3µm
Fig.3.3.15 The photo leakage current model of Drain-shielding TFT at linear region.
Fig.3.3.16 The photo leakage current model of Drain-shielding TFT at saturation region.
Fig.3.4.1 Poly-Si TFT with split metal shielding layer, the split near the drain junction.
Fig.3.4.2 The ID-VG characteristics of shielding TFT with low drain bias measured in forward and reverse modes at dark.
Dark V
D=9V
Gate Voltage (V)
-15 -10 -5 0 5 10 15
Drain Current (A)
10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3
Reverse Forward
Forward V
D=0.1V
Fig.3.4.4 The ID-VG relationships of Forward TFT operated in linear region at the dark and photo states.
Fig.3.4.5 The ID-VG relationships of Forward TFT operated in saturation region at the dark and photo states.
Reverse V
D=0.1V
Fig.3.4.6 The ID-VG relationships of Reverse TFT operated in linear region at the dark and photo states.
Fig.3.4.8 The photo leakage current model of Forward TFT.
Fig.3.4.9 The photo leakage current model of Reverse TFT.
Fig.3.4.10 The model of band diagram to explain the S.S degradation of Poly-Si TFT.
Fig.4.1.1 The Poly-Si TFTs with lightly doped drain (LDD) structure. It is stressed as VG=5V and VD=20V.
Dark Stress
Gate Voltage (V)
-10 -5 0 5 10
D ra in C u rr en t (A )
10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5
0s 1000s
74%
Fig.4.1.2 The ID-VG of TFTs in linear region after darkness stress.
5620nits Stress
Gate Voltage (V)
-10 -5 0 5 10
D ra in C u rr en t (A )
10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5
0s 1000s
60%
Fig.4.1.3 The ID-VG of TFTs in linear region after illumination stress.
Fig.4.1.4 The on current variation in dark stress and light stress.
Fig.4.1.5 Our proposed model as high drain voltage and small gate voltage are applied.
Fig4.1.6 Poly-Si TFT with lateral body thermal (LBT).
Fig.4.1.7 The Ibody-VG relationships of LBT poly-Si TFTs with the increasing brightness of back-light.
Fig.4.2.1 The gate electrode applies a AC pulse voltage, and source and drain is grounded.
Fig.4.2.2 The waveform of the AC signal.
Dark Stress V
D=0.1V
Gate Voltage (V)
-10 -5 0 5 10
D ra in C u rr en t (A )
10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5
0s 1s 100s 1000s 2000s
66.3%
Fig.4.2.3 The ID-VG of TFTs in linear region after darkness stress.
3280nits Stress V
D=0.1V
Gate Voltage (V)
-10 -5 0 5 10
D ra in C u rr en t (A )
10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5
0s 1s 100s 1000s 2000s
74.1%
Fig.4.2.4 The ID-VG of TFTs in linear region after illumination stress.
Fig.4.2.5 When a high voltage is applied to the gate, the device turns on and is operating in
Fig.4.2.6 When the gate voltage drops, the electrons in the channel move rapidly to the source and drain.
Fig.4.2.7 Some of the trapped electrons are exposed to the high electric field and grain energy from the field. The density of state (DOS) in tail edge of poly-Si is increased by the hot electrons.
Fig.4.2.8 shows the comparison of dark Stress and illumination stress.
Fig.4.3.1 The poly-Si TFT with a split metal shielding layer. The gate electrode applies a AC pulse voltage, and source and drain is grounded.
Dark Stress V
D=0.1V
Fig.4.3.2 The ID-VG of TFTs in linear region after darkness stress.
3280nits V
D=0.1V
Fig.4.3.3 The ID-VG of TFTs in linear region after illumination stress.
Fig.4.3.4 The band diagram of dark Stress and illumination stress.
Tables
Table.1 The comparison of the threshold voltage shift for different structure TFTs.
1.2
VTH(V) VD=0.1V
VTH(V)
VD=15V VTHShift (V)
Full Shielding 0.738 -1.038 1.776
M1 0.917 0.211 0.706
M2 0.952 0.454 0.498
M3 0.949 0.580 0.369
M4 0.953 0.654 0.299
M5 0.936 0.645 0.291
Table.2 The comparison of the variation of sub-threshold swing for different TFTs under illumination.
簡 歷
姓 名：林 威 廷 ( Wei-Ting Lin )
性 別：男
出生年月日：民國 73 年 04 月 06 日
住 址：台北縣三重市大智街147號4樓
學 歷：
國立中山大學物理學系學士 (91.9-95.6)
國立交通大學光電工程學系顯示科技研究所碩士 (95.9-97.6)
碩士論文題目:
低溫複晶矽薄膜電晶體於背光下之電性研究
Study on Electrical Characteristic of Low Temperature Polycrystalline Silicon Thin Film Transistors under Illumination