低溫複晶矽薄膜電晶體於背光下之電性研究

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國

立

交

通

大

學

電機學院光電工程學系

顯示科技研究所

碩士論文

低溫複晶矽薄膜電晶體於背光下

之電性研究

Study on Electrical Characteristic of

Low Temperature Polycrystalline Silicon Thin Film

Transistors under Illumination

研究生：林威廷

指導教授：劉柏村博士

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低溫複晶矽薄膜電晶體於背光下之電性研究

Study on Electrical Characteristic of Low Temperature

Polycrystalline Silicon Thin Film Transistors under Illumination

研究生：林威廷 Student：Wei-Ting Lin

指導教授：劉柏村博士 Advisor：Dr. Po-Tsun Liu

國立交通大學

顯示科技研究所

碩士論文

A Thesis

Submitted to Department of Photonics and Display Institute College of Electrical and Computer Engineering

National Chiao Tung University in Partial Fulfillment of the Requirements

for the Degree of Master

in Photonics June 2008

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低溫複晶矽薄膜電晶體於背光下之電性研究

研究生：林威廷指導教授：劉柏村博士

國立交通大學電機學院

光電工程學系顯示科技研究所

摘要

近年來液晶顯示器的需求急速升溫，中小尺寸高亮度高對比的顯示器需求也是成長近乎供不應求，例如在投影元件應用、行動通訊以及車用面板上都是。然而亮度提高相對的也會提高薄膜電晶體元件的光漏電流，此一漏電流的提高，會降低畫面顯示的對比度以及顯示顏色的偏差。因此降低或抑制元件在高亮度下的光漏電流是重要的。本論文中，先提出了一種具有金屬遮光層的薄膜電晶體。與傳統電晶體的差異為在其緩衝層底部沉積一層不透光的金屬材料，藉此隔絕光線直接入射至主動層。雖然此種新式結構可以有效的抑制光漏電效應，但由於本身結構使然，這種元件會受到汲極電壓與金屬遮光層的耦合效應，使得起始電壓在不同的汲極電壓操作下會有飄移的問題。為了改善耦合效應，在此研究中更近一步提出二種不同結構的遮光層元件，其金屬遮光層皆非完全覆蓋，預期能改善起始電壓飄移的問題。第一種元件具有不連續的金屬遮光層，有效降低起始電壓飄移的幅度。且其遮光層的缺口可控制光線入射的位置，用來釐清照光產生光漏電的機制，並提出一物理模型。第二種為局部遮光層的元件，完全解決了起始電壓飄移的問題。在線性區的操作下，能有效抑制光漏電，但是在飽和區的操作，受到汲極電壓與金屬遮光層的耦合效應，造成光漏電上升，同時也提出一物理模型來解釋此現象。此外，我們利用不連續金屬遮光層的元件，釐清照光時次臨界擺幅劣化的原因，並提出一物理模型。最後，為了模擬元件在實際應用時的衰退，分別在暗態及亮態的環境下做了直流電 壓以及交流電壓的可靠度測試，並提出薄膜電晶體在亮態下操作的衰退機制。

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Study on Electrical Characteristic of Low Temperature

Polycrystalline Silicon Thin Film Transistors under Illumination

Student : Wei-Ting Lin Advisor : Dr. Po-Tsun Liu

Department of Photonics and Display Institute

College of Electrical and Computer Engineering

National Chiao Tung University

English Abstract

The market for liquid crystal displays has been rapidly expanding in recent years. The demand for a high luminance and a high contrast ratio in liquid crystal displays (LCDs) is continuing to grow and seems insatiable. However, high luminance would increase photo leakage current (PLC) in the TFTs, which would cause a low contrast ratio. Consequently, it is necessary to suppress the PLC in LCDs with high illumination.

In this thesis, the Poly-Si TFT with a metal shielding layer is proposed. The metal shielding layer was deposited before buffer layer to block light beams directly illuminated on the active layer. The Metal-Shielding TFT has lower OFF-Current under illumination, but it induces another issue which is threshold voltage shift. In order to overcome the issue, the Split-Shielding TFT and Partial-Shielding TFT are proposed.

The metal layer in Split-Shielding TFT is not continuous; it reduces the ratio of threshold voltage shift. In addition, the split location of metal layer can control the exposed region of active layer. Based on the experiment results, the model is proposed to explain the relationships of photo leakage current with exposed region.

The Partial-Shielding TFT solves the issue of threshold voltage shift absolutely. It has lower OFF-Current under illumination in linear region, but not in saturation region. A model is proposed to explain the phenomenon. Besides, the mechanism of the degradation of sub-threshold swing in poly-Si TFT which is exposure to back-light is clarified.

Finally, we also apply the DC bias stress and AC bias stress on the device to test the devises stability under dark and illumination respectively. According to the result of this

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誌謝

在這兩年的碩士研究生涯中，有太多人令我心存感激。首先，要特別感謝我的指導教授劉柏村博士與張鼎張博士，感謝老師們的指導、教誨和鼓勵，不僅僅是在學術研究上的指導，對於人生規劃及待人處事的態度上，亦讓我獲益良多，使我能順利的完成碩士學位，在此致上內心最誠摯的敬意和謝意。此外，感謝論文口試當天的口試委員－吳文發主任以及李柏璁博士，你們的指導和建議，讓我對研究有了更進一步的想法，同時也對做研究的態度有更進一步的啟發，也在此謹申謝意。同時，感謝李泓緯學長與盧皓彥學長悉心的教導使我得以一窺薄膜電晶體領域的深奧，在實驗、量測分析以及論文寫作給予我莫大的協助與建議，使我在這些年中獲益匪淺，順利獲得知識與學位。另外亦得特別感謝吳興華學長、蔡志宗學長、鄒一德學長、與鍾宛芳學姐的大力協助，因為有你們的陪伴及幫忙讓兩年的研究生活變得絢麗多彩。還有要感謝陳緯仁學長、馮立偉學長、林昭正學長、胡志瑋學長、陳仕承學長、李勝凱學長，感謝學長們平日對我的照顧以及研究上的建議。也要感謝實驗室一起工作的同學－王超駿、陳巍方、鄭逸立、吳凱庭、羅元駿、廖述穎、鄧貴宇、江成能、薛培堃、王派璿、黃志文、黃宥豪、林儀倡、陳聖錡、竹立煒、蔡尚祐、郭豫杰、陳思維、張繼聖，以及學弟－張耿維、王信淵、蔡侑廷、張耀峰、謝介銘、蘇智昱、鄧立峯、楊維哲、黃羿霖，還有 DADS 實驗室的夥伴－何漢清、鄭枷彬、李允翔，感謝你們陪伴我共同走過這一段甘甜的日子，讓我無論是在實驗中或是讀書時永遠充滿歡樂。同時，衷心感謝國家奈米元件實驗室(NDL)和交大半導體中心提供良好的研究設備與充足的資源。最後，我願將這份榮耀呈獻給我深愛的家人，父親－林水河先生、母親－林陳玉琴女士、姐姐－林秀蓉小姐、以及弟弟－林成峯先生。感謝家人們的鼓勵，特別是父母親多年來辛苦的教導與栽培，一直以來的支持與關懷，陪我度過了許多風雨與榮耀的時光，讓我能無後顧之憂，全力衝刺學業，終於不負所望完成學業，在此獻上我內心最深的謝意。此外，特別要感謝陪伴我多年的女友－沈丹靈，在背後的默默支持更是我前進的動力，一直以來因為妳的支持及協助，使我能順利的從大學畢業到現在碩士學位的完成，在此由衷的對妳說聲謝謝。林威廷 2008 年 6 月

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Content

Abstract ... i

English Abstract... ii

Chinese Acknowledgment ... iii

Content ... iv

Figure Captions ... vi

Table Captions ... xii

Chapter 1 Introduction ... 1

1.1 Overview of Low-Temperature Polycrystalline Silicon Thin Film Transistors. 1 1.2 Motivation ... 3

1.3 Organization of This Thesis ... 4

Chapter 2 Device Fabrication and Experiment ... 6

2.1 Fabrication Process of Poly-Si TFTs ... 6

2.2 Devices Structure of Metal Shielding layer ... 6

2.3 Experimental procedure of Metal Shielding Layer Structure ... 7

2.4 Introduction of Instruments ... 7

2.5 Electrical Characterization Measurement and Analysis ... 8

2.5.1 Output characteristics ... 8

2.5.2 Methods of Device Parameter Extraction ... 9

Chapter 3 Poly-Si TFT with Metal Shielding Layer... 13

3.1 Full Metal Shielding TFT ... 13

3.2 Split Metal Shielding TFT... 14

3.3 Partial Metal Shielding TFT ... 18

3.4 Electrical Characteristics of Poly-Si TFT under Illumination... 21

Chapter 4 Bias Stress of Poly-Si TFT under Illumination ... 25

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4.3 AC Stress of Split Shielding TFT under illumination ... 27 Chapter 5 Conclusion ... 29 Reference ... 32 Figures ... 36 Tables ... 83 Vita ... 84

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Figure Captions

Fig.1.1.1 The ID-VG transfer curves of standard Poly-Si TFT. ... 36

Fig.2.1.1 The average grain size of polycrystalline silicon was found to be 280~300nm. ... 36

Fig.2.1.1 Pep1 Process Flow of LTPS PMOS TFT. ... 37

Fig.2.1.5 Process Flow of LTPS PMOS TFT. ... 37

Fig.2.1.6 Pep6,7 Process Flow of LTPS PMOS TFT. ... 38

Fig.2.2.1 Structure of shielding metal which was employed Molybdenum. ... 38

Fig.2.4.1 I-V/C-V instruments set up in the laboratory. ... 38

Fig.2.5.1 The typical TFT output characteristics. ... 39

Fig.2.5.2 Poly TFT Transfer Characteristics (ID-VG Curve). ... 39

Fig.2.5.3 Plotting of





ln D G FB I V V      _    versus





2 FB G

V



V

 . ... 40

Fig.3.1.1 The cross-sectional view of proposed TFT. ... 40

Fig.3.1.2 The ID-VG transfer curves of full shielding TFT. ... 41

Fig.3.1.3 The photo leakage current of full metal shielding TFT and convention TFT. ... 41

Fig.3.1.4 The ID-VG relationships of Full-Metal-Shielding TFT. ... 42

Fig.3.1.5 Back channel effect of full shielding TFT. ... 42

Fig.3.2.1 Poly-Si TFT with split metal shielding layer, M1. ... 43

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Fig.3.2.7 The ID-VG relationships of M2 devices. ... 45

Fig.3.2.11 The ID-VG relationship of M1 TFT and Full-Metal-Shielding TFT with the drain voltage is 0.1V under darkness. ... 47

Fig.3.2.12 The ID-VG relationship of M1 TFT and Full-Metal-Shielding TFT with the drain voltage is 9V under darkness. ... 47

Fig.3.2.13 The ID-VG relationship of M1 TFT and Full-Metal-Shielding TFT with the drain voltage is 0.1V under illumination. ... 48

Fig.3.2.14 The ID-VG relationship of M1 TFT and Full-Metal-Shielding TFT with the drain voltage is 9V under illumination. ... 48

Fig.3.2.15 The photo leakage current model of M1 TFT. ... 49

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Fig.3.2.24 The ID-VG relationship of M3 TFT and Full-Metal-Shielding TFT with the drain

voltage is 9V under illumination. ... 53

Fig.3.2.36 The IPLC extracted at a voltage |VG-VTH| of 7V as VD is 0.1V for TFT. ... 59

Fig.3.2.37 The IPLC extracted at a voltage |VG-VTH| of 7V as VD is 9V for TFT. ... 60

Fig.3.3.1 The partial metal shielding layer is located in channel region. ... 60

Fig.3.3.2 The partial metal shielding layer is located in drain junction region. ... 60

Fig.3.3.3 The partial metal shielding layer is located in source junction region. ... 61

Fig.3.3.4 The ID-VG relationships of poly-Si TFT with partial metal shielding layer located in channel region. ... 61

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Fig.3.3.5 The ID-VG relationships of poly-Si TFT with partial metal shielding layer located in

drain junction region. ... 62

Fig.3.3.6 The ID-VG relationships of poly-Si TFT with partial metal shielding layer located in source junction region. ... 62

Fig.3.3.7 The ID-VG relationships of Poly-Si TFT with metal shielding layer. The drain voltage is 0.1V, and the illumination is 2160 nits. ... 63

Fig.3.3.8 The ID-VG relationships of Poly-Si TFT with metal shielding layer. The drain voltage is 5V, and the illumination is 2160 nits. ... 63

Fig.3.3.11 The IPLC extracted at a voltage |VG-VTH| of 7V as VD is 0.1V for TFT. ... 65

Fig.3.3.12 The IPLC extracted at a voltage |VG-VTH| of 7V as VD is 9V for TFT. ... 65

Fig.3.3.13 The band diagram of Source-shielding TFT under illumination. ... 66

Fig.3.3.14 The band diagram of Drain-shielding TFT under illumination. ... 66

Fig.3.3.15 The photo leakage current model of Drain-shielding TFT at linear region... 67

Fig.3.3.16 The photo leakage current model of Drain-shielding TFT at saturation region. .... 67

Fig.3.4.1 Poly-Si TFT with split metal shielding layer, the split near the drain junction. ... 67

Fig.3.4.2 The ID-VG characteristics of shielding TFT with low drain bias measured in forward and reverse modes at dark. ... 68

Fig.3.4.3 The ID-VG characteristics of shielding TFT with high drain bias measured in forward and reverse modes at dark. ... 68

Fig.3.4.4 The ID-VG relationships of Forward TFT operated in linear region at the dark and photo states. ... 69

Fig.3.4.5 The ID-VG relationships of Forward TFT operated in saturation region at the dark and photo states... 69

Fig.3.4.6 The ID-VG relationships of Reverse TFT operated in linear region at the dark and photo states. ... 70

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Fig.3.4.7 The ID-VG relationships of Reverse TFT operated in saturation region at the dark

and photo states... 70

Fig.3.4.8 The photo leakage current model of Forward TFT. ... 71

Fig.3.4.9 The photo leakage current model of Reverse TFT. ... 71

Fig.3.4.10 The model of band diagram to explain the S.S degradation of Poly-Si TFT. ... 72

Fig.4.1.1 The Poly-Si TFTs with lightly doped drain (LDD) structure. It is stressed as VG=5V and VD=20V. ... 73

Fig.4.1.2 The ID-VG of TFTs in linear region after darkness stress. ... 73

Fig.4.1.3 The ID-VG of TFTs in linear region after illumination stress. ... 74

Fig.4.1.4 The on current variation in dark stress and light stress. ... 74

Fig.4.1.5 Our proposed model as high drain voltage and small gate voltage are applied. ... 75

Fig4.1.6 Poly-Si TFT with lateral body thermal (LBT). ... 75

Fig.4.1.7 The Ibody-VG relationships of LBT poly-Si TFTs with the increasing brightness of back-light. ... 76

Fig.4.2.1 The gate electrode applies a AC pulse voltage, and source and drain is grounded. . 76

Fig.4.2.2 The waveform of the AC signal. ... 77

Fig.4.2.3 The ID-VG of TFTs in linear region after darkness stress. ... 77

Fig.4.2.4 The ID-VG of TFTs in linear region after illumination stress. ... 78

Fig.4.2.5 When a high voltage is applied to the gate, the device turns on and is operating in ON state. The electrons gather to form a channel. ... 78

Fig.4.2.6 When the gate voltage drops, the electrons in the channel move rapidly to the source and drain. ... 79

Fig.4.2.7 Some of the trapped electrons are exposed to the high electric field and grain energy from the field. The density of state (DOS) in tail edge of poly-Si is increased by the hot electrons. ... 79

Fig.4.2.8 shows the comparison of dark Stress and illumination stress... 80

Fig.4.3.1 The poly-Si TFT with a split metal shielding layer. The gate electrode applies a AC pulse voltage, and source and drain is grounded. ... 80

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Table Captions

Table.1 The comparison of the threshold voltage shift for different structure TFTs. ... 83 Table.2 The comparison of the variation of sub-threshold swing for different TFTs under illumination... 83

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Chapter 1 Introduction

1.1 Overview of Low-Temperature Polycrystalline Silicon Thin Film

Transistors

Thin film transistor (TFT) is a metal-oxide-silicon field effect transistor (MOSFET) fabricated on an insulator substrate by employing all thin film constituents. Thin film transistors have been widely used as switching devices in flat panel display, such as active-matrix liquid crystal display (AMLCDs)[1]-[3], and organic light-emitting displays (OLEDs)[4]. Except large area displays, Poly-Si TFTs have been applied into some memory devices such as dynamic random access memories (DRAMs)[5], static random access memories (SRAMs)[6], electrical programming read only memories (EPROM)[7],electrical erasable programming read only memories (EEPROMs)[8]. Poly-Si TFTs are also very potential to be used on devices such as linear image sensors [9], thermal printer heads [10], photodetector amplifier[11], scanner[12], neutral networks[12], and three dimension LSIs [13]. Especially, the application in AMLCDs is the major reason to push the Poly-Si TFTs technology programming rapidly.

Poly-silicon is a silicon-based material, which contains numerous Si grains with sizes ranging from 0.1 to several um. In semiconductor manufacturing, poly-silicon is usually prepared by LPCVD (Low Pressure Chemical Vapor Deposition) and then annealed above 900 C, i.e. so called SPC (Solid Phase Crystallization) method. Obviously, the same way could not be applied on the flat panel display industry since glass's strain temperature is only about 650 C. Therefore, Low temperature poly-silicon (LTPS) technology is the novel technology specific for the flat panel display application. Presently there are several approaches in the preparation of LTPS film on glass or plastic substrate：Metal Induced Crystallization (MIC)、Cat-CVD、Laser anneal.

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The preparation of LTPS film is apparently more complicated than a-Si, but LTPS TFT has 100 times higher mobility than a-Si TFT and can carry out CMOS process on the glass substrate. The Poly-Si TFTs are currently investigated for applications in AMLCD. The possibility to integrate on the same substrate driving circuitry as well as switching devices seems to represent a major advantage of the poly-silicon technology over the amorphous silicon on, because the mobility of Poly-Si TFTs is usually larger than that of the amorphous silicon TFTs, for Poly-Si TFTs, a mobility larger than 50 cm2/v-s is easily achieved by presently mature technology, that is enough to used as peripheral driving circuits. Therefore the pixel array and the peripheral circuits can be made on the same glass, bring the era of system-on-glass (SOG) technology. The process complexity can be greatly simplified to lower the cost. In addition, due to the higher mobility of Poly-Si TFTs , the dimension of the Poly-Si TFTs can be made smaller compared to that of amorphous Si TFTs for high density、high resolution AMLCDs.

In small size AMLCD application, such as the projector, which must be high resolution and small size to reduce the cost associated with the projection optical system and remain the graphic quality. On the other hand, Poly-Si TFTs also play the role of light shutters in projection display. The higher durability against luminance and heat is required because those devices are placed close to a high-power lamp. Undoubtedly, Poly-Si TFT technology is the most promising approach.

However, some problems still exist in applying Poly-Si TFTs on large-area displays. In comparison with single-crystalline silicon, Poly-Si is rich in grain boundary defects as well as intra-grain defects, and the electrical activity of the charge-trapping centers profoundly affects the electrical characteristics of Poly-Si TFTs. Large amount of defects serving as trap states locate in the disordered grain boundary regions to degrade the ON current seriously[14]. Moreover, the relatively large leakage current is one of the most important issues of

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the leakage current in poly TFTs is field emission via grain boundary traps due to the high electric field near the drain junction. To solve these problems, some crystallization methods such as excimer laser annealing (ELA) have been introduced to enlarge the grain size[17]. A drain offset region or lightly-doped drain (LDD) region is used to effectively lower leakage current by decreasing drain electric field[18]. Now, some studies of Poly-Si TFTs also focus on developing new technologies to lower the maximum fabrication temperature, which enables the use of low-quality glass and therefore reduce production cost[19]. Some reported papers focus on the fabrication and characterization of small-dimensional Poly-Si TFTs[20], which has high driving ability and high resolution and can be applied on AMLCD peripheral circuitry or the high-resolution projectors. In summary, it is expected that the Poly-Si TFTs will becomes more and more important in future technologies, especially when the 3-D circuit integration era is coming. More researches studying the related new technologies and the underlying mechanisms in Poly-Si devices with shrinking dimensions are therefore worthy to be indulged in.

1.2 Motivation

The market for liquid crystal displays has been rapidly expanding in recent years. The demand for a high luminance and a high contrast ratio in liquid crystal displays (LCDs), such as small-medium LCDs for projection device, mobile displays and displays for cars, is continuing to grow and seems insatiable. However, high luminance would increase photo leakage current (PLC) in the TFTs, which diminishes the voltages that are held across the pixel electrodes or affect the gray level controlling, which in turn, would cause a low contrast ratio and error color display. For instance, the off current of Poly-Si TFTs exposure at the 2160nits backlight is higher that in the dark, which is about higher three order. Fig.1.1.1 shows the ID-VG transfer curves of standard Poly-Si TFT at the linear operation under the dark

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gate bias is varied from 0 to -12 V. With the same range of gate bias, the leakage current of Poly-Si TFTs under illumination is as high as three orders of magnitude, about 10-11A. It is clearly observed that the on/off current ratio of Poly-Si TFTs was substantially decreased to seriously affect the function of TFTs used as the pixel switch under illumination environment. In addition, the sub-threshold swing is increased under illumination, about 0.49 V/decade, as the initial value in dark is 0.28 V/decade. The variation of sub-threshold swing is about 75%. Since the light from back-light is mainly absorbed at the interface of Poly-Si and the glass substrate, plenty of light-induced electron-hole pairs are accumulated in the bottom of Poly-Si film to generate the IPLC.

We proposed a light-shielding structure, it used an opaque material to shield the light. It is the most effective to cut-off the light from the backlight source. And we make the shielding layer with several kind structures. The first is full shielding layer, second is split shielding layer, and finally the partial shielding layer.

1.3 Organization of This Thesis

This thesis is divided into four chapters. After a brief introduction given in Chapter 1, the fabrication of the poly-Si TFTs device structure in Chapter 2 has been described. In addition, brief descriptions aboutthe instruments for cryogenics system and current-voltage (I-V) measurement are also included. At the end, we describe the methods of device parameter extraction.

In Chapter 3, the photo leakage current of poly-Si TFT with full shielding structure, split shielding structure, and partial shielding structure has been measured. Then, we describe the photo leakage current mechanism of poly-Si TFT, giving a brief description about the degradation mechanism of sub-threshold swing when measurement under illumination.

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about the AC stress definition and the degradation mechanism of AC stress, showing and analyzing the electrical characteristics of poly-Si TFTs with various AC stress conditions under darkness and illumination.

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Chapter 2 Device Fabrication and Experiment

2.1 Fabrication Process of Poly-Si TFTs

The top gate n-channel and self align light drain doping (LDD) TFTs were fabricated on Corning1737 glass substrate [21]. First, the buffer SiNx/oxide layer and 50 nm thickness a-Si:H film were deposited by plasma enhanced chemical vapor deposition (PECVD) at 380℃, we dehydrogenated aSi:H film in a furnace at 450℃. Then the poly silicon channel was formed by 308nm XeCl excimer laser irradiation at 350mJ/cm2. In this work, 95% laser overlap ratio was adopted to obtain large grain size and better uniformity of active layer. As the SEM Fig.2.1.1, the average grain size of polycrystalline silicon was found to be 280~300nm [22]. The island was patterned by plasma dry etching Fig.2.1.2. The 100nm thickness gate insulator was deposited by TEOS (Tetra-Ethyl-Ortho-Silicate)-base oxide. The source/drain and LDD region were formed by the mass-separated ion implanter technique. The doping activation was performed at 530℃/1hr thermal furnace and RTA irradiation, as shown in Fig.2.1.3-2.1.4. Finally, the interlayer oxide and inter-connection metal were deposited and pattern. The H2 plasma hydrogenation was performed in a commercial RF parallel-plate plasma reactor at 100W, 480℃ 15min in H2 and Argon gas mixture. The SiO2/SiNx with 300nm and 100nm interlayer film and source/drain contact holes etching and S/D metal patterning, as shown in Fig. 2.1.5. Finally, the planer layer (UHA2) and ITO were employed on our device Fig.2.1.6 [23]-[25]; the device electrical measurements were finished by HP4156C.

2.2 Devices Structure of Metal Shielding layer

Fig.2.2.1 was shown the shielding structure with molybdenum (Mo), it was oversimplification and directly perceived way to suppress or cutoff the backlight to reach the Poly-Si active layer. The section 2.3 specified how the process to be implemented.

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2.3 Experimental procedure of Metal Shielding Layer Structure

The n-channel Poly-Si TFTs with LDD structure were fabricated on Corning1737 glass substrate. First of all, a 50nm thick molybdenum film was sputtered and was patterned using additional mask to be a shielding layer on the glass substrate. The buffer layer and a thin 50 nm-thick undoped a-Si film were sequentially deposited by PECVD at 380℃, followed by dehydrogenated via furnace annealing process at 450℃. Then the a-Si films were crystallized by 308nm XeCl excimer laser with the line-shaped beam power of 350mJ/cm2. The 100nm thickness gate insulator was deposited by TEOS oxide. The source/drain regions were defined by a mask and formed by the mass-separated ion implanter technique. Then, MoW was sputtered and patterned as a gate metal [26]. Following, implantation for LDD region is preformed on overall device after the S/D photoresistor is removed. The doping activation was performed by RTA irradiation. The dimensions of TFTs in this work were L = 18 μm, W = 18 μm and the LDD length is 1.25 μm.

2.4 Introduction of Instruments

The electrical test setup of HP4156C semiconductor parameter analyzer is utilized in this experiment, illustrated in Fig.2.4.1, a probe station is situated inside a dark box. The ground probe station is furnished with an electrically isolated, water-cooled thermal chuck. The chuck is controlled by Temptronic TPO315A thermal controller, which can operate temperature from 25C to 300C. An Agilent 4156C precision semiconductor parameter analyzer can provide I-V measurement, bias for BTS, and quasi C-V measurement, etc. We employ the ICS (Interactive Characterization Software) to obtain the output and transfer characteristics, like VD- ID, VG- ID (Linear), VG- ID (saturation), and extract the typical semiconductor parameters

.

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2.5 Electrical Characterization Measurement and Analysis

2.5.1 Output characteristics

The typical TFT output characteristics are shown in Fig.2.5.1. They represent the dependence of the Drain-Source current (IDS) on the Drain-Source voltage (VDS) at different

gate voltage (VGS). The Drain-Source current increase linearly at low Drain-Source voltage

(Linear regime/operation) and saturates at high Drain-Source voltage (Saturation regime /operation). The saturation values of IDS depend on the applied gate voltage. When the low

gate voltage is applied, the thickness of the induced channel is small and current is low. On the other hand, thicker channel is induced at high gate voltage and the saturation current is higher. Well-separated output characteristics are an indication of good ohmic contact at drain and source. The transistor enters in saturation regime when VDS >VSAT , where VSAT=VGS-VT .

In ID-VD curve, the points corresponding to VDS = VSAT are connect the blue line described

the following equation:





_   _      2 2 1 T GS DS V V L W Cox fe I  (2-1)

When W and L are the width and length of the transistor channel, μfe is the field-effect

electron mobility and Cox is the gate insulator capacitance. The threshold voltage and the field

mobility effect mobility can be determined from measuring the saturation current, plotting the square root of the measured IDS vs. VGS in saturation ( VDS≧VGS-VT ).

Of course, the Poly-Si TFTs are not perfect device as the single crystalline; it is since the grain boundary [27]. The region of operation in Poly-Si TFT roughly:

A. Cut-off : Current is due to reverse-bias drain junction leakage trap-assisted mechanisms. B. Subthreshold : Current is due to carrier diffusion. Limited by source junction potential

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C. Pseudo-subthreshold : Current is due to carrier drift. Inversion-charge density Qinv

increases ~linearly with VG-VT. The field mobility μfe increases ~ exponentially with VG

→ ID increases ~ exponentially with VG.

D. Above threshold : Current is due to carrier drift, Qinv VG-VT; μfe ~ constant → ID

increases linearly with VG

Refer to the Fig.2.5.2.

2.5.2 Methods of Device Parameter Extraction

In this section, we will introduce the methods of typical parameter extraction such as the threshold voltage VT, subthreshold swing S.S, field-effect mobility FE from the device

characteristics.

Several methods are used to determinate the threshold voltage, VT , which is the most

important parameter of the semiconductor devices. The method to determinate the threshold voltage in this thesis is the constant drain current method, the voltage at a specific normalized drain current NID is taken as the threshold voltage. This technique is adopted in most studies

of TFTs. It can give a threshold voltage close to that obtained by the complex linear extrapolation method. Typically, the specific normalized current NID = ID/(W/L) is defined at

10nA for VD operated in linear region and 100nA for VD operated in saturation region, to

extract the threshold voltage of TFTs in most papers.

The subthreshold swing S.S (V/dec) is a significant parameter to describe the control ability of gate bias toward drain current and the efficiency of the switch turning on and off. It is defined as the amount of gate voltage required to increase/decrease drain current by one order of magnitude. It should be independent of drain voltage and gate voltage. However, in reality, the subthreshold swing might increase with drain voltage due to the short-channel effects such as charge sharing, avalanche multiplication, and punch through-like effects. It is also related to the gate voltage due to some undesirable factors such as serial resistance and

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interface state. In this experiment, the subthreshold swing is defined as one-second of the gate voltage required to decrease the threshold current by two orders of magnitude. The threshold current is specified to be the drain current when the gate voltage is equal to the threshold voltage.

The field-effect mobility (FE) is determined from the transconductance gm at low drain

voltage (linear region). The transfer characteristics of Poly-Si TFTs are similar to those of conventional MOSFETs, ignoring any other non-ideal effect and assuming the electric field in the channel is uniform, so the first order I-V relationship in the bulk Si MOSFETs can be applied to the Poly-Si TFTs, which can be expressed as

2 1 [( ) ] 2 D FE ox G T D D W I C V V V V L     (2-1) where Cox is the gate oxide capacitance per unit area

W is channel width L is channel length

VT is the threshold voltage.

If VD is much smaller than (VG-VT) (i.e., VD << VG-VT ) and VG > VT, the drain current can

be approximated as: ( ) D FE ox G T D W I C V V V L    (2-2) The transconductance is defined as

D FE ox const V G D m V L WC V I g D



    _ _. (2-3)

Therefore, the field-effect mobility can be obtained by

gm D ox FE WV C L   (2-4)

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The extraction method of the trap density Nt is following. From the Seto’s model, the

grain boundary potential barrier height VB can be expressed by the following equation

2 ₂ 2 2 8 t t B s s N qN qn V n n      _ _    (2-5)

where VB is the grain boundary potential barrier height

n is the carrier concentration

Nt is the grain boundary trap density

The grain boundary potential barrier height VB is related to the carrier concentrations

inside the grain and the trapping states located at grain boundaries. Based on this consideration, the amount of trap state density Nt can be extracted from the current-voltage

characteristics of Poly-Si TFTs. As proposed by Levinson et al. [28], the I-V characteristics including the trap density can be obtained by the following equation









3 2 0 exp 8 t ch D ox G TH D s ox G TH q N t W I C V V V L kT C V V       __ __    (2-6)

This equation had been further corrected by Proano et al. by considering the mobility under low gate bias [29]. It is found that the behavior of carrier mobility under low gate bias can be expressed more correctly by using the flat-band voltage VFB instead of the threshold

voltage VTH. Moreover, a better approximation for channel thickness tch in an undoped

material is given by defining the channel thickness as the thickness at which 80 percent of the total charge resides. Therefore, by solving the Poisson’s equation, the channel thickness is given by





8 _s _{o x} ch ox G FB kT t qC V V     (2-7)

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2 2 0 ( ) exp 2 2 ( ) ox t s D ox G FB D ox G FB q N W I C V V V L C V V                    (2-8)

The effective trap state density then can be obtained from the slope of the curve





ln_I_D/ V_GV_FB _ versus



V_G V_FB



2 as in Fig.2.5.3 and we can calculate the slope from it. The grain boundary trap-state density can be determined from the square root of the slope directly, expressed by the simplified equation below.

ox trap C N Slope q  (2-9)

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Chapter 3 Poly-Si TFT with Metal Shielding Layer

3.1 Full Metal Shielding TFT

The cross-sectional view of proposed TFT is illustrated in Fig.3.1.1. A thin metal film which is deposited on the glass substrate is to block the light emitted into poly-Si thin film. Fig.1.1.1 shows the ID-VG transfer curves of standard poly-Si TFT at the linear operation

under the dark and photo states. As the gate bias is varied from 0 to -12 V, the leakage current of poly-Si TFTs in the darkness was around 10-14A. With the same range of gate bias, the leakage current of poly-Si TFTs under illumination raises three orders of magnitude, about 10-11A. It is clearly observed that the on/off current ratio of poly-Si TFTs was substantially decreased and seriously affect the function of TFTs used as the pixel switch under illumination environment. In addition, the sub-threshold swing is increased under illumination, about 0.49 V/decade, as the initial value in dark is 0.28 V/decade. The variation of sub-threshold swing is about 75%. Since the light from back-light is mainly absorbed at the interface of poly-Si and the glass substrate, plenty of light-induced electron-hole pairs are accumulated in the bottom of poly-Si film to generate the IPLC [30].

To solve this issue, the poly-Si TFT with full metal shielding structure was proposed. The ID-VG transfer curves of proposed poly-Si TFT under the dark and photo states are shown in

Fig.3.1.2. It is clearly observed that the IPLC is entirely eliminated in the proposed poly-Si TFT.

The leakage current is about 10-12 A under illumination at the linear operation, as same as that in the dark state. The sub-threshold slope is also absolutely unchanged under illumination by the light-shielding structure. Fig.3.1.3 shows comparison of the photo leakage current of full metal shielding TFT and convention TFT. The Metal shielding TFT reduce photo leakage well even the brightness enhances to 5620nits.

The drain voltage is 0.1V when measure ID-VG relationships in linear region, and in

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Full-Metal-Shielding TFT. It is clearly that the VTH of Poly-Si TFT with partial metal

shielding layer is dependent of drain bias. The VTH decreases when the drain voltage increases.

The VTH is 0.738V when the drain voltage is 0.1V, and the VTH is -1.038V when the drain

voltage is 15V. The shift of VTH is 1.776V. The VTH of proposed TFT is dependent of drain

voltage so that the drain current would increase with drain bias.

Since the metal film is located under the poly-Si active layer, a parasitic capacitance in the overlap of source and drain side is generated. The positive voltage at drain side would lead to a positive potential distribution, VM, in the metal film owing to the coupling effect. VM is

regarded as the substrate bias to affect the threshold voltage of the proposed poly-Si TFTs[31]. The threshold voltage shifts in negative are explained by the positive VM induces the back

channel in the bottom of Poly-Si layer shown in Fig.3.1.5. Therefore, the split metal shielding structure for poly-Si TFT is proposed and discussed in the next section.

3.2 Split Metal Shielding TFT

Shown as Fig.3.2.1-3.2.5, there are five kind of Poly-Si TFT with split metal shielding layer. We assign numbers to those devices is M1, M2, M3, M4, and M5. The split of metal shielding layer located at different place. The split of M1 device is the nearest to the Source, and followed by M2, M3, M4, and M5.When we put a light source under the device, the light beams will go through the splits to different location of semiconductor layer.

Fig.3.2.6-3.2.7 plots the ID-VG relationships of M1 and M2 devices. It is found that the

VTH shift slightly when compare with full metal shielding TFT. Fig.3.2.8-3.2.10 plots the

ID-VG relationships of the M3, M4 and M5 devices. It is clearly that the VTH of poly-Si TFT

with split metal shielding layer is independent of drain bias. The detail results are listed in Table.1.

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Then, we want to know where the critical region is to induce photo leakage current when the device exposure with light. Fig.3.2.11 shows the ID-VG relationship of M1 device and

Full-Metal-Shielding device with the drain voltage is 0.1V. Measuring in darkness environment, the photo leakage current of M1 device and Full-Metal-Shielding device are the same. Fig.3.2.12 shows the ID-VG relationship under darkness and the drain voltage is 9V.

Fig.3.2.13 shows the ID-VG relationship under 5620nits brightness and the drain voltage is

0.1V. Fig.3.2.14 shows the ID-VG relationship under 5620nits brightness and the drain voltage

is 9V. The photo leakage current of M1 still keep the same with Full-Metal-Shielding device. It determines that the light beams go through the split in M1 device will not affect photo leakage current. The electron-hole pairs produced by light cannot separate and diffuse to Drain no matter the capacity of drain voltage. The electrons and holes will combine in recombination center, Shown as Fig.3.2.15.

Fig.3.2.16 shows the ID-VG relationship of M2 device and Full-Metal-Shielding device

with the drain voltage is 0.1V. Measuring in darkness environment, the photo leakage current of M2 device and Full-Metal-Shielding device are the same. Fig.3.2.17 shows the ID-VG

relationship under darkness and the drain voltage is 9V. Fig.3.2.18 shows the ID-VG

relationship under 5620nits brightness and the drain voltage is 0.1V. Fig.3.2.19 shows the ID-VG relationship under 5620nits brightness and the drain voltage is 9V. The photo leakage

current of M2 still keep the same with Full-Metal-Shielding device. It determines that the light beams go through the split in M2 device will not affect photo leakage current. The electron-hole pairs produced by light cannot separate and diffuse to Drain no matter the capacity of drain voltage. The electron and hole will combine in recombination center, Shown as Fig.3.2.20.

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relationship under 5620nits brightness and the drain voltage is 0.1V. The photo leakage current of M3 still keep the same with Full-Metal-Shielding device. It is particularly when measures under 5620nits brightness and the drain voltage is 9V, shown as Fig.3.2.24. The photo leakage current of M3 device increases slightly and large than Full-Metal-Shielding device. It determines that the light beams go through the split in M3 device will affect photo leakage current slightly. Fig.3.2.25 shows the photo leakage current model of M3 TFT. When the drain voltage is 0.1V, the electron-hole pairs produced by light cannot separate and diffuse to Drain. The electron and hole will combine in recombination center. But when the drain voltage is 9V, the electron field in active layer is strong. The high drain voltage will also induce the floating potential, VM, in the Metal layer. The VM will induce the back channel in

the bottom of Poly-Si layer. The electron-hole pairs produced by light cannot separate and drift to Drain.

relationships under 5620nits brightness and the drain voltage is 0.1V. The photo leakage current of M4 still keep the same with Full-Metal-Shielding device. It is particularly different when measures under 5620nits brightness and the drain voltage is 9V, shown as Fig.3.2.29. The photo leakage current of M4 device is large than Full-Metal-Shielding device. It determines that the light beam go through the split in M4 device will affect photo leakage current. Fig.3.2.30 shows the photo leakage current model of M3 TFT. When the drain voltage is 0.1V, the electron-hole pairs produced by light cannot separate and diffuse to Drain. The electron and hole will combine in recombination center. But when the drain voltage is 9V,

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potential, VM, in the Metal layer. The VM will induce the back channel in the bottom of

Poly-Si layer. The electron-hole pairs produced by light cannot separate and drift to Drain. Fig.3.2.31 shows the ID-VG relationship of M5 device and Full-Metal-Shielding device

relationship under darkness and the drain voltage is 9V. The photo leakage current of M5 still keep the same with Full-Metal-Shielding device. It is particularly different when measures under 5620nits brightness and the drain voltage is 0.1V or 9V, shown as Fig.3.2.33-3.2.34. The photo leakage current of M5 device is large than Full-Metal-Shielding device. It determines that the light beam go through the split in M5 device will affect photo leakage current, Show as Fig.3.2.35. Compare to M4 device, M5 device has large photo leakage current under brightness when the drain voltage is 0.1V. It is because the split of M5 device located in the edge of Drain, the electron-hole pairs produced by light can separate and diffuse to Drain. But the split of M4 has a distance to Drain, the electron will combine with holes in recombination center during it diffuse to Drain.

Fig.3.2.36 reveals the comparison of IPLC which is extracted at a voltage |VG-VTH| of 7V

as VD is 0.1V for TFT, the vertical axis is the normalization of drain current, and the

horizontal axis is illumination of light source under the device. The M5 devices have the highest of photo leakage current, and the M4, M3, M2, and M1 devices are lower. It indicates that the location of split will influence photo leakage current. The semiconductor layer absorbs light to produce electron-hole pairs. If the distance from split to Drain was short, the electron-hole pairs will separate. Then the electrons arrive to Drain, inducing photo leakage current. However, if the distance from split to Drain is long, the electron-hole pairs will not separate and arrive to Drain. The electron-hole pairs will be combined during the electrons diffuse to Drain.

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as VD is 9V for TFT, the vertical axis is the normalization of drain current, and the horizontal

axis is illumination of back light source. When the drain voltage enhance to 9V, the distribution of the curves are different. The M5, M4, and M3 devices are the higher of photo leakage current, the M2, and M1 devices are lower. It indicates that the location of split will influence photo leakage current. Enhancing the drain voltage will change the distribution of curves. When drain voltage increased to 9V, the limit diffusion distance from split to Drain is increased. Therefore, the M4 and M3 devices have larger photo leakage current. But the electron-hole pairs of M1 and M2 devices still cannot separate and arrive to Drain, so the leakage current of M1 and M2 are similar, and smaller than others.

3.3 Partial Metal Shielding TFT

The partial metal shielding layer is located in channel (Channel-shielding TFT) and junction region of channel (Drain-shielding TFT and Source-shielding TFT) as shown in Fig.3.3.1-3.3.3, respectively. As the shielding metal is located in the channel and shorter than the gate metal shown in Fig.3.3.1, the space between the edge of shielding metal and the gate metal is set to 3μm. Fig.3.3.2-3.3.3 plots the Poly-Si TFT with shielding metal remained to be located in junction side. Similarly, the overlap region between the edge of shielding metal and the gate metal is 3μm. Therefore, the effect of location for IPLC is investigated employing the

two types of Poly-Si TFT with different partial metal shielding structure.

Fig.3.3.4-3.3.6 plots the ID-VG relationships of poly-Si TFT with partial metal shielding

layer located in channel region (Channel-shielding TFT) and drain junction region (Drain-shielding TFT) and source junction region (Source-shielding TFT) as drain voltage is varied at dark state. It is clearly that the VTH of poly-Si TFT with partial metal shielding layer

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Then, we measure with a light source under the device, controlling input current to decide illumination. The condition of illumination is 2160nits. Fig.3.3.7 plots the ID-VG

relationships of Poly-Si TFT with different kind of metal shielding layer. The drain voltage is 0.1V, and the illumination is 2160 nits. The Drain-shielding TFT reduces photo leakage current as well as Full-shielding TFT. The capacity of the off current is about 10-12~10-11A. The Source-shielding TFT and the Channel-shielding TFT have larger photo leakage current, the capacity is about 10-11A.

We increase the drain voltage but keep the same illumination. Shown as Fig.3.3.8, the drain voltage is 5V. It is clearly that only Full-shielding TFT has smaller photo leakage current, the Drain-shielding TFT cannot keep the same capacity of photo leakage current with Full-shielding TFT. Shown as Fig.3.3.9-3.3.10, the drain voltage is 9V and 15V. The photo leakage current of Drain-shielding TFT increases as Source-shielding TFT and the Channel-shielding.

as VD is 0.1V for TFT with Full-shielding TFT and partial metal shielding layer located in

channel region (Channel-shielding TFT), drain side (Drain-shielding TFT) and source side (Source-shielding TFT) as brightness of back-light is in Channel creased (2160, 3100, 4110,and 5620nits). The IPLC of Full-shielding TFT and Drain-shielding TFT are much lower

than that of Channel-shielding TFT and Source-shielding TFT. The maximum values of IPLC

of Full-shielding TFT, Drain-shielding TFT, Channel-shielding TFT and Source-shielding TFT are 4pA, 4.1pA, 19.2pA and 24.5pA. In addition, the IPLC of Full-shielding TFT and

Drain-shielding TFT exhibit a weak dependence on the increasing brightness of back-light. The result confirms that drain side is the dominant region for IPLC of Poly-Si TFT operated in

linear region. Fig.3.3.12 shows the IPLC of Full-shielding TFT, Drain-shielding TFT,

Channel-shielding TFT and Source-shielding TFT as drain voltage is 9V. It is observed the shielding effect of Full-shielding TFT is reduced markedly. The Drain-shielding TFT cannot

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keep the same IPLC with Full-shielding TFT, but it is still less than that of Channel-shielding

TFT and Source-shielding TFT.

While Poly-Si TFT is exposure to back-light, the excess electron-hole pairs are generated. The regions generating photo-induced electron-hole pairs can be divided into two parts. One is drain junction region, and the other is channel region. The excess electron-hole pairs, generated in drain junction, would be separated due to the electric field and the excess electrons could flow to drain to become leakage current. By contrast, since Si is an indirect band-gap material, photo-induced electron-hole pairs in channel region could not be recombined directly. Therefore, the excess electrons in channel region would diffuse to drain to form current. It is inferred that the IPLC is attributed to the diffusion current and drift current

from channel region and drain junction, respectively. As shown in Fig.3.3.13, the band diagram to explain the generation of IPLC for Source-shielding TFT is proposed. Since the

shielding metal is located in source side, the excess electrons generated at channel and junction region flow to drain by diffusion and drift, leading to the IPLC. Fig3.3.14 shows the

band diagram of Drain-shielding TFT under illumination. As the shielding metal is located in drain side, light emitting to the junction region is blocked to eliminate the junction part of IPLC.

In addition, the electrons induced by light outside the shielding metal are difficult to diffuse to drain since the excess electrons must to pass through an intrinsic Poly-Si region, while drain voltage is 0.1V, as shown in Fig3.3.15. Hence, Drain-shielding TFT operated in linear region exhibits a highest immunity to illumination environment compared to Source-shielding TFT and Channel-shielding TFT. However, as the high voltage is applied at drain, a positive potential distribution, VM, in the shielding metal of Drain-shielding TFT owing to the

coupling effect is generated due to the parasitic capacitance in the overlap of drain and shielding metal. Hence, electrons induced by VM gather to form the back channel near drain in

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Therefore, the shielding effect of Drain-shielding TFT under illumination would be suppressed by applied high drain voltage.

3.4 Electrical Characteristics of Poly-Si TFT under Illumination

In this chapter, IPLC and S.S behavior of Poly-Si TFT with specific process steps under

illumination is discussed. In order to clarify the factors of affecting the sub-threshold properties of Poly-Si TFT under illumination, a patterned metal shielding layer is used to investigate the electrical characteristics of Poly-Si TFTs under light exposure. By patterned metal shielding structure, the exposure region is controlled to be located in the drain or source junction. Based on the analysis of measurement results, the key factors effectively influent the photo leakage and the sub-threshold swing are observed clearly in this work.

Fig.3.4.1 shows the poly-Si TFT with split metal shielding layer, the split located near the drain junction. Fig.3.4.2 shows the ID-VG characteristics of shielding TFT with low drain

bias measured in forward and reverse modes at dark. The exposure region is located close to the drain and source junction for forward and reverse measurement, respectively. The two curves are almost identical and VTH of TFT in forward mode (Forward TFT) is as same as that

of TFT in reverse mode (Reverse TFT). However, the VTH of Reverse TFT is slightly less than

that of Forward TFT while drain voltage is 9V, as shown in Fig.3.4.3. Since the shielding layer for Forward TFT has a gap in drain junction, the potential distribution coupling from drain voltage would not extend into channel region. Therefore, VTH of Forward TFT is

independent of applied drain bias. By contrast, the shielding metal of Reverse TFT is distributed over most of channel region from drain. It is indicates that the potential distribution induced by high drain voltage, VM, in the metal film of Reverse TFT would affect

the VTH. In addition, the S.S of Forward TFT and Reverse TFT is unchanged by drain voltage

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Fig.3.4.4 plots transfer curves of Forward TFT operated in linear region at the dark and photo states. As the gate bias is -12V, the leakage current of Forward TFTs is about 10-14~10-13A at dark but is significantly increased under illumination. The IPLC is 2.5x10-11A,

approximately three orders of magnitude greater than the dark leakage current. In addition, the S.S is slightly raised under illumination. The S.S under dark and photo states is 0.36 V/decade and 0.41 V/decade, respectively. As the drain bias is 9V, the ID-VG relationships of Forward

TFT at dark and photo states are illustrated in Fig.3.4.5. Similarly, a markedly high IPLC and

the nearly unaltered S.S of Forward TFT under illumination are observed clearly. Since the width of depletion region at drain would be increased with high drain bias, the more electron-hole pairs induced by light would be separated in the depletion region. Therefore, in forward mode, the IPLC at high drain voltage is higher than that under low drain voltage.

The ID-VG characteristics of Reverse TFT are also investigated in this work, as shown in

Figs.3.4.6-3.4.7, respectively. As VD is 0.1V, the IPLC of Reverse TFT is 2.7x10-12A, as low as

one order of magnitude, compared to that in Forward TFT under same drain voltage. Furthermore, the S.S under illumination in Fig.3.4.6 is almost unchanged. The increase ratio of S.S in Reverse TFT is about 12.96% as drain bias is 0.1V. Fig.3.4.7 indicates that the S.S of Reverse TFT with high drain voltage, however, is substantially degraded under illumination. It is increased 54.08% of the magnitude of that at dark state. The detail results of the variation of S.S are listed in Table.2. With high drain bias, the IPLC is also increased in Reverse TFT but

still lower than that in Forward TFT. From the comparison in Forward TFT and Reverse TFT with high and low drain bias, it is inferred the significant increase of S.S in the Reverse TFT would be attributed to that the exposure region is located in source junction and the device is operated with high drain voltage.

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junction. Therefore, excess electrons could flow directly to the drain, leading to the IPLC, as

shown in Fig.3.4.8. By contrast, the exposure region of Reverse TFT is close to source side. As the drain bias is low, numerous electron-hole pairs generated in source junction is difficult to be separated by lateral electrical field. Therefore, the excess electrons flowing to drain is fewer to cause the lower IPLC. However, as the drain voltage is high, a positive potential

distribution, VM, in the metal film owing to the coupling effect is generated from the parasitic

capacitance in the overlap of drain and metal shielding layer [32]. Hence, electrons induced by VM gather to form the back channel in the bottom of Poly-Si layer, as illustrated in

Fig.3.4.9. So that excess electrons at source junction would flow to drain through the back channel and excess holes is residual to be accumulated in the source junction to form the floating body which offers a positive potential. It can be inferred that the degraded S.S in Poly-Si TFTs under illumination is mainly caused by the floating body with positive potential near the source side. The key factors to affect IPLC and the S.S under illumination are clarified

clearly using the patterned metal shielding layer in Poly-Si TFTs.

When the gate bias is below the threshold and the semiconductor surface is in weak inversion or depletion, the corresponding drain current is the sub-threshold current.[] In weak inversion and depletion, the electron charge is small, the drain current is dominated the diffused electron from source in n-type Poly-Si TFT. Therefore, it would be affected strongly by the barrier height of source. As the gate bias is applied, the barrier height of source is lowered to increase the amount of electron in channel diffused from source. Therefore, it is clearly observed that the S.S current is dependent of the applied gate voltage. The sub-threshold current in poly-Si TFT is empirically expressed [33]:

𝐈_𝐬𝐮𝐛 = 𝐈_{𝐬𝐮𝐛𝟎}𝐞𝐱𝐩⁡[𝐪(𝐕𝐆− 𝐕𝐆𝟎) 𝐧𝐤𝐁𝐓 ]

For simplity and giving more clear physics picture, it is also can be expressed as following equation [34]:

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𝐈_𝐬𝐮𝐛 ∝ 𝐞𝐱𝐩⁡(𝜷𝝋_𝒔)

It indicates that, the drain current varies exponetntially with 𝛗_𝐬 in the subthreshold region, where 𝛗_𝐬 is the suface potential.

Based on the experimental results of treated TFT and shielding TFT, a model of band diagram to explain the S.S degradation of Poly-Si TFT is proposed, as shown in Fig.3.4.10. First, as the excess electron-hole pairs are generated under illumination with positive drain voltage, the light-induced electrons flow to drain directly, forming the photo leakage current. Therefore, the residual excess holes are accumulated in the Poly-Si film to form the floating body with a positive channel potential, ΔV. Hence, the source barrier is lowered by ΔV due to the floating positive potential distributed in the channel. While the applied gate bias is swept from negative to positive directions and smaller than the threshold voltage, TFT would be operated at sub-threshold region. So the source barrier would be lower again by the positive gate bias. However, the more lowering source barrier induce that the excess holes accumulated in channel are more easily diffuse to the source to reduce the positive channel potential. So that the fewer channel potential leads to a raise of source barrier. It means that the source barrier is not only controlled by applied gate bias but also affected by the floating body with positive potential, ΔV when Poly-Si TFTs are under illumination. In our method of treated TFT, the trap states on the top face of buffer layer can effectively recombine the excess electron-hole pairs induced by back light. So that amount of accumulated holes is also reduced effectively to suppress the effect of floating body. Hence, the improvement of sub-threshold swing is clearly observed in this work. In addition, the results of shielding TFT confirm that the effective region affecting by floating positive potential is the source junction.

(39)

Chapter 4 Bias Stress of Poly-Si TFT under Illumination

4.1 DC Stress under illumination

Fig.4.1.1 shows the Poly-Si TFTs with lightly doped drain (LDD) structure. We stressed the poly-Si TFT as VG=5V and VD=20V are applied. During the stress time of 1000sec, we

measured the ID-VG in 1, 10, 100, and 1000sec, comparing the device behavior which was

stressed in light and dark. Fig.4.1.2 shows the ID-VG of TFTs in linear region in dark. It could

be observed that the on current decrease 74% after 1000sec dark stress. The decrease of the off current means the decrease of the mobility which owing to the tail states increase. The VTH

and S.S do not change after 1000sec stress, so the deep state does not increase. Fig.4.1.3 shows the ID-VG of TFTs in linear region in darkness. The on current decreases 60% after

1000sec light stress. Fig.4.1.4 shows the on current variation in dark stress and light stress. We could observe that the on current decrease less as we measured the TFT under light stress than under dark stress.

Fig.4.1.5 shows our proposed model. In the dark, as high drain voltage and small gate voltage are applied, impact ionization is occurred in the junction between channel and drain due to the high electric field. The damage in the junction is remarkable when the high electric field is applied. Since the light emitted from back-light is mainly absorbed at the interface between the poly-Si layer and the buffer layer, plenty of electron-hole pairs are generated in the bottom of poly-Si film. As the electron-hole pairs are generated, the electric field in the junction of channel and drain decrease. So the on current decreases less when we measured the TFT under light stress than under dark stress.

In order to verify the model, we employed a Poly-Si TFT with lateral body thermal (LBT) as shown in Fig.4.1.6. The lateral body thermal is near the Drain thermal as the drain voltage is applied on the n+ region which near p+ region. The p+ region could sense hole current

低溫複晶矽薄膜電晶體於背光下之電性研究

國

立

交

通

大

學

電機學院光電工程學系

顯示科技研究所

碩 士 論 文

低溫複晶矽薄膜電晶體於背光下

之電性研究

Study on Electrical Characteristic of

Low Temperature Polycrystalline Silicon Thin Film

Transistors under Illumination

研 究 生：林威廷

指導教授：劉柏村 博士

低溫複晶矽薄膜電晶體於背光下之電性研究

Study on Electrical Characteristic of Low Temperature

Polycrystalline Silicon Thin Film Transistors under Illumination

研 究 生：林威廷 Student：Wei-Ting Lin

指導教授：劉柏村 博士 Advisor：Dr. Po-Tsun Liu

國 立 交 通 大 學

顯 示 科 技 研 究 所

碩 士 論 文

低溫複晶矽薄膜電晶體於背光下之電性研究

研究生：林威廷 指導教授：劉柏村 博士

國立交通大學 電機學院

光電工程學系顯示科技研究所

摘要

Study on Electrical Characteristic of Low Temperature

Polycrystalline Silicon Thin Film Transistors under Illumination

Student : Wei-Ting Lin Advisor : Dr. Po-Tsun Liu

Department of Photonics and Display Institute

College of Electrical and Computer Engineering

National Chiao Tung University

English Abstract

誌 謝

Content

Figure Captions









V



V

Table Captions

Chapter 1 Introduction

1.1 Overview of Low-Temperature Polycrystalline Silicon Thin Film

Transistors

1.2 Motivation

1.3 Organization of This Thesis

Chapter 2 Device Fabrication and Experiment

2.1 Fabrication Process of Poly-Si TFTs

2.2 Devices Structure of Metal Shielding layer

2.3 Experimental procedure of Metal Shielding Layer Structure

2.4 Introduction of Instruments

.

2.5 Electrical Characterization Measurement and Analysis

2.5.1 Output characteristics





2.5.2 Methods of Device Parameter Extraction























Chapter 3 Poly-Si TFT with Metal Shielding Layer

3.1 Full Metal Shielding TFT

3.2 Split Metal Shielding TFT

3.3 Partial Metal Shielding TFT

3.4 Electrical Characteristics of Poly-Si TFT under Illumination

碩士論文

研究生：林威廷

指導教授：劉柏村博士

研究生：林威廷 Student：Wei-Ting Lin

指導教授：劉柏村博士 Advisor：Dr. Po-Tsun Liu

國立交通大學

顯示科技研究所

碩士論文

研究生：林威廷指導教授：劉柏村博士

國立交通大學電機學院

誌謝