Conclusion

Chapter 1 Introduction

2.6 Conclusion

In this chapter, we investigate the influences of the channel width and S/D width on the drain current at both 〝on〞 and 〝off〞 state. At on state, the drain current is enlarged by increasing the side channel width and this is because the additional current flow paths existed in the side channel region. On the contrary, at off state, the drain leakage current is not obviously related to the side channel width. These conclusions are listed as follows：

(1) The current flow lines can exist in the side channel region. If we increase the side channel region width, the on-state current of the test structure should be increased.

(2) If the channel length is increased, there will be more current flow lines existed in the side channel region.

(3) The side current flow lines distribute within a certain side channel width. Besides, this width should be related to the channel length.

Chapter 3 Experimental of Low-Temperature poly-Si TFTs with thick S/D and thin channel

3.1 Introduction

In poly-Si TFTs, the dominant leakage current mechanism has been reported. It arises from the field emission via grain boundary by a high electric field near the drain [10]. Recently, some studies on the influence of lateral electric field on the anomalous leakage current of poly-Si TFTs has been reported [9,17]. It was found that the high lateral electric field at the channel/drain junction can be effectively reduced by use of a thicker source/drain but thinner channel structure. However, this fabrication will need five lithography steps. In this chapter, we will discuss the device performance of our novel staggered structure of poly-Si TFTs (4-masks) and the comparisons of our structure with the conventional staggered structure (5-masks) and conventional co-planar structure (4-masks) are also shown.

3.2 Device fabrication

The conventional staggered poly-Si TFTs were fabricated on 6-inch-diameter n-type silicon wafer. The fabrication process flow is as follows. At first, amorphous silicon (a-Si) films with three kinds of thickness (100nm, 200nm, and 300nm) were deposited on thermally oxidized Si wafers by LPCVD system at 620°C with SiH4 as the gaseous source. After the first lithography step, we used the TCP system to etch amorphous silicon films. Then amorphous silicon (a-Si) films with a thickness of

50nm were deposited on thermally oxidized Si wafers by LPCVD system at 620°C with SiH4 again. Then the solid phase crystallization (SPC) process was carried out with 600°C for 24 hours. After the second lithography step, the poly silicon layer was then defined as the active region and we used the TCP poly-etcher system to etch other poly-Si film. A 50 nm-thick TEOS oxide film was deposited at 350°C to serve as the gate dielectric by PECVD. Then, a 300 nm-thick poly-Si was deposited by LPCVD at 620°C with SiH4 for the gate electrode and the third lithography step was used to define gate region. The active region was doped by 5E15 ions/cm²phosphorus implantation at a 50 KeV(100nm), 70 KeV(200nm), and 100 KeV(300nm) of acceleration voltage. The dopants were activated at 600°C in N2 ambient for 24 hours.

Next, a 300-nm oxide was deposited by PECVD at 350°C as a passivation layer, and contact lithography was carried out. After opening contact holes, a 500-nm Al was deposited by evaporation and the metal layer was patterned. Finally, the samples were sintered at 400° C for 30 minutes in N2 gas ambient. After completing the device fabrication, no hydrogenation step was performed. Therefore, this fabrication needs five lithography steps.

However, in our proposed staggered structure, after the second amorphous silicon (a-Si) films with a thickness of 50-nm were deposited, the SPC was carried out.

The second a-Si films were removed after defining gate region. Therefore, the channel width should be wider than the S/D width in our proposed staggered structure as shown in Figure 3.3 and this new fabrication only need four lithography steps.

The critical five-lithography fabrication procedures are shown in Figure 3.1 and listed as follows：

1. Thermal wet oxidation at 980°C to grow 500 nm thermal SiO2 in furnace

2. α-Si (100 nm, 200 nm and 300 nm) film was deposited by LPCVD at 620°C in SiH4 gas

3. Mask#1: define S/D island

4. α-Si (50nm) film was deposited by LPCVD at 620°C in SiH4 gas 5. SPC was carried out with 600°C for 24 hrs

6. Mask#2: define active region

7. 50 nm TEOS gate dielectric deposition by PECVD at 350°C

8. 300 nm poly-Si gate was deposited by LPCVD at 620°C in SiH4 gas 9. Mask#3: define gate region

10. Poly-Si film was dry etched by TCP system

11. Ion implantation: P³¹, 5×10¹⁵ cm^-2, 50 KeV (100 nm), 70 KeV (200 nm) ,100 KeV (300 nm)

12. Dopant activation in N2 ambient at 600°C for 24 hr

13. 300 nm TEOS oxide film was deposited by PECVD at 350°C for the passivation layer

14. Mask#4: open contact holes 15. Wet etching by B.O.E

16. 500 nm Al thermal evaporation 17. Mask#5: Al pads definition

18. Etching Al and removing photoresist

19. Al sintering at 400°C in N2 ambient for 30 min

The critical four-lithography fabrication procedures are shown in Figure 3.2 and listed as follows：.

1. Thermal wet oxidation at 980°C to grow 500 nm thermal SiO2 in furnace 2. α-Si (100 nm, 200 nm and 300 nm) film was deposited by LPCVD at 620°C in

SiH4 gas

3. Mask#1: define S/D island

4. α-Si (50nm) film was deposited by LPCVD at 620°C in SiH4 gas

5. SPC was carried out with 600°C for 24 hrs

6. 50 nm TEOS gate dielectric deposition by PECVD at 350°C

7. 300 nm poly-Si gate was deposited by LPCVD at 620°C in SiH4 gas 8. Mask#2: define gate region

9. Poly-Si film was dry etched by TCP system 10. Ion implantation:

11. Dopant activation in N2 ambient at 600°C for 24 hr

12. 300 nm TEOS oxide film was deposited by PECVD at 350°C for the passivation layer

13. Mask#3: open contact holes 14. Wet etching by B.O.E

15. 500 nm Al thermal evaporation 16. Mask#4: Al pads definition

17. Etching Al and removing photoresist

18. Al sintering at 400°C in N2 ambient for 30 min

3.3 The experimental results of the proposed staggered structure

Figures 3.4~3.7 show the ID-VG curve of our proposed structure with different S/D thickness. We can see that the leakage current (at Vgs = -15 V) is reduced by increasing the thickness of source/drain. It is due to that the proposed structure has a thicker S/D to reduce the lateral electric field near the drain junction. Next, we compare the conventional co-planar structure, conventional staggered structure and our proposed staggered structures. In our proposed structure, the channel width is wider than the S/D width. However, the channel width is identical to the S/D width in conventional staggered structure. In Figures 3.8~3.11, we use the different channel

length (Lch = 3 μm and Lch = 15 μm) and different S/D width (Wsd = 5 μm and Wsd = 10 μm) to compare the transfer characteristics. Although these device parameters are different, these transfer characteristics have the same tendency. As shown in table 1~4, for the two kinds of staggered structures, the leakage currents (at Vgs = -15 V) are all smaller than convention co-planar structure. In addition, the drain currents of the conventional staggered structure are almost the same as the conventional co-planar structure at on-state. These results are responsible with previous literatures [9,17].

Owing to the existence of the side current flows, the drain currents of our proposed staggered structure with wider channel width would be larger than the conventional stagger structure in on-state(VG = 30 V) . Moreover, the drain currents of our proposed staggered are obviously larger than the conventional co-planar structure when the channel length is 15μm. This result fits the second conclusion in chapter 2.

Further, it can be seen that the minimum drain currents are also enlarged. It also results from the side current flows.

In table 1 ~ 4, it can be seen that on/off ratio of our proposed staggered structure is decreased. In off state, compared with conventional staggered structure and conventional co-planar structure, the leakage current of the conventional staggered structure is larger than that of the co-planar structure. It is due to more grain boundary traps exist in the thick channel regions near the S/D region. Moreover, compared with the conventional staggered structure and the proposed structure, the leakage current of the proposed structure is larger than that of the conventional staggered structure.

However, it is due to that the side channel current would increase the drain leakage current. Therefore, the on/off current ratio of our proposed structure is smaller than the conventional co-planar structure. Although, the on/off current ratio is smaller, the drain leakage current (at Vgs = -15 V) would significantly decrease about one order.

Therefore, our proposed staggered structure can not only enlarge on-state current but

also decrease the leakage current (at Vgs = -15 V). Of course, it also can reduce our cost because it needs only four masks.

3.4 Conclusion

In this chapter, we discuss the electrical properties of the novel structures with thicker S/D width and wider channel length. The drain leakage current (at Vgs = -15 V) would be decreased and the on-state current would be increased. However, the on/off ratio is also decreased.

Chapter 4 Conclusion and future work

4.1 Conclusion

In this thesis, we first discuss the influences of the channel width and S/D width on the drain current at both on-state and off-state. Then we use these results to discuss the electrical properties of the novel staggered structure with thicker S/D region and wider channel region. The drain current at on-state will be enlarged and the leakage current (Vgs = -15V) will be decreased. In our fabrication process, we only need four lithography steps. Therefore, the novel structure of thicker S/D region and wider channel region exhibits superior electrical characteristics to the conventional co-planar structure. Hence, the proposed high performance poly-Si TFTs are promising for the application of integrated circuits on LCS panel.

4.2 Future work

We have proposed a novel low-temperature poly-Si TFTs with a thicker source/drain region and wider channel to improve the conventional low-temperature poly-Si TFTs performance. In order to further improve electrical properties of our devices, there will be still some works worth of being investigated.

In our experiment, the minimum leakage current of the proposed structures was increased due to large number of the grain boundary traps near the drain region existence. It is well known that NH3 or H2 plasma could significantly reduce the grain boundary traps due to the formation of S≣N and S-H bonds [18]. In addition, we also can establish the drain current model of the test structure with wider channel region.

Reference

[1] T.Serilawa, S.shirai, A. Okamoto, and S. Suyama, “Low-temperature fabrication of high-mobility Poly-Si TFTs for large-area LCD’s,” IEEE Trans. Electron Dev., vol. 36, no. 9, pp. 1929,1989.

[2] J. R. Ayres and N. D. Young, “Hot carrier effects in devices and circuits formed from poly-Si,” IEEE proc. Circuits Devices Syst., vol. 131, no. 1, p.38, 1994.

[3]S.D Brotherton, “Topical review：Polycrystalline silicon thin film transistors,”

Sci.Technoi., vol.10, pp721-738, 1995.

[4] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider,

“Conductivity behavior in polycrystalline semiconductor thin film transistors,” J.

Appl. Phys. Vol. 53, pp.1193-1202, 1982

[5] P. Migliorato, C. Reita, G. Tallatida, M. Quinn and G. Fortunato, “Anomalous off-current mechanisms in n-channel poly-Si thin film transistors.”

Solid-State-Electronics, Vol.38, pp.2075-2079, 1995

[6] M. Hack, I-W. Wu, T. H. King and A. G. Lewis, “Analysis of Leakage Currents in Poly-silicon Thin Film Transistors,” IEDM Tech. Dig., vol. 93, pp. 385-387, 1993 [7] Byung-Hyuk Min and Jerzy Kanicki, “Electrical characteristics of new LDD

poly-Si TFT structure tolerant to process misalignment,” IEEE Electron Device Lett., vol. 20, pp. 335-337, 1999

[8] Shengdong Zhang, Ruqi Han, and Mansun J. Chan, “A novel self-aligned bottom gate poly-Si TFT with in-situ LDD,” IEEE Electron Devices Lett., vol. 22, pp.

393-395, 2001.

[9] A. Kumar K.P. and J. K. O Sin, “Influence of lateral electric field on the

anomalous leakage current in polysilicon TFT,” IEEE Electron Device Lett, vol.

20, pp.27-29, 1999

[10]K.R.Olasupo and M.K.Hatalis, “Leakage current mechanism in sub-micron polysilicon Thin-Film Transistors,” IEEE Trans. Electron Device, vol. 43, no.8, pp.1218-1223, 1996

[11] S. M. Sze, Physics of Semiconductor Devices, 2^nd ed., Taiwan: John Wiley &

Sons, 1981, pp. 433-448.

[12] Gi-Young Yang, Sung-Hoi Hur, and Chul-Hi Han, “A Physical-Based Analytical Turn-On Model of Polysilicon Thin-Film Transistors for Circuit Simulation,”

IEEE Trans. Electron Devices, vol.46, no.1, pp.165-172, Jan. 1999.

[13] Hsin-Li Chen and Ching-Yuan Wu, “A New I-V Model Considering the Impact-Ionization Effect Initiated by the DIGBL Current for the Intrinsic n-Channel Poly-Si TFT’s,” IEEE Electron Device Letters, vol. 46, no. 4, pp.

772-728, Apr. 1999.

[14] Peyman Servati, and Arokia Nathan, “Modeling of the Reverse Characteristics of a-Si:H TFTs,” IEEE Trans. Electron Devices, vol.49, no.5, pp.812-819, May.

2002.

[15] Horng Nan Chern, Chung Len Lee, and Tan Fu Lei, “An Analytical Model for the Above-Threshold Characteristics of Polysilicon Thin-Film Transistors,” IEEE Trans. Electron Devices, vol.42, no.7, pp.1240-1246, Jul. 1995.

[16] Filippos V. Farmakis, Jean Brini, George Kamarions, Constantinos T. Angelis, Charalambos A. Dimitriadis, and M. Miyasaka, “On-Current Modeling of Large-Grain Polycrystalline Silicon Thin-Film Transistors,” IEEE Trans.

Electron Devices, vol.48, no.4, pp.701-706, Apr. 2001.

[17] Ching-Wei Lin; Li-Jing Cheng; Yin-Lung Lu; Yih-Shing Lee; Huang-Chung Cheng , “High-performance low-temperature poly-Si TFTs crystallized by excimer laser irradiation with recessed-channel structure,” IEEE Electron Device Letters, vol.22, pp. 269 – 271, 2001

[18] W. Wu, W. B. Jackson, T. Y. Huang, A. G. Lewis, and A. C. Chiang,

“Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation,” IEEE Electron Device Lett., vol. 12, no. 5, pp. 181–183, May 1991

Table 1

off-state current 7.6×10^-12 1.07×10^-11 1.9×10^-11 The leakage

current (Vgs = -15 V)

1.26×10^-7 4.06×10^-8 3.07×10^-8

On/Off ratio 1.2×10⁷ 1.07×10⁷ 8.95×10⁶

Table 1： Compared with the maximum on-state current (V_gs= 30 V), the minimum off-state current and the leakage current (V_gs= -15 V ). The channel length (L_ch) is 3 μm, S/D width (W) is 5μm, and drain voltage ( V_ds ) is 5 V.

on-state current 1.97×10^-4 2.06×10^-4 2.65×10^-4 The minimum

off-state current 1.33×10^-11 1.69×10^-11 2.44×10^-11 The leakage

current

（V_gs= -15 V）

3.7×10^-7 5.2×10^-8 6.2×10^-8

On/Off ratio 1.48×10⁷ 1.19×10⁷ 1.1×10⁷

Table 2： Compared with the maximum on-state current (Vgs = 30 V), the minimum off-state current and the leakage current (Vgs = -15 V ). The channel length (Lch) is 3 μm, S/D width (W) is 10μm, and drain voltage ( Vds ) is 5 V.

Table 3

on-state current 2.7×10^-5 2.56×10^-5 6.3×10^-5 The minimum

off-state current 2.6×10^-12 5.1×10^-12 8.57×10^-12 The leakage

current

（Vgs = -15 V）

1.9×10^-7 2.8×10^-8 1.8×10^-8

On/Off ratio 1.04×10⁷ 5.02×10⁶ 7.35×10⁶

Table 3： Compared with the maximum on-state current (Vgs = 30 V), the minimum off-state current and the leakage current (Vgs = -15 V ). The channel length (Lch) is 15 μm, S/D width (W) is 5μm, and drain voltage ( Vds ) is 5 V.

on-state current 5.06×10^-5 5×10^-5 8.73×10^-5 The minimum

off-state current 3.94×10^-12 5.98×10^-12 9.8×10^-12 The leakage

current

（V_gs= -15 V）

2.5×10^-7 5.2×10^-8 3.55×10^-8

On/Off ratio 1.28×10⁷ 8.36×10⁶ 8.91×10⁶

Table 4： Compared with the maximum on-state current (V_gs= 30 V), the minimum off-state current and the leakage current (V_gs= -15 V ). The channel length (L_ch) is 15 μm, S/D width (W) is 10μm, and drain voltage ( V_ds ) is 5 V.

Region I: main channel Region II: side channel

Figure 2.1(a) Top view of the test structure

S D W _s,d

L I _ch W _ch

Figure 2.1(b) Top view of the conventional structure

Figure 2.2 (a) The current flow lines of 2-D numerical simulator

structure with Lch = 3μm , Wsd = 5μm.

MEDICI simulation for the conventional structure. (b) The current flow lines of 2-D numerical simulator MEDICI simulation for the test

Figure 2.2 (c) The current flow lines of 2-D numerical simulator MEDICI simulation for the test structure with L_ch= 10μm , W_sd = 5μ m.(d) The current flow lines of 2-D numerical simulator MEDICI simulation for the test structure with Lch = 10μm , Wsd = 10μm.

-10 0 10 20 30 10^-11

10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4

Lch=5

μ

m; Wsd=5

μ

m; Vd=5V

ΔWch=0

μ

m ΔWch=2

μ

m ΔWch=4

μ

m ΔWch=6

μ

m ΔWch=14

μ

Drain current,Id(A)

Gate Voltage,Vg(V)

Figure 2.3(a) ID-VG curve with different △Wch

20 30 2x10^-5

4x10^-5 6x10^-5 8x10^-5 10^-4

Lch=5

μ

m; Wsd=5

μ

m; Vd=5V

ΔWch=0

μ

m ΔWch=2

μ

m ΔWch=4

μ

m ΔWch=6

μ

m ΔWch=14

μ

Drain current,Id(A)

Gate Voltage,Vg(V)

Figure 2.3(b) ID-VG curve with different △Wch

-10 0 10 20 30 10^-11

10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4

ΔWch=0

μ

m ΔWch=2

μ

ΔWch=4

μ

m ΔWch=6

μ

m ΔWch=14

μ

Drain current,Id(A)

Gate Voltage,Vg(V) Lch=5

μ

^{m; Wsd=10}

μ

^{m; Vd=5V}

Figure 2.3(c) ID-VG curve with different △Wch

20 30 5x10^-5

10^-4 1.5x10^-4 2x10^-4 2.5x10^-4 3x10^-4

Wch=0 μ m

Wch=2 μ m

Wch=4 μ m

Wch=6 μ m

Wch=14 μ m

Drain cur rent ,I d(A)

Gate Voltage,Vg(V) Lch=5 μ m; Wsd=10 μ m; Vd=5V

Figure 2.3(d) ID-VG curve with different △Wch

-2 0 2 4 6 8 10 12 14 16 18 20

-2 0 2 4 6 8 10 12 14 16 18 20 and V_gs = 30 V for different channel length

-2 0 2 4 6 8 10 12 14 16

min. off state current max. on state current

Leakage current (pA)

Figure 2.7(a) the maximum drain current and minimum of-state current virus △Wch at Wsd = 5 μm, Vds = 5 V for channel length is 15 μm

Figure 3.1 The critical five-lithography fabrication procedures

Figure 3.2 The critical four-lithography fabrication procedures

Figure 3.3(a) Top view of the proposed staggered structure

G

Figure3.3 (b) the cross-section view of the AB line

-10 0 10 20 30 10^-11

10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4

Drain current (A )

Gate voltage(V) L=3 um; W=5 um; Vd= 5 V

proposed staggered 1000 proposed staggered 2000 proposed staggered 3000

Figure 3.4 I_D - V_G curve for L_ch= 3 μm, W = 5 μm and V_d = 5 V for different S/D width (100 nm , 200 nm ,300 nm )

-10 0 10 20 30 10^-11

10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4

Gate voltage(V)

Dr ain cur rent (A)

L=3 um; W=10 um; Vd= 5 V

proposed staggered 1000 proposed staggered 2000 proposed staggered 3000

Figure 3.5 I_D - V_G curve for L_ch= 3 μm, W = 10 μm and V_d = 5 V for different S/D width (100 nm , 200 nm ,300 nm )

-10 0 10 20 30 10^-12

10^-11 10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4

L=15 um; W=5 um; Vd= 5 V

Drain current (A)

Gate voltage(V)

proposed staggered 1000 proposed staggered 2000 proposed staggered 3000

Figure 3.6 I_D - V_G curve for L_ch= 15μm, W = 5μm and V_d = 5 V for different S/D width (100 nm , 200 nm ,300 nm )

-10 0 10 20 30 10^-11

10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4

Dr ai n c u rr ent (A )

Gate voltage(V) L=15 um; W=10 um; Vd= 5 V

proposed staggered 1000 proposed staggered 2000 proposed staggered 3000

Figure 3.7 I_D - V_G curve for L_ch= 15 μm, W = 10 μm and V_d = 5 V for different S/D width (100 nm , 200 nm ,300 nm )

-10 0 10 20 30 10^-11

10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4 10^-3

5-masks conv. staggered 4-masks prop. staggered conv. co-planar

Drain current (A)

Gate voltage(V) L=3 um; W=5 um; Vd= 5 V

Figure 3.8 I_D - V_G curve for L_ch= 3μm, W = 5μm and V_d = 5 V for the proposed staggered structure, conventional staggered structure and conventional co-planar structure.

-10 0 10 20 30 10^-11

10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4 10^-3

Drain current(A)

Gate voltage(V)

5-masks conv. staggered 4-masks prop. staggered conv. co-planar

L=3 um; W=10 um; Vd= 5 V

Figure 3.9 I_D - V_G curve for L_ch= 3 μm, W = 10 μm and V_d = 5 V for the proposed staggered structure, conventional staggered structure and conventional co-planar structure

-10 0 10 20 30 10^-12

10^-11 10^-10 10^-9 10^-8 10^-7 10^-6 10^-5

5-masks conv. staggered 4-masks prop. staggered conv. co-planar

D rain c u rr ent (A )

Gate voltage(V) L=15 um; W=5 um; Vd= 5 V

Figure 3.10 I_D - V_G curve for L_ch= 15 μm, W = 5 μm and V_d = 5 V for the proposed staggered structure, conventional staggered structure and conventional co-planar structure

-10 0 10 20 30 10^-12

10^-11 10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4

Drai n current (A)

Gate voltage(V) L=15 um; W=10 um; Vd= 5 V

5-masks conv. staggered 4-masks prop. staggered conv. co-planar

Figure 3.11 I_D - V_G curve for L_ch= 15 μm, W = 10 μm and V_d = 5 V for the proposed staggered structure, conventional staggered structure and conventional co-planar structure

簡歷

姓名：陳正國

性別：男

出生日期：民國 70 年 3 月 5 日

出生地：台灣省新竹市

住址：彰化縣員林鎮東和里員水路二段 566 巷 26 弄 8 號

學歷：台中市國立台中一中(民國 85 年 9 月~88 年 6 月)

國立成功大學物理學系(民國 88 年 9 月~92 年 6 月)

國立交通大學電子工程所碩士班(民國 92 年 9 月~95 年 8 月)

碩士論文：具有較厚源/汲極與較寬通道的多晶矽薄膜電晶體的模擬與電性分析

The Simulations and Analysis of The Poly-Si Thin Film Transistor with Thicker S/D and wider Channel

在文檔中具有較厚源/汲極與較寬通道的多晶矽薄膜電晶體的模擬與電性分析 (頁 18-0)

Chapter 1 Introduction

2.6 Conclusion

Chapter 3

Experimental of Low-Temperature poly-Si TFTs with thick S/D and thin channel

3.1 Introduction

3.2 Device fabrication

3.3 The experimental results of the proposed staggered structure

3.4 Conclusion

Chapter 4

Conclusion and future work

4.1 Conclusion

4.2 Future work

Reference

Region I: main channel Region II: side channel

S D W s,d

L I ch W ch

μ

μ

μ

μ

μ

μ

μ

μ

μ

μ

μ

μ

μ

μ

μ

μ

μ

μ

μ

μ

μ

Wch=0 μ m

Wch=2 μ m

Wch=4 μ m

Wch=6 μ m

Wch=14 μ m

Drain cur rent ,I d(A)

Gate Voltage,Vg(V) Lch=5 μ m; Wsd=10 μ m; Vd=5V

G

Drain current (A )

Gate voltage(V) L=3 um; W=5 um; Vd= 5 V

proposed staggered 1000 proposed staggered 2000 proposed staggered 3000

Gate voltage(V)

Dr ain cur rent (A)

L=3 um; W=10 um; Vd= 5 V

proposed staggered 1000 proposed staggered 2000 proposed staggered 3000

L=15 um; W=5 um; Vd= 5 V

Drain current (A)

Gate voltage(V)

proposed staggered 1000 proposed staggered 2000 proposed staggered 3000

Dr ai n c u rr ent (A )

Gate voltage(V) L=15 um; W=10 um; Vd= 5 V

proposed staggered 1000 proposed staggered 2000 proposed staggered 3000

5-masks conv. staggered 4-masks prop. staggered conv. co-planar

Drain current (A)

Gate voltage(V) L=3 um; W=5 um; Vd= 5 V

Drain current(A)

Gate voltage(V)

5-masks conv. staggered 4-masks prop. staggered conv. co-planar

L=3 um; W=10 um; Vd= 5 V

5-masks conv. staggered 4-masks prop. staggered conv. co-planar

D rain c u rr ent (A )

Gate voltage(V) L=15 um; W=5 um; Vd= 5 V

Drai n current (A)

Gate voltage(V) L=15 um; W=10 um; Vd= 5 V

5-masks conv. staggered 4-masks prop. staggered conv. co-planar

S D W _s,d

L I _ch W _ch