Future work

We have proposed a novel low-temperature poly-Si TFTs with a thicker source/drain region and wider channel to improve the conventional low-temperature poly-Si TFTs performance. In order to further improve electrical properties of our devices, there will be still some works worth of being investigated.

In our experiment, the minimum leakage current of the proposed structures was increased due to large number of the grain boundary traps near the drain region existence. It is well known that NH3 or H2 plasma could significantly reduce the grain boundary traps due to the formation of S≣N and S-H bonds [18]. In addition, we also can establish the drain current model of the test structure with wider channel region.

Reference

[1] T.Serilawa, S.shirai, A. Okamoto, and S. Suyama, “Low-temperature fabrication of high-mobility Poly-Si TFTs for large-area LCD’s,” IEEE Trans. Electron Dev., vol. 36, no. 9, pp. 1929,1989.

[2] J. R. Ayres and N. D. Young, “Hot carrier effects in devices and circuits formed from poly-Si,” IEEE proc. Circuits Devices Syst., vol. 131, no. 1, p.38, 1994.

[3]S.D Brotherton, “Topical review：Polycrystalline silicon thin film transistors,”

Sci.Technoi., vol.10, pp721-738, 1995.

[4] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider,

“Conductivity behavior in polycrystalline semiconductor thin film transistors,” J.

Appl. Phys. Vol. 53, pp.1193-1202, 1982

[5] P. Migliorato, C. Reita, G. Tallatida, M. Quinn and G. Fortunato, “Anomalous off-current mechanisms in n-channel poly-Si thin film transistors.”

Solid-State-Electronics, Vol.38, pp.2075-2079, 1995

[6] M. Hack, I-W. Wu, T. H. King and A. G. Lewis, “Analysis of Leakage Currents in Poly-silicon Thin Film Transistors,” IEDM Tech. Dig., vol. 93, pp. 385-387, 1993 [7] Byung-Hyuk Min and Jerzy Kanicki, “Electrical characteristics of new LDD

poly-Si TFT structure tolerant to process misalignment,” IEEE Electron Device Lett., vol. 20, pp. 335-337, 1999

[8] Shengdong Zhang, Ruqi Han, and Mansun J. Chan, “A novel self-aligned bottom gate poly-Si TFT with in-situ LDD,” IEEE Electron Devices Lett., vol. 22, pp.

393-395, 2001.

[9] A. Kumar K.P. and J. K. O Sin, “Influence of lateral electric field on the

anomalous leakage current in polysilicon TFT,” IEEE Electron Device Lett, vol.

20, pp.27-29, 1999

[10]K.R.Olasupo and M.K.Hatalis, “Leakage current mechanism in sub-micron polysilicon Thin-Film Transistors,” IEEE Trans. Electron Device, vol. 43, no.8, pp.1218-1223, 1996

[11] S. M. Sze, Physics of Semiconductor Devices, 2^nd ed., Taiwan: John Wiley &

Sons, 1981, pp. 433-448.

[12] Gi-Young Yang, Sung-Hoi Hur, and Chul-Hi Han, “A Physical-Based Analytical Turn-On Model of Polysilicon Thin-Film Transistors for Circuit Simulation,”

IEEE Trans. Electron Devices, vol.46, no.1, pp.165-172, Jan. 1999.

[13] Hsin-Li Chen and Ching-Yuan Wu, “A New I-V Model Considering the Impact-Ionization Effect Initiated by the DIGBL Current for the Intrinsic n-Channel Poly-Si TFT’s,” IEEE Electron Device Letters, vol. 46, no. 4, pp.

772-728, Apr. 1999.

[14] Peyman Servati, and Arokia Nathan, “Modeling of the Reverse Characteristics of a-Si:H TFTs,” IEEE Trans. Electron Devices, vol.49, no.5, pp.812-819, May.

2002.

[15] Horng Nan Chern, Chung Len Lee, and Tan Fu Lei, “An Analytical Model for the Above-Threshold Characteristics of Polysilicon Thin-Film Transistors,” IEEE Trans. Electron Devices, vol.42, no.7, pp.1240-1246, Jul. 1995.

[16] Filippos V. Farmakis, Jean Brini, George Kamarions, Constantinos T. Angelis, Charalambos A. Dimitriadis, and M. Miyasaka, “On-Current Modeling of Large-Grain Polycrystalline Silicon Thin-Film Transistors,” IEEE Trans.

Electron Devices, vol.48, no.4, pp.701-706, Apr. 2001.

[17] Ching-Wei Lin; Li-Jing Cheng; Yin-Lung Lu; Yih-Shing Lee; Huang-Chung Cheng , “High-performance low-temperature poly-Si TFTs crystallized by excimer laser irradiation with recessed-channel structure,” IEEE Electron Device Letters, vol.22, pp. 269 – 271, 2001

[18] W. Wu, W. B. Jackson, T. Y. Huang, A. G. Lewis, and A. C. Chiang,

“Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation,” IEEE Electron Device Lett., vol. 12, no. 5, pp. 181–183, May 1991

Table 1

off-state current 7.6×10^-12 1.07×10^-11 1.9×10^-11 The leakage

current (Vgs = -15 V)

1.26×10^-7 4.06×10^-8 3.07×10^-8

On/Off ratio 1.2×10⁷ 1.07×10⁷ 8.95×10⁶

Table 1： Compared with the maximum on-state current (V_gs = 30 V), the minimum off-state current and the leakage current (V_gs = -15 V ). The channel length (L_ch) is 3 μm, S/D width (W) is 5μm, and drain voltage ( V_ds ) is 5 V.

on-state current 1.97×10^-4 2.06×10^-4 2.65×10^-4 The minimum

off-state current 1.33×10^-11 1.69×10^-11 2.44×10^-11 The leakage

current

（V_gs = -15 V）

3.7×10^-7 5.2×10^-8 6.2×10^-8

On/Off ratio 1.48×10⁷ 1.19×10⁷ 1.1×10⁷

Table 2： Compared with the maximum on-state current (Vgs = 30 V), the minimum off-state current and the leakage current (Vgs = -15 V ). The channel length (Lch) is 3 μm, S/D width (W) is 10μm, and drain voltage ( Vds ) is 5 V.

Table 3

on-state current 2.7×10^-5 2.56×10^-5 6.3×10^-5 The minimum

off-state current 2.6×10^-12 5.1×10^-12 8.57×10^-12 The leakage

current

（Vgs = -15 V）

1.9×10^-7 2.8×10^-8 1.8×10^-8

On/Off ratio 1.04×10⁷ 5.02×10⁶ 7.35×10⁶

Table 3： Compared with the maximum on-state current (Vgs = 30 V), the minimum off-state current and the leakage current (Vgs = -15 V ). The channel length (Lch) is 15 μm, S/D width (W) is 5μm, and drain voltage ( Vds ) is 5 V.

on-state current 5.06×10^-5 5×10^-5 8.73×10^-5 The minimum

off-state current 3.94×10^-12 5.98×10^-12 9.8×10^-12 The leakage

current

（V_gs = -15 V）

2.5×10^-7 5.2×10^-8 3.55×10^-8

On/Off ratio 1.28×10⁷ 8.36×10⁶ 8.91×10⁶

Table 4： Compared with the maximum on-state current (V_gs = 30 V), the minimum off-state current and the leakage current (V_gs = -15 V ). The channel length (L_ch) is 15 μm, S/D width (W) is 10μm, and drain voltage ( V_ds ) is 5 V.

Region I: main channel Region II: side channel

Figure 2.1(a) Top view of the test structure

S D W _s,d

L I _ch W _ch

Figure 2.1(b) Top view of the conventional structure

Figure 2.2 (a) The current flow lines of 2-D numerical simulator

structure with Lch = 3μm , Wsd = 5μm.

MEDICI simulation for the conventional structure. (b) The current flow lines of 2-D numerical simulator MEDICI simulation for the test

Figure 2.2 (c) The current flow lines of 2-D numerical simulator MEDICI simulation for the test structure with L_ch = 10μm , W_sd = 5μ m.(d) The current flow lines of 2-D numerical simulator MEDICI simulation for the test structure with Lch = 10μm , Wsd = 10μm.

-10 0 10 20 30 10^-11

10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4

Lch=5

μ

m; Wsd=5

μ

m; Vd=5V

ΔWch=0

μ

m ΔWch=2

μ

m ΔWch=4

μ

m ΔWch=6

μ

m ΔWch=14

μ

m

Drain current,Id(A)

Gate Voltage,Vg(V)

Figure 2.3(a) ID-VG curve with different △Wch

20 30 2x10^-5

4x10^-5 6x10^-5 8x10^-5 10^-4

Lch=5

μ

m; Wsd=5

μ

m; Vd=5V

ΔWch=0

μ

m ΔWch=2

μ

m ΔWch=4

μ

m ΔWch=6

μ

m ΔWch=14

μ

m

Drain current,Id(A)

Gate Voltage,Vg(V)

Figure 2.3(b) ID-VG curve with different △Wch

-10 0 10 20 30 10^-11

10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4

ΔWch=0

μ

m ΔWch=2

μ

^m

ΔWch=4

μ

m ΔWch=6

μ

m ΔWch=14

μ

^m

Drain current,Id(A)

Gate Voltage,Vg(V) Lch=5

μ

^{m; Wsd=10}

μ

^{m; Vd=5V}

Figure 2.3(c) ID-VG curve with different △Wch

20 30 5x10^-5

10^-4 1.5x10^-4 2x10^-4 2.5x10^-4 3x10^-4

Δ

Wch=0 μ m

Δ

Wch=2 μ m

Δ

Wch=4 μ m

Δ

Wch=6 μ m

Δ

Wch=14 μ m

Drain cur rent ,I d(A)

Gate Voltage,Vg(V) Lch=5 μ m; Wsd=10 μ m; Vd=5V

Figure 2.3(d) ID-VG curve with different △Wch

-2 0 2 4 6 8 10 12 14 16 18 20

-2 0 2 4 6 8 10 12 14 16 18 20 and V_gs = 30 V for different channel length

-2 0 2 4 6 8 10 12 14 16 18 20 and V_gs = 30 V for different channel length

-2 0 2 4 6 8 10 12 14 16

-2 0 2 4 6 8 10 12 14 16

min. off state current max. on state current

Leakage current (pA)

Figure 2.7(a) the maximum drain current and minimum of-state current virus △Wch at Wsd = 5 μm, Vds = 5 V for channel length is 15 μm

Figure 3.1 The critical five-lithography fabrication procedures

Figure 3.2 The critical four-lithography fabrication procedures

Figure 3.3(a) Top view of the proposed staggered structure

G

Figure3.3 (b) the cross-section view of the AB line

-10 0 10 20 30 10^-11

10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4

Drain current (A )

Gate voltage(V) L=3 um; W=5 um; Vd= 5 V

proposed staggered 1000 proposed staggered 2000 proposed staggered 3000

Figure 3.4 I_D - V_G curve for L_ch = 3 μm, W = 5 μm and V_d = 5 V for different S/D width (100 nm , 200 nm ,300 nm )

-10 0 10 20 30 10^-11

10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4

Gate voltage(V)

Dr ain cur rent (A)

L=3 um; W=10 um; Vd= 5 V

proposed staggered 1000 proposed staggered 2000 proposed staggered 3000

Figure 3.5 I_D - V_G curve for L_ch = 3 μm, W = 10 μm and V_d = 5 V for different S/D width (100 nm , 200 nm ,300 nm )

-10 0 10 20 30 10^-12

10^-11 10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4

L=15 um; W=5 um; Vd= 5 V

Drain current (A)

Gate voltage(V)

proposed staggered 1000 proposed staggered 2000 proposed staggered 3000

Figure 3.6 I_D - V_G curve for L_ch = 15μm, W = 5μm and V_d = 5 V for different S/D width (100 nm , 200 nm ,300 nm )

-10 0 10 20 30 10^-11

10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4

Dr ai n c u rr ent (A )

Gate voltage(V) L=15 um; W=10 um; Vd= 5 V

proposed staggered 1000 proposed staggered 2000 proposed staggered 3000

Figure 3.7 I_D - V_G curve for L_ch = 15 μm, W = 10 μm and V_d = 5 V for different S/D width (100 nm , 200 nm ,300 nm )

-10 0 10 20 30 10^-11

10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4 10^-3

5-masks conv. staggered 4-masks prop. staggered conv. co-planar

Drain current (A)

Gate voltage(V) L=3 um; W=5 um; Vd= 5 V

Figure 3.8 I_D - V_G curve for L_ch = 3μm, W = 5μm and V_d = 5 V for the proposed staggered structure, conventional staggered structure and conventional co-planar structure.

-10 0 10 20 30 10^-11

10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4 10^-3

Drain current(A)

Gate voltage(V)

5-masks conv. staggered 4-masks prop. staggered conv. co-planar

L=3 um; W=10 um; Vd= 5 V

Figure 3.9 I_D - V_G curve for L_ch = 3 μm, W = 10 μm and V_d = 5 V for the proposed staggered structure, conventional staggered structure and conventional co-planar structure

-10 0 10 20 30 10^-12

10^-11 10^-10 10^-9 10^-8 10^-7 10^-6 10^-5

5-masks conv. staggered 4-masks prop. staggered conv. co-planar

D rain c u rr ent (A )

Gate voltage(V) L=15 um; W=5 um; Vd= 5 V

Figure 3.10 I_D - V_G curve for L_ch = 15 μm, W = 5 μm and V_d = 5 V for the proposed staggered structure, conventional staggered structure and conventional co-planar structure

-10 0 10 20 30 10^-12

10^-11 10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4

Drai n current (A)

Gate voltage(V) L=15 um; W=10 um; Vd= 5 V

5-masks conv. staggered 4-masks prop. staggered conv. co-planar

Figure 3.11 I_D - V_G curve for L_ch = 15 μm, W = 10 μm and V_d = 5 V for the proposed staggered structure, conventional staggered structure and conventional co-planar structure

簡歷

姓 名：陳正國

性 別：男

出生日期：民國 70 年 3 月 5 日

出 生 地：台灣省新竹市

住 址：彰化縣員林鎮東和里員水路二段 566 巷 26 弄 8 號

學 歷：台中市國立台中一中(民國 85 年 9 月~88 年 6 月)

國立成功大學物理學系(民國 88 年 9 月~92 年 6 月)

國立交通大學電子工程所碩士班(民國 92 年 9 月~95 年 8 月)

碩士論文：具有較厚源/汲極與較寬通道的多晶矽薄膜電晶體的模擬與電性分析

The Simulations and Analysis of The Poly-Si Thin Film Transistor with Thicker S/D and wider Channel

在文檔中 具有較厚源/汲極與較寬通道的多晶矽薄膜電晶體的模擬與電性分析 (頁 25-57)