A radio-frequency to DC voltage converter (RFVC) is designed and implemented in 0.18 μm CMOS technology. By using proposed mechanism, the input RF signal could be direct- converted to output DC voltage without frequency down- conversion and division. From measurement result, with input signal from 1 GHz to 5 GHz, the output DC voltage is from 0.215 mV to 1.42 mV. And the dynamic range is from -7 dBm to 5 dBm. This work is suitable for RF direct FSK demodulation.
Chapter 4
Wideband Delay Circuit for Time Array System
4.1 Introduction
In the modern communication system, the trend will aim to beam-forming system integration. The main methods of implementation are time array and phase array. The most important circuit block of time array system is time delay circuit, and the block diagram is shown in Fig. 4-1. The design goals of this wideband time delay circuit are the extension of operating bandwidth and reduction of circuit area.
This chapter is organized as follows. In Section 4-2, the circuit design is described.
The measurement results are summarized in Section 4-3. Finally, a conclusion is given in Section 4-4.
LNA
Time Delay
LNA
Time Delay
LNA
Time Delay
LNA
Time Delay
Fig. 4-1 The block diagram of time array receiver
4.2 Circuit Design
The ideal time delay circuit essentially exhibits an all-pass filter response with unit gain in the magnitude and a constant group delay over the operation frequency. The transfer function of such a system can be expressed as an exponential functionH(s)=e−std for a group delay of td. A method for implementation is using Padé approximant [9]. Mathematically, H(s) can be approximately expressed as the first-order and the second-order forms, respectively, as
(7)
The group delay time of the transfer function is defined as the negative differentiation of the phase response. Using (7), the group delay of the 1st-order and 2nd-order APF can be derived, respectively, as
2
The natural frequency ω0, defined as 1/td, is introduced for convenience. The group delay remains constant when the operation frequency is smaller than the natural frequency. As the frequency increases, it exhibits dispersion. Fig. 4-2 shows the group delay of the 1st-order and 2nd-order functions (Q=1/√3 for maximum flat delay
bandwidth in the 2nd-order function) for the delay of 50 psec. The higher-order transfer function gives a wider delay bandwidth.
0 2 4 6 8 10 12
Fig. 4-2 Frequency dispersion of the group delay of the transfer functions with different Padé approximants.
Fig. 4-3. The schematic of proposed wideband delay circuit.
The implementation of the 2nd-order transfer function in a single stage is chosen in this work. Fig. 4-3 shows the schematic of the proposed wideband delay circuit. This circuit is composed of a differential pair M1-M2, two common-gate cascode stages M3-M6 and two common gate amplifiers M7-M8. Actually the circuit implementation is considered by rewriting the 2nd-order all-pass transfer function in two terms as
2
The first term is unit gain, and the second term represents a transfer function of a band-pass filter. In the proposed circuit, M1 and M2 give a constant gain as the first term, and the path through M3-M6 yields to the band-pass response. The signals of two paths are summed up at the drain of M1-M2 in the current domain.
When the summed up current runs through the load, the intrinsic capacitor from the transistors and the loading effect from the next stage give an extra low-pass response to the transfer function. This non-ideal effect will introduce extra group delay and delay dispersion to the entire circuit performance. Even though the inductance peaking technique used in [10] can compensate for delay dispersion, the group delay tends to be sensitive to the resulted overshooting.
In order to alleviate the issue, two common-gate transistors M7-M8 are added as a buffer stage, rather than as the inductive loading. The output impedance can also introduce inductance peaking by adding resistor Rb on the gate side of M7 and M8.
This inductance peaking introduces a farther zero compare to that in [10], yielding to a larger bandwidth of group delay. The summed current finally goes through M7-M8 to the load RL, providing unit gain buffering of all-pass response. Rc at the input is for input matching purpose.
Limited by the Q value on the band-pass path, the maximum Q value of the entire circuit is 0.5 (in Eq. (3)), which results in the equivalent performance of two cascaded 1st-order delay circuits. The transfer function of the delay circuit can be derived as
2
where Z1 is the equivalent impedance of Ra parallelto the transconductance of M3., and Z2 is the source impedance observed from M4 and M6. The product of capacitance and transconductance determines the resulted time delay.
4.3 Measurement results of Wideband Time Delay Circuit
Fig. 4-4. Die micrograph. The core circuit occupies the area of 320×160 μm2.
Fig. 4-5. The measured S-parameters.
Fig. 4-6. The measured group delay. Fig. 4-7. The measured P1dB versus input frequency.
The proposed wideband time-delay circuit is designed and fabricated in 0.18 μm CMOS technology. Both input and output ports are differential. Fig. 4-4 shows the die micrograph. The core circuit occupies the area of 320×160μm2. The total chip size is 520×820 μm2. The DC power consumption of core circuit and buffer are 7.88 mW and 8.91 mW from 1.8 V power supply, respectively.
The measurement result of S-parameter is shown in Fig. 4-5. The input and output matching return loss are better than 10 dB up to 10 GHz. The loss of proposed time-delay circuit at 1 GHz and 5 GHz are 5.72 dB and 8.93 dB, respectively. Due to the output buffer of a source follower, the gain level of the entire circuit becomes less than 0 dB. This can be recovered in a fully integrated circuit design. Fig. 4-6 shows the measured group delay. At low frequencies, it appears to be flat around 45 psec.
The group delay becomes 37.2 psec at 5 GHz. The linearity performance of the measured P1dB versus input frequency is shown in Fig. 3-7. The worst P1dB is -4.72 dBm at 1 GHz. Since the gain level drops as frequency increases, P1dB increases to be -4 dBm at 5 GHz.
4-4 Conclusions
A wideband 2nd-order delay circuit in 0.18-μm CMOS technology is presented with the features of double delay bandwidth of the 1st-order active all-pass filter. The main principle is to use Padé approximant for all-pass filter design, which has an advantage of smaller chip area from passive delay line.
Chapter 5
High Input Power Range Phase Shifter for Transmitter Array Application
Fig. 5-1. Block diagram of RF-path shifter transmitter array
5.1 Introduction
The other method for beam-forming implementation is phase array system, and the key component is the phase shifter. The block diagram of RF-path shifting phase array transmitter is shown in Fig. 5-1.
In phase shifter design, the technique of I/Q vector combination is widely used in the active scheme. The desired output signal phase can be synthesized by summing a pair of quadrature I and Q input signals, each with an appropriate magnitude. By using two of the four input phases of 0o, 90o, 180o, and 270o, a full range of
360-degree output phase can be achieved. The scheme therefore requires variable gain amplifiers (VGAs) to adjust the magnitude of the I/Q signals to the desired ratio.
The design issue arises from VGA linearity. Although the phase shifting resolution is loose, the shifted phase shall remain constant irrelevant to the signal content.
Consider the complicated modulation technique in modern digital communications normally with high signal peak-to-average ratio (PAR). If the VGA causes nonlinear amplitude distortion, the output phase of the shifter varies along with the modulated signal envelope. The output signal then suffers from the error vector magnitude (EVM) degradation, similar to the AM-to-PM distortion issue in power amplifier design.
The typical implementation of VGA calls for the conFiguration of a differential amplifier, which voltage gain is controlled by the device transconductance, or, in turn, the bias current [11], [12]. Given a bias current setting, the transconductance only remains constant within a limited range of the input signal swing. Since the modulated signal envelope variation could be more than 10 dB, it is critical to permit a large
dynamic range of the input signal swing for a given phase shift. This issue is seldom discussed for phase shifter implementation. For example, if the average phase distortion to signal data symbols were 2°, the phase shifter would cause EVM of -29.14 dB. This degradation would fail conformance requirements in modern communication systems, such as WiMAX.
In this circuit, a phase shifter using modified VGA design is proposed to overcome this issue. The revised schematic improves the linearity of the I/Q vector combiner.
Thus, it improves the accuracy of phase shift.
This chapter is organized as follows. In Section 5.2, the proposed circuit design is described. The chip implement and measurement results are shown in Section 5.3.
Finally, a conclusion is given in Section 5.4.
5.2 Circuit Design
The commonly used VGA design in a phase shifter with I/Q vector combination technique is as shown in Fig. 5-2 [11], [12]. Signal appears in the differential format.
The phase shifter consists of four differential amplifiers in a group of two. Each group amplifies the I or Q signal to the specified output level. Essentially the two input signals in each group are simply phase inversed to each other, yielding to summation or subtraction. Only one signal in each group is amplified and summed up at the output in the current domain. Gain control and input signal selection are realized by tuning the dc bias current to the specified transconductance. By doing so, the output phase covers the full range of 360 degrees.
Fig. 5-2 Block diagram of a conventional I/Q vector combiner phase shifter.
Fig. 5-3 Phase distortion versus input swing of commonly used VGA
The issues of the VGA circuit configuration are twofold. One is the transconductance variation along with the input signal swing. If the input swing becomes large, device nonlinearity causes the effective dc bias to change. Thus the amplifier gain changes correspondingly. The other is the gain variation due to gain tuning in another amplifier pair. In deep submicron devices, the device transconductance varies notably at different VDS bias even if the bias current is fixed.
In this conFiguration, the dc voltage of Vop and Von actually changes if the bias current changes in one transistor pair. The gain level of a transistor pair therefore is affected by gain tuning in another pair.
The reason of narrow input power range of commonly used VGA design is that the
selected DC current is not suitable for wide dynamic input swing. For example, if we choose different bias condition for each gain state of I/Q path under small signal operation, the phase distortion and gain variation of output signal will be extremely low. But these bias conditions are not suitable for large signal operation owing to VGA linearity issue. Nevertheless, the phase shifter on the RF path shall handle both small signal and large signal swings of the modulated signal without phase distortion.
Fig. 5-3 shows the simulated phase distortion of commonly used VGAs. Owing to the linearity of I/Q ac magnitude ratio, if the desired output phase is at 22.5° and 67.5°, the phase distortion will increase to 10 degrees when the input swing is 300 mV.
Fig. 5-4 Schematic of proposed VGA and vector combiner
Fig.5-5 Diagram of phase shift base on I/Q vector combiner 5.2.1 Proposed Variable Gain Amplifier
To solve the phase distortion issue, the VGA circuit is proposed for phase shifter design, as shown in Fig. 4. The circuit takes four-phase input signals. The difference from the traditional phase shifter is gain control, which is implemented by four sets of differential amplifier cells. Each cell is biased with a current source that is digitally controlled by switching ON/OFF. Each set includes gain cells in different device sizes, resulting in weighted output currents for vector combination at the nodes Vop and Von. Since the bias current of each cell is fixed when turn on, the amplifier
transconductance is also fixed, namely, irrelevant to the input voltage swing.
The output phase resolution relies on the gain control to I and Q signals, and in turn on the device size ratio among gain cells.
This concept is similar to the programmable gain amplifier (PGA) in [13]. Fig. 5-5 shows the magnitude ratio of I/Q signals to synthesize the phase resolution of 22.5°
with equal magnitudes. Calculated by arctangent function, the integral I/Q ratio of 0°, 22.5°, 45°, 67.5°, and 90° are 13/0, 12/5, 9/9, 5/12, and 0/13, respectively. The device sizes in a set of gain cells need to be chosen properly. Although binary weighting allows high resolution [6], the sizes of x1, x3, x4, x5 are chosen in this work for minimum hardware implementation. The congenital theoretical phase error and gain variation are 0.12° and 0.092 dB, respectively.
By using proposed schematic of VGA in I/Q vectors combination based phase shifter design, the mechanism of gain tuning only depends on the accuracy of device ratio. The bias condition of each gain cell is fixed in ON state. This is the maximum difference between commonly used VGA and proposed VGA. Based on proposed VGA, the sensitivity of VDS could be reduced. The phase distortion and gain variation of phase shifter will be improved in wide input power range.
5.2.2 Quadrature Phase Generator and Output Buffers
The phase shifter requires quadrature phase input signals. In this design, an RC poly-phase filter (PPF) is adopted to convert a differential input for the purpose. A 100-Ω resistor is also placed in shunt to the input for impedance matching. As such, the PPF introduces significant signal loss. The simulated result shows that the voltage loss of the PPF is 5.75 dB at 3.5 GHz. This voltage loss is subtracted from measurement data in phase shifter gain calculations.
At the phase shifter output, a source follower stage is included as an output buffer for impedance matching for measurement. The voltage loss of the output buffer is 7.5 dB at 3.5 GHz.
5.3 Circuit Implement and Measurement Results
The proposed phase shifter was fabricated using 0.18-μm standard CMOS technology. Fig. 5-6 shows the die photo of this work. The core circuit which includes an RC PPF, VGA and output buffers occupies 793 μm x 280 μm chip area. The total chip size, including testing pads, is 1015 μm x 805 μm.
Fig. 5-7 shows the phase shift versus input power of 16 different phase states at 3.5 GHz. The phase shifter gain at 3.5 GHz is shown in Fig. 5-8. The averaged gain of the proposed phase shifter, including VGA, and output buffer, is about -12.47 dB. The measured phase distortion versus input power is shown in Fig. 5-9. In this work, by using the proposed VGA, the gain variation is below 1.5 dB and phase distortion is small than ±2°. The frequency responses of the phase shift and gain are shown in Fig.
5-10 and Fig. 5-11. The values of the phase error and gain variation increase with the frequency offset to the corner frequency of PPF. The maximum phase error and gain variation are 5° and 2 dB in the operating frequency band from 3 GHz to 4 GHz.
Owing to the operated mechanism of proposed VGA, the DC dissipations of 16 phase states are not equally. With 1.8 V supply voltage, the maximum the minimum power dissipation are 21.27 mW and 15.46 mW, respectively. The output buffers consumes 15.62 mW from 1.8 V supply. The power consumption depended on the transconductance of active device, if the advance technology could be used in this design, the power consumption could be reduced. The performance summary and comparison is shown in Table 1.
Fig. 5-6 Chip photo Fig. 5-7 Phase shift versus input power
Fig. 5-8 Gain versus input power Fig. 5-9 Phase distortion versus input power
Fig. 5-10 Phase shift versus input frequency
Fig. 5-11 Gain versus input frequency
5.4 Conclusion
A 3.5 GHz high dynamic input power range phase shifter in 0.18-μm CMOS technology is designed and implemented in this work. With proposed schematic of VGA, the dynamic of input power of gain variation and phase error could be improved.
From measurement results, when the input power range was swept from -33 dBm to 7 dBm, the phase distortion and gain variation versus input power of proposed phase shifter are smaller than ±2° and 1.5 dB, respectively. This circuit is suitable for wide dynamic input power range and high accuracy of phase and gain application.
Chapter 6 Conclusions and Future Works
6.1 Conclusions
In this report, the circuit blocks for wideband frequency operation and beam-forming system are designed and implemented. From the measurement result, the design targets have been achieved.
A 1.27-5.31 GHz wideband, high linearity balun LNA is suitable for the first stage design in receiver chain, and the 3-5.7 GHz frequency tripler is also suitable for wideband LO source generator.
Otherwise, for FSK demodulation requirement, a direct radio-frequency to DC voltage converter is developed and implemented. The wideband LO signal source is not necessary demand in this FSK demodulator, so the design complexity, and chip size will has a significant reduction.
For beam-forming system design, the 3 dB bandwidth of proposed wideband delay circuit is extended to 4.38 GHz without any inductor peaking which will reduce silicon area. This circuit has a great potential for fully time array system integration.
In phase shifter design, the wide input dynamic range requirement is solved by proposed method. This circuit is also suitable to phase array transmitter integration.
These works are also presented in Mater Theses [14], [15] of National Chiao-Tung University.
6.2 Future Work
The design techniques of most critical circuit blocks for wide frequency band operation and beam-forming system have been developed. The further progress is the integration of fully system.
For Chapter 2, the down conversion mixer, IF amplifier and a frequency synthesizer could be integrated with proposed LNA and frequency tripler. And then, the wideband receiver will be implemented.
For Chapter 3, the wideband LNA which is developed in Chapter 2 could be reused an integrated with proposed RFVC. The direct FSK demodulator could be demonstrated.
Finally, for future communication systems, the most important circuits which are time delay circuit and phase shifter should be integrated in beam-forming receiver and transmitters.
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