Chapter 2 Experiments
2.1 Procedure of Fabrication of LTPS TFTs
LTPS TFTs used in the experiment were the conventional top-gate structure and fabricated on glass substrates. The process flow of TFTs is described below. First, the buffer oxide and 50 nm thick a-Si:H films were deposited on glass substrates with plasma-enhanced chemical vapor deposition (PECVD). The samples were then put into the oven for dehydrogenation. The XeCl excimer laser of wavelength 308 nm and energy density of 400 mJ/cm2 was applied to scan the a-Si:H film with the beam width of 4 mm and 98 % overlap to recrystallize the a-Si:H film to poly-Si. After poly-Si active area definition, 80 nm SiO2 and 40 nm SiNx films were deposited with PECVD as the gate insulator. Next, the metal gate was formed by sputter and then defined. The lightly doped drain (LDD) and the n+ source/drain doping were formed by PH 3
implantation with dosage 2×1013 and 2×1015 cm2 of PH3, respectively. The LDD implantation was self-aligned and the n+ regions were defined with a separate mask.
Then the interlayer of SiNx was deposited. Subsequently, the rapid thermal annealing was conducted to activate the dopants. Meanwhile, the poly-Si film was hydrogenated.
Finally, the contact holes formation and metallization were performed to complete the fabrication work.
In this study, N-type TFTs with a channel width of 20 µm and a channel length of 5 µm with an LDD structure of length 1.2 µm are fabricated. Figure 2-1 shows the cross-section structure of the N-type poly-Si TFT with LDD.
n+ n+
Glass substrate buffer oxide
interlayer metal
Gate
n-
n-insulator
Fig. 2-1 The cross-section view of N-type LTPS TFT with LDD structure
2.2 Extraction of Device Electrical Parameters
Here, we will introduce the methods of the typical electrical parameter extraction, including threshold voltage (Vth), field-effect mobility (µFE), subthreshold swing (SS).
Determination of the Threshold Voltage (Vth)
For most of the researches on TFT, the constant current method is widely-used to determine the threshold voltage (
V
th). In this thesis, the Vth is determined by this method, which extracts the rated current (IDt) from the drain current curve. Thus, the corresponding voltage is the threshold voltage of the constant current. In general, the rated current is defined asL I W
IDt = DN (2-1) where IDN is normalized drain current, i.e. threshold current. Typically, the threshold current is specified as 10 nA for |VDS| =0.1 V and 100 nA for. |VDS| =10 V.
Determination of the Field Effect Mobility (µFE)
The transfer characteristics of poly-Si TFTs are similar to those of conventional MOSFETs. The MOSFETs can be applied to the poly-Si TFTs, so the first order I-V relation in the bulk Si. The field effect mobility (Mu, µFE) is derived from the maximum value of the transconductance (gm), which can be expressed as
( ) where Cox is the gate capacitance per unit area, W is channel width, L is channel length, Vth is the threshold voltage. If the drain voltage (VD) is much smaller as compared with
G th
V −V , i.e. VD <<(VG −Vth) , and VG >Vth then the drain current can be approximated as
D From the above equation, the gm can be obtained,
D
Therefore, the field effect mobility with Eq. (2-4) can be rewritten as
m
In other words, the field-effect mobility can be extracted by taking the maximum value of the gm into (2-5) when VD = 0.1 V.
Determination of the Subthreshold Swing (S.S)
When the gate voltage (Vg) is below the threshold voltage (Vth) and the channel of poly-Si appears weak inversion or depletion, the corresponding drain current is called the sub-threshold current. The subthreshold region tells how sharply the current drops with gate bias. In general, the subthreshold current is exponentially dependent on
G th
V −V , so the subthreshold swing (S.S) is used for observing the characteristic of turning on and turning off about the TFT. It can be shown that the expression for S.S is given by
2.3 Stress Conditions
The Agilent 4156A precise semiconductor parameter analyzer with HP 41501B pulse generator was used to measure the I-V curve and stress the device with different conditions, respectively. The AC pulse voltage was performed on the gate electrode as the dynamic stress and the drain DC bias was applied with grounding source, which is shown in Fig.2-2. Regarding standard stress conditions, we used a rectangular pulse with amplitude of +15 V, duty ratio of 50 %, and frequency of 500 kHz, and both the rising time (Tr) and falling time (Tf) were fixed in 100 ns as shown in Fig.2-3.
Furthermore, the drain bias and source were +15V and grounded respectively. The basic parameters of AC signal include frequency (F), i.e. the reciprocal of period (T), signal high level (Vgh), signal low level (Vgl), high-level time (T_vgh), low-level time (T_vgl), rising time (Tr), and falling time (Tf). Here, the definition of individual parameter is given as follows:
T = Tr + T_vgh + Tf + T_vgl (2-7)
F = 1 / T (2-8)
Duty ratio = ( Tr + T_vgh ) / T (2-9)
Fig. 2-3 Waveform and definition of the AC signal
In the beginning, Vd is changed from 0 V to 20 V as listed in Table 2-1. With the increase in drain bias, the stress condition is observed to result in the significant degradation. Therefore, to investigate which parameter of the stress pulse dominates the degradation of the n-type Poly-Si TFTs, we measured the various experiment results including the effects of pulse frequency, transient time, gate pulse range, and duty ratio.
Table 2-1 Experiment conditions of drain bias
Stress Conditions Experiment
Gate Pulse Drain Bias Frequency Duty Ratio Stress time
Drain Bias Vg=0~15V Vd=0、、、、5、、、、
10、、、、15、、、、20V 500kHz 50% 100s
First, we change frequency of gate pulse from 5 kHz to 500 kHz for the gate pulse repetition study. The conditions are listed in table 2-2.
Table 2-2 Experiment conditions of pulse repetitions
Stress Conditions
ExperimentGate Pulse Drain Bias Frequency Duty Ratio Stress time
Pulse Repetition Vg=0~15V Vd=15V
5kHz degradation of the device is examined. Here, the Tr and Tf from 100 ns to 700 ns are changed. Meanwhile, the duration of signal high-level (T_Vgh) and signal low-level (T_Vgl) are fixed as 900 ns. The experiment conditions are listed in Table 2-3.
Table 2-3 Experiment conditions of transient time (T_Vgh = TVgl = 900ns)
Stress Conditions
Experiment
Gate Pulse Drain Bias Rising Time Falling Time Pulse Period
Pulse
Subsequently, in order to compare the effects of gate pulse in different range, we classified the swing ranges of gate pulse into two categories. Namely, fixed low gate voltage Vgl of 0 V, and fixed high gate voltage Vgh of 15 V. To clarify the effect of the pulse level for the degradation dependence, the stress conditions of various Vg levels with fixed pulse swing are examined and are further distinguished according to the
duty ratio. Finally, we examine the dependence of degradation on DC offset of the gate pulse under various pulse ranges and duty ratios. The experiment conditions are summarized in Table 2-4.
Table 2-4 Experiment conditions of various pulse ranges and duty ratios Stress Conditions
Experiment
Gate Pulse Drain Bias Frequency Duty Ratio Stress time
Vg=0~5、、、10、、 、、、
Chapter 3 Results and Discussion
In previous research, Uraoka et al. proposed that the degradation of N-type poly-Si TFTs under gate AC operation as source and drain were grounded increases obviously with the variation of amplitude in the OFF region, as shown in Fig. 3-1 [3.1].
In the ON region, the degradation is negligible. However, with drain bias, the stress condition for gate AC operation is more similar to the actual switching operation that occurs in real panel. In order to further understand the phenomena, the degradation of N-type poly-Si TFTs under gate ON region AC stress with drain bias will be described and discussed in this chapter.
Fig. 3-1 Dependence of degradation on swing region of AC operation as source and drain were grounded
3.1 Degradation of the Transfer Characteristics
Figure 3-2 shows the transfer characteristics and extracted mobility for the N-type poly-Si TFTs before and after 100 s stress under gate pulse of 0~15 V with various drain bias (Vd) from 0 V to 20 V. The drain voltage used in the measurement was 0.1 V.
It is observed that devices remain almost unchanged in the subthreshold region.
However, the changes of the mobility curve and the decrease of ON-current are relatively obvious in this case. The dependence of mobility degradation at various Vd is shown in Fig. 3-3. The mobility degradation is expressed by the ratio of degraded mobility (MuS) to the initial mobility (Mu0). It must be noted that the degradation is significantly accelerated on Vd of 15 V and 20 V.
Therefore, we can recognize from the result that the degradation of N-type poly-Si TFTs under gate AC operation in the ON region with drain bias is important. To obviously demonstrate the degradation in the case, the drain bias for the other experiment conditions is set to be 15 V.
-10 -5 0 5 10 15 20
Fig. 3-2 The transfer characteristics and the extracted mobility before and after 100s stress under gate pulse of 0~15 V with various Vd
0 5 10 15 20
Fig. 3-3 Dependence of mobility degradation on various Vd with gate pulse stress of 0~15V
3.2 Dependence on the Number of Gate Pulse Repetition
Under gate AC pulse with various frequencies and fixed Vd of 15 V, the time dependence of the device degradation is shown in Fig. 3-4. Degradation is enhanced with the increase in frequency. And the degradation is changed violently in a shorter period of stress beginning for higher frequency. It occurs to us that the larger switching numbers take place in high frequency stress. Therefore, the number of the pulse repetition can be suggested as a reason for the degradation.
Then, the time dependence of the degradation for various frequencies is re-plotted as the repetition number dependence as shown in Fig. 3-5. The relationship between the degradation and the repetition number of the pulse is almost universal, and it is not apparently dependent on the frequency. As the slight degradation shift in the same number of repetition, we regard it as a consequence of the device variation. Since the degradation closely correlates with the number of gate pulse repetition, it is necessary to further investigate the transient effect. In the next section, the experiment conditions with various rising time and falling time will be performed.
0 200 400 600 800 1000
Fig. 3-4 Time dependence of degradation under gate AC pulse with various frequencies and fixed Vd of 15V
1000000 1E7 1E8 1E9
Fig. 3-5 Dependence of degradation on the repetition number of the gate AC pulse with fixed Vd of 15V
Universal Curve
3.3 Effect of the Transient Time
In this section, we would like to investigate the effect of the transient time for the device degradation under ON region gate AC operation with drain bias. Here, we examine the transient time dependence for the degradation at fixed number of the pulse repetition. Because the duration of signal high-level (T_Vgh) and signal low-level (T_Vgl) are set the same as 900 ns. Therefore, as various stress conditions are set, the frequency could vary and the period (T) is about 2 ~ 2.6 us as illustrated in Fig. 3-6.
The experiment conditions are listed in Table 3-1.
Fig. 3-6 The various transient time of the gate pulse with fixed duration of Vgh and Vgl
Table 3-1 Experiment conditions of transient time (T_Vgh = TVgl = 900ns)
Stress Conditions
Experiment
Gate Pulse Drain Bias Rising Time Falling Time Pulse Period
Pulse
For those stress conditions with the rising time Tr from 100 ns to 700 ns at a fixed falling time Tf of 100 ns, no significant change in mobility degradation ratio (MuS/ Mu0) is observed as shown in Fig. 3-7(a). Similarly, the degradation of the device has no obvious difference when we change the falling time Tf from 100 ns to 700 ns as shown in Fig. 3-7(b).
Based on the results of the pulse repetition number dependence and the pulse transient time dependence, we suggest that the degradation occurs mainly owing to the swing range of the gate pulse repetition. Therefore, the degradation behavior of the gate pulse range is interesting to be examined. Then, we measure different gate pulse ranges for the stress to validate the assumption in the next section.
0 100 200 300 400 500 600 700 800
Fig. 3-7(a) Rising time dependence of the mobility degradation for AC stress with Vg of 0~15V and fixed Vd of 15V
Fig. 3-7(b) Falling time dependence of the mobility degradation for AC stress with Vg of 0~15V and fixed Vd of 15V
3.4 Dependence on Gate Pulse Profile 3.4.1 Pulse Range
To investigate which range in gate voltage of the stress pulse dominates the degradation of the N-type poly-Si TFTs in the ON operation, the swing range is separated into two; one is the high-level range, and the other is the low-level range. We modulated the pulse swing by fixing the start voltages to the low-level and high-level of the gate pulse as shown in Fig. 3-8(a) and (b). Finally, we set the pulse swing fixed with different Vg level to further estimate the pulse range dependence for the degradation. The duty ratio and frequency of the gate pulse are 50 % and 500 kHz, respectively. In this section, we will present the experimental phenomena and discuss the degradation of the devices under various pulse range stress.
Fig. 3-8(a) The various high-levels of the gate pulse with fixed low-level voltage
Fig. 3-8(b) The various low-levels of the gate pulse with fixed high-level voltage
3.4.1.1 High-Level of the Gate Pulse
The AC stress conditions with various high-levels of the gate pulse (Vgh) are illustrated in Fig.3-8(a). The low-level of the gate pulse (Vgl) is fixed at 0 V while Vgh varies from 5 V to 20 V. The dependence of mobility degradation on various Vgh stress is shown in Fig. 3-9. It is observed that the degradation increases with the decrease in Vg swing. The result obtained is contrary to our expectation. It is presumed that the device degradation would be enhanced as the Vg swing increases. As mention in section 1.2.1, with the increase in gate voltage, the power dissipation in the device is becoming high. The power dissipation causes the increase of device temperature due to Joule heat, which is known as self-heating or thermal effect. The degradation features of self-heating effect are increase in the amount of
V
th shift and S.S change. In view of this, the degradation dependences ofV
th shift and S.S change are shown in Fig. 3-10(a) and (b).0 5 10 15 20
0.0 0.2 0.4 0.6 0.8 1.0
Vg High Level (V) M u
S/ M u
0Vg=0~5V Vg=0~10V Vg=0~15V Vg=0~20V
Fig. 3-9 Dependence of mobility degradation on various Vgh stress
0 5 10 15 20
Fig. 3-10(a) Dependence of Vth shift on various Vgh stress
0 5 10 15 20
Fig. 3-10(b) Dependence of S.S change on various Vgh stress
With the increase in Vg swing, no significant change is observed on S.S change.
However, the
V
th shift is slightly increased for stress conditions of various Vgh. In the case of AC stress, these results lead us to the suggestion that the degradation is dominated by the lower Vg level. Therefore, the degradation caused by lower Vg level will be examined in detail later.3.4.1.2 Low-Level of the Gate Pulse
To further evidence the lower Vg level is the dominant cause of degradation. The AC stress conditions with various Vgl are performed as illustrated in Fig.3-8(b). The Vgh is fixed at 15 V while Vgl varies from 0 V to 10 V. Figure 3-11 shows the dependence of degradation on Vgl stress. It is observed that the mobility degradation is the worst as Vgl is between 0 V and 5 V, which are around the threshold voltage (Vth) of the device. On the other hand, the mobility is relatively less degraded for the gate voltage swinging between 10 V and 15 V.
0 2 4 6 8 10
0.0 0.2 0.4 0.6 0.8 1.0
Vg Low Level (V)
Mu S / Mu 0Vg=0~15V Vg=2~15V Vg=5~15V Vg=10~15V
Fig. 3-11 Dependence of mobility degradation on various Vgl stress
The
V
th shift is obviously increased at Vgl of 2V as shown in Fig. 3-12(a).However, S.S change is no significantly increased as shown in Fig. 3-12(b) For the stress conditions with various levels of the gate pulse, the results reveal that the degradation is more important in accordance with the lower level of the gate pulse when drain bias is present. Compared with unitary gate AC stress, i.e. the AC pulse is performed on the gate electrode with the source and drain grounded [3.1], this dependence is a unique feature to our knowledge.
0 2 4 6 8 10
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Vg Low Level (V)
V th s h if t (V )
Vg=0~15V Vg=2~15V Vg=5~15V Vg=10~15V
Fig. 3-12(a) Dependence of Vth shift on various Vgl stress
0 2 4 6 8 10 0.0
0.1 0.2 0.3 0.4 0.5 0.6
S.S change ( V/dec )
Vg Low Level (V)
Vg=0~15V Vg=2~15V Vg=5~15V Vg=10~15V
Fig. 3-12(b) Dependence of S.S change on various Vgl stress
3.4.1.3 Effect of the pulse level
In this section, we will clarify the effect of the pulse level for the degradation dependence. The AC stress conditions of various Vg levels with fixed pulse swing are examined as shown in Fig. 3-13. The dependence of mobility degradation on various Vg levels with fixed pulse swing is shown in Fig. 3-14.
Fig. 3-13 The AC stress conditions of various Vg levels with fixed pulse swing
0~5 5~10 10~15 15~20 0~10 5~15 10~20 0~15 5~20 0.0
0.2 0.4 0.6 0.8 1.0
Mu S / Mu 0
Pulse Swing Range
Pulse Swing of 5V Pulse Swing of 10V Pulse Swing of 15V
(V)
Fig. 3-14 Dependence of mobility degradation on various Vg levels with fixed pulse swing
It is observed that the degradation strongly depends on Vg level. The degradation is relieved as the Vg at high level range no matter the increase in pulse swing. The dependences of
V
th shift and S.S change are shown in Fig. 3-15(a) and (b), respectively.It is obviously found that the
V
th shift and S.S change are increased at high level range.The degradation behavior of Vg at high level range is similar to the case of DC self-heating effect as mentioned in section 1.2.1. In addition, the worst mobility degradation occurs at lower level of the gate pulse, especially for swing range around the Vth of the device. It means that the degradation behavior of Vg at low level range is similar to the case of DC hot carrier effect as mentioned in section 1.2.1. The hot carrier is generated by impact ionization under the high electric field which is induced by high Vd and low Vg around Vth. Based on the results of the pulse level for the degradation dependence, it occurs to us that the DC components of the AC stress waveform might play an important role. Therefore, in the next section, the degradation behaviors induced by DC components of the AC stress waveform will be further analyzed.
Pulse Swing Range
0~5 5~10 10~15 15~20 0~10 5~15 10~20 0~15 5~20 0.0
Fig 3-15(a) Dependence of Vth shift on various Vg levels with fixed pulse swing
0~5 5~10 10~15 15~20 0~10 5~15 10~20 0~15 5~20 0.0
0.6 Pulse Swing of 5V
Pulse Swing of 10V Pulse Swing of 15V
Pulse Swing Range
S.S change (V/dec)
(V)
Fig 3-15(b) Dependence of S.S change on various Vg levels with fixed pulse swing
3.4.2 Duty Ratio
To study the degradation behavior induced by DC components of the AC stress waveform (Vgl and Vgh), we modulate the duty ratio from 25 % to 75 % to understand the relation during the different stress periods of single pulse. The duty ratio of the AC waveform (T_Vgl and T_Vgh) is illustrated in Fig. 3-16.
Fig. 3-16 Different stress duration of the Vg pulse level
For the stress pulse with fixed swing of 10 V as set in section 3.4.2.3, the dependences of mobility degradation on various duty ratios are shown in Fig. 3-17. It is observed that the serious degradation occurs at Vg of 0 V to 10 V and 5 V to 15 V with the decrease in duty ratio. In other words, the more degradation occurs when Vgl is around Vth of the device and stays longer. On the other hand, an opposite dependence trend on various duty ratios is found at Vg swinging between 10 V and 20 V. The degradation is enhanced with the increase in duty ratio. Moreover, the increase in the amount of
V
th shift and S.S change are observed at the same pulse range for longer duty ratio as shown in Fig. 3-18. It is clearly indicates that the degradation strongly25 50 75
Fig. 3-17 Dependence of degradation on various duty ratios for the stress pulse with fixed swing of 10 V
Fig. 3-18(a) Dependence of Vth shift on various duty ratios for the stress pulse with fixed swing of 10 V
25 50 75 0.0
0.1 0.2 0.3 0.4 0.5 0.6
Duty Ratio (%)
S.S change ( V/dec )
Vg=0~10V Vg=5~15V Vg=10~20V
Fig 3-18(b) Dependence of S.S change on various duty ratios for the stress pulse with fixed swing of 10 V
Base on the results, the degradation behavior of higher Vg level is quite similar to
Base on the results, the degradation behavior of higher Vg level is quite similar to