Table 3-1 Experiment conditions of transient time...24 Table 3-2 DC offset of various pulse ranges with fixed pulse swing and
duty ratio ...40 Table 3-3 DC offset of various levels and duty ratios of AC Pulse ...43
Figure Captions
Chapter 1 Introduction
Fig. 1-1 Stress voltage dependence of the Vth shift of the TFTs ...3 Fig. 1-2 Dependence of stress voltage on the Ion variation in the TFTs ...4 Fig. 1-3 A schematic diagram for degradation model of the N-type TFT ....5 Fig. 1-4 Previous researches of LTPS TFT reliability ...7
Chapter 2 Experiments
Fig. 2-1 The cross-section view of N-type LTPS TFT with LDD structure ... ..11 Fig. 2-2 TFT under gate AC stress with drain bias while source is grounded
...14 Fig. 2-3 Waveform and definition of the AC signal...15
Chapter 3 Results and Discussion
Fig. 3-1 Dependence of degradation on swing region of AC operation as source and drain were grounded ...18 Fig. 3-2 The transfer characteristics and the extracted mobility before and
after 100s stress under gate pulse of 0~15 V with various Vd...20 Fig. 3-3 Dependence of mobility degradation on various Vd with gate pulse stress of 0~15V ...20 Fig. 3-4 Time dependence of degradation under gate AC pulse with various
frequencies and fixed Vd of 15V ...22 Fig. 3-5 Dependence of degradation on the repetition number of the gate
AC pulse with fixed Vd of 15V ...22
Fig. 3-6 The various transient time of the gate pulse with fixed duration of
Vgh and Vgl ...23
Fig. 3-7(a) Rising time dependence of the mobility degradation for AC stress with Vg of 0~15V and fixed Vd of 15V ...25
Fig. 3-7(b) Falling time dependence of the mobility degradation for AC stress with Vg of 0~15V and fixed Vd of 15V ...25
Fig. 3-8(a) The various high-levels of the gate pulse with fixed low-level voltage...26
Fig. 3-8(b) The various low-levels of the gate pulse with fixed high-level voltage...26
Fig. 3-9 Dependence of mobility degradation on various Vgh stress ...27
Fig. 3-10(a) Dependence of Vth shift on various Vgh stress ...28
Fig. 3-10(b) Dependence of S.S change on various Vgh stress ...28
Fig. 3-11 Dependence of mobility degradation on various Vgl stress ...30
Fig. 3-12(a) Dependence of Vth shift on various Vgl stress ...31
Fig. 3-12(b) Dependence of S.S change on various Vgl stress ...32
Fig. 3-13 The AC stress conditions of various Vg levels with fixed pulse swing ...33
Fig. 3-14 Dependence of mobility degradation on various Vg levels with fixed pulse swing ...33
Fig. 3-15(a) Dependence of Vth shift on various Vg levels with fixed pulse swing ...35
Fig. 3-15(b) Dependence of S.S change on various Vg levels with fixed pulse swing...35
Fig. 3-16 Different stress duration of the Vg pulse level...36
Fig. 3-17 Dependence of degradation on various duty ratios for the stress pulse with fixed swing of 10 V ...37 Fig. 3-18(a) Dependence of Vth shift on various duty ratios for the stress
pulse with fixed swing of 10 V ...37 Fig. 3-18(b) Dependence of S.S change on various duty ratios for the stress
pulse with fixed swing of 10 V ...38 Fig. 3-19 Dependence of mobility degradation on VGO with fixed pulse
swing of 5V and 10V ...40 Fig. 3-20(a) Dependence of Vth shift on VGO with fixed pulse swing of 5V
and 10V...42 Fig. 3-20(b) Dependence of S.S change on VGO with fixed pulse swing of
5V and 10V ...42 Fig 3-21 Dependence of mobility degradation on VGO with various levels
and duty ratios of the gate pulse ...44 Fig. 3-22(a) Dependence of Vth shift on VGO with various levels and duty
ratios of the gate pulse ...44 Fig. 3-22(b) Dependence of S.S change on VGO with various levels and
duty ratios of the gate pulse ...45 Fig. 3-23 Dependence of mobility degradation on various DC Vg with
fixed Vd of 15V ...48 Fig. 3-24(a) Dependence of Vth shift on various DC Vg with fixed Vd of
15V...48 Fig. 3-24(b) Dependence of S.S change on various DC Vg with fixed Vd of
15V...49 Fig. 3-25 Dependence of degradation on VGO of overall experiment
conditions with various duty ratios ...50 Fig. 3-26 Dependence of mobility degradation between VGO under various
stress conditions and Vg of DC stresses with drain bias ...50 Fig. 3-27(a) Dependence of Vth shift between VGO under various stress
conditions and Vg of DC stresses with drain bias ...51 Fig. 3-27(b) Dependence of S.S change between VGO under various stress
conditions and Vg of DC stresses with drain bias ...51
Chapter 1 Introduction
1.1 Overview of Low-Temperature Polycrystalline Silicon Thin Film Transistors (LTPS TFTs)
In recent years, with the arrival of digital era and development of the flat panel display technology, the technology of low temperature polycrystalline silicon (LTPS) has become a pronoun of high-resolution displays. The LTPS thin-film transistors (TFTs) have attracted a great attention and have been used very successfully for active matrix displays, such as active matrix liquid crystal displays (AMLCDs) [1.1]-[1.6]
and active matrix organic light emitting displays (AMOLEDs), due to allow for peripheral integration of driving circuits with pixel panel and a high current driving capability as compared to conventional amorphous Si (α-Si) TFTs [1.7]-[1.11].
Moreover, taking advantage from these features, poly-Si TFTs can be fabricated both as pixel TFTs and the peripheral circuits including n-channel and p-channel transistors. LTPS TFTs for displays have become a very mature and high yield manufacturing technology in the latest innovations underlining the unique capability.
Advancing LTPS technology has led to the better display performance and up to now, several peripheral circuits have been successfully integrated on substrate [1.12].
Recently LTPS TFTs have been significant focus on the applications of the high level of device and circuit integration, such as Ambient Light Sensing, Integrated Touch, Ultra-Low Power Display Driving, and Advanced AMLCD Display Driving [1.13].
However, in spite of having superior applications, the degradation behavior of the poly-Si device is an important issue. Therefore, in order to realize the new applications and achieve those functions with LTPS TFTs, the improvement of the performance and the reliability of poly-Si TFTs is the most important requirement.
1.2 Review of Degradation for TFT under DC and AC Stress
In order to understand the degradation behavior of poly-Si TFTs, we briefly describe the mechanisms of device degradation under stress of different operating conditions as follows.
1.2.1 Degradation under DC Stress
Recently it was reported that poly-Si TFTs suffer from several degradation mechanisms, such as hot carrier effect [1.14]-[1.17], self-heating effect [1.18, 1.19], and photon-induced leakage current [1.20, 1.21]. In previous reports, Satoshi Inoue brought up the stress voltage dependence of the threshold voltage (Vth) shift in poly-Si TFTs, as shown in Fig. 1-1. Also, Satoshi Inoue (2003) presented the degenerated phenomena were classified to two main degradation regions including the stress voltage of region A and region B as shown in Fig. 1-2. It shows the effect of stress voltage on the Ion variation in TFTs [1.22, 1.23]. The two main degradation mechanisms of n-type TFTs are the hot carrier effect and the self-heating effect. In region A, the dominant degradation mechanism is self-heating, both the drain and gate voltages are high, typically over 10 V. Then, the dominant degradation mechanism is hot carrier in region B, where only the stress drain voltage is high, typically over 10 V, and gate voltage is low, typically from 2 V to 5 V.
At first, hot carrier degradation is considered to originate from the carriers under the high electric field around the drain; conduction carriers can obtain energy from the high electric field and become “hot” to cause the damage of the metal-oxide-semiconductor (MOS) interface and that of the channel near the drain of TFTs. Thus,
Si, creating many defect states and oxide charges.
As the gate voltage increases and correspondingly the equivalent lateral electrical field decreases, the hot carrier effect will be reduced. Instead, the power dissipation in the device is becoming high, causing the increase of device temperature due to Joule heat, which is known as self-heating or thermal effects [1.24]. Since TFTs are fabricated on glass substrates which have the poor thermal conductivity, the heat dissipation to the substrate is relatively low compared with Si substrate and makes the degradation worse. Besides, the influence of self-heating effects will increase with the width of TFTs.
Fig. 1-1 Stress voltage dependence of the Vth shift of the TFTs
Fig. 1-2 Dependence of stress voltage on the Ion variation in the TFTs
1.2.2 Degradation under AC Stress
Conventionally, dynamic stress (AC Stress) indicates the imposition of a gate pulse causing the repetition of channel ON/OFF. Under dynamic stress, TFTs in driving circuits are more similar to the actual switching operation that occurs in real panel than conventional DC stress. Even a small degradation cannot be allowed under high-frequency operation. Therefore, the degradation mechanism under dynamic operation should be understood in detail [1.25, 1.26].
In previous reports, Uraoka et al. attributed the dominant of degradation mechanism to hot electrons generated by trapped electrons exposed to the high electric field and gain energy from the electric field during AC stress. The mechanism was analyzed by using a pico-second emission microscope and device simulation to examine the transient current experimentally and theoretically, respectively.
The degradation model under AC stress by Uraoka is described as follows. When the gate voltage is high (Vg=15V, ON state), the electrons gather to form a channel, as shown in Fig. 1-3 (a). When the gate voltage abruptly varies from high to low (Vg=15V→-15V), the electrons in the channel move rapidly to the source and drain, as show in Fig. 1-3(b). Some of the trapped electrons are exposed to the high electric field and gain energy from the field. Hot electrons are generated at this moment and form electron traps shown in Fig. 1-3 (c), result in the increase of density of state (DOS) in tail edge of poly-Si.
ON
generation of hot carrier current
Vth
Fig. 1-3 A schematic diagram for degradation model of the N-type TFT
1.3 Motivation
While LTPS is developing towards integrated, system on panel (SOP) of high-efficiency, size of pixel and peripheral circuit shrink constantly, so extremely easy to destroy by the external force. Therefore, the quality of the device reliability has become the important key of deciding the issue of the battle. As compared to static stress, dynamic stress is closer to real operational condition and the enhanced degradation in poly-Si TFTs can be observed clearly. In addition, when the gate of the TFT is under dynamic operation, the drain-source voltage is usually present. Moreover, it is particularly important for circuit operation than pixel applications where drain biases of up to high voltage are necessary.
Although studies on static stress and dynamic stress for LTPS TFTs have been reported [1.27]-[1.32], to our knowledge a systematic study of the degradation in combination to that of dynamic and static stress has not been reported. The summary of previous researches is shown in Fig. 1-4. The purpose of the previous works was to better understand hot carrier degradation effects in the devices, and to be able to make reliable predictions of device lifetime. However, from the viewpoint of realizing devices of high reliability, hot-carrier-induced degradation under AC and DC stress is a critical issue.
In this thesis, the different aspects of the degradation in the characteristics of N-type poly-Si TFTs under gate pulse stress of the ON region with drain bias are described. Therefore, the investigation of N-type poly-Si TFT degradation phenomena including frequency, swing range, the profile of the gate pulse, and duty ratio will be discussed to verify the mechanisms under AC stress.
Fig. 1-4 Previous researches of LTPS TFT reliability
1.4 Thesis Organization
Chapter 1 Introduction
1.1 Overview of Low-Temperature Polycrystalline Silicon Thin Film Transistors (LTPS TFTs)
1.2 Review of Degradation for TFT under DC and AC Stress
1.2.1 Degradation under DC stress
1.2.2 Degradation under AC stress
1.3 Motivation
1.4 Thesis Organization
Chapter 2 Experiments
2.1 Procedure of Fabrication of LTPS TFTs
2.2 Extraction of Device Electrical Parameters
2.3 Stress Conditions
Chapter 3 Results and Discussion
3.1 Degradation of the Transfer Characteristics
3.2 Dependence on the Number of Gate Pulse Repetition
3.3 Effect of the Transient Time
3.4 Dependence on Gate Pulse Profile
3.4.1 Pulse Range
3.4.1.1 High-Level of the Gate Pulse
3.4.1.2 Low-Level of the Gate Pulse
3.4.1.3 Effect of the Pulse Level
3.4.2 Duty Ratio
3.4.3 DC Offset of the AC Pulse
3.4.2.1 Dependence on DC Offset of the AC Pulse with Fixed Swing Range
3.4.2.2 Dependence on DC Offset of the AC Pulse with Various Duty Ratio
3.4.4 Summary
3.5 Discussion
3.6 Summary