N型複晶矽薄膜電晶體在閘極開區域脈衝電壓及汲極直流偏壓下的劣化研究

(1)

國

立

交

通

大

學

電機學院光電顯示科技產業研發碩士班

碩

士

論

文

N 型

型

型複晶矽薄膜電晶體在閘極

複晶矽薄膜電晶體在閘極

複晶矽薄膜電晶體在閘極開區域

複晶矽薄膜電晶體在閘極

開區域

開區域脈衝電壓

開區域

脈衝電壓

及汲極直流偏壓下的劣化研究

Study of N-type LTPS TFTs Degradation under Gate Pulse Stress

in ON Region with Drain Bias

研

究

生

生：

：

：詹

詹

長

龍

Chang-Lung Chan

指導教授

指導教授：

：

：戴

戴

亞

翔

博士

Dr. Ya-Hsiang Tai

中

華

民

國

九

十

七

年

三

月

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N 型複晶矽薄膜電晶體在閘極開區域脈衝電壓

及汲極直流偏壓下的劣化研究

Study of N-type LTPS TFTs Degradation under Gate Pulse Stress

in ON Region with Drain Bias

研究生：詹長龍 Student：Chang-Lung Chan

指導教授：戴亞翔 Advisor：Dr. Ya-Hsiang Tai

國立交通大學

電機學院光電顯示科技產業研發碩士班

碩士論文

A Thesis

Submitted to College of Electrical and Computer Engineering National Chiao Tung University

in partial Fulfillment of the Requirements for the Degree of

Master in

Industrial Technology R & D Master Program on Photonics and Display Technologies

March 2008

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N 型

型

型複晶矽薄膜電晶體在閘極開區域脈衝電壓

複晶矽薄膜電晶體在閘極開區域脈衝電壓

及汲極直流偏壓下的劣化研究

學生

學生：

：

：詹長龍

：

詹長龍

詹長龍指導教授

指導教授：

指導教授

：

：戴亞翔

戴亞翔

戴亞翔博士

博士

國立交通大學電機學院產業研發碩士班

摘

要

摘

要

摘

要

摘

要

本論文主要的目的是研究 N 型複晶矽薄膜電晶體在交流訊號操作下的劣化行為。這篇論文不同於先前的研究，其是研究 N 型複晶矽薄膜電晶體在閘極開區域交流訊號和汲極偏壓操作下的劣化特性，這將更接近實際電路應用上的操作條件。元件的劣化是透過改變不同交流閘極脈衝和汲極直流偏壓的條件來測試。我們觀察到元件的劣化受到汲極直流偏壓、閘極脈衝次數、閘極電壓位準和工作週期所影響。基於皆有大汲極直流偏壓下的直流閘極操作和交流閘極操作之間的比較，我們提出一個新的指標（VGO）來針對閘極交流訊號作直流閘極電壓的等效估

算。由此結果更進一步的發現，直流操作下的熱載子效應（hot carrier effect）和自我發熱效應（self-heating effect）的特徵可對應於有汲極直流偏壓的交流閘極操作。除此新發現外，也清楚知道在交流操作下，不同工作週期與元件劣化之間的關係。即熱載子是主導低閘極電壓範圍操作的劣化，且劣化相對隨著閘極脈衝的工作週期減少明顯增加。然而，在高閘極電壓脈衝造成的劣化是由自

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我發熱主導，並隨著閘極脈衝工作週期的增加而效應更明顯。根據直流操作和交流操作之間的相似處，在開區域的動態操作下，其複晶矽薄膜電晶體的可靠度便可藉由直流操作條件的可靠度行為做簡單地估算。

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Study of N-type LTPS TFTs Degradation under

Gate Pulse Stress in ON Region with Drain Bias

student：

：

：Chang-Lung Chan Advisor：

：

：Dr. Ya-Hsiang Tai

Industrial Technology R & D Master Program of

Electrical and Computer Engineering College

National Chiao Tung University

ABSTRACT

The purpose of this thesis is to study the degradation behavior of N-type poly-Si TFTs under AC operation. It differs from previous studies, the characteristics of poly-Si TFTs under gate pulse AC operation in the ON region with drain bias are investigated, which would be much similar to the real operation conditions in applications. Degradation of the device is examined for various conditions of AC gate pulse and DC drain bias. It is observed that the degradation is affected by the drain bias, pulse repetition number, gate pulse level, and duty ratio.

On the basis of the comparison between the DC gate stress and AC gate stress both with large Vd, we proposed a new index VGO to estimate the equivalent DC Vg

for the gate AC signal. It is further found from the results that the features of hot carrier effect and self-heating effect in DC stress are corresponding to gate AC stress with drain bias. In addition to this new finding, the relation between the device

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degradation and various duty ratios under AC operation with Vd is also evidenced. That is, hot carriers are the dominant cause of degradation under low-level of the gate voltage (Vgl), and the mobility degradation obviously increases with the decrease in duty ratio. However, the degradation is dominated by self-heating under high-level of the gate pulse (Vgh) and corresponding with the increase in duty ratio. Based on the similarity between the DC stress and AC gate stress, the reliability of poly-Si TFTs dynamically operated in the ON region could be simply estimated from its reliability behavior under DC stress conditions.

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誌

誌謝

謝

在這兩年來的研究生涯中，首先我要誠摯感謝我的指導教授戴亞翔博士，謝謝老師在研究上的熱心指導及思考邏輯上的指引，使我嘗試去發掘問題且能有效率的解決問題。此外也感謝老師在人生規劃上給予的建議，使我在處事上能以更積極正面的態度來面對。感謝實驗室的博班學長與已畢業的學長姐們，謝謝你們在實驗上的指導和課業上的協助，其中包含了士哲、彥甫、一德、虹娟、俊文、育德、偉倫、振業及晉煒。當然還有實驗室的同學與學弟妹，明憲、曉嫻、逸侑、誼明、勝昌、翔帥、漢清、枷彬、阿貴、紹文、柏廷、騰瑞與國珮，在研究上、課業上以及生活上的扶持和勉勵。特別是在趕論文的這段期間，有你們鼎力相助的量測和精神上的支持，也因為你們的相伴，實驗室裡的研究生活才充滿歡樂且多采。感謝我的好朋友們，世明、彥佑、采芬、博忠、玫嬛、瑞堂、玉錫、佑生、宜陽、信旗與益煒，有你們的陪伴和關心，不僅帶給我成長的動力也替我分擔了生活中遇到的煩憂，在此由衷的致上謝意並希望能藉此論文與你們分享我的喜悅。最後要感謝我的家人們，爸爸、媽媽、老哥以及小妹，不停地在背後給我支持與祝福，讓我在人生旅途中有溫暖的靠岸。另外還有很多幫助過我的朋友們，因為有大家的幫助和祝福，我才能有今天的成果，再次謝謝您們。

長龍

2008.03.27

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Abstract (Chinese)...i

Abstract (English)...iii

Acknowledgements...v

Contents...vi

Table Captions...viii

Figure Captions...ix

Chapter 1 Introduction...1

1.1 Overview of Low-Temperature Polycrystalline Silicon Thin Film Transistors (LTPS TFTs)...1

1.2 Review of Degradation for TFT under DC and AC Stress...2

1.2.1 Degradation under DC Stress...2

1.2.2 Degradation under AC Stress...4

1.3 Motivation...6

1.4 Thesis Organization...8

Chapter 2 Experiments...10

2.1 Procedure of Fabrication of LTPS TFTs...10

2.2 Extraction of Device Electrical Parameters...12

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Chapter 3 Results and Discussion...18

3.1 Degradation of the Transfer Characteristics...19

3.2 Dependence on the Number of Gate Pulse Repetition...21

3.3 Effect of the Transient Time...23

3.4 Dependence on Gate Pulse Profile...26

3.4.1 Pulse Range...26

3.4.1.1 High-Level of the Gate Pulse...27

3.4.1.2 Low-Level of the Gate Pulse...30

3.4.1.3 Effect of the pulse level...33

3.4.2 Duty Ratio...36

3.4.3 DC Offset of the AC Pulse...39

3.4.3.1 Dependence on DC Offset of the AC Pulse with Fixed Swing Range...39

3.4.3.2 Dependence on DC Offset of the AC Pulse with Various Duty Ratio...43 3.4.4 Summary ...46 3.5 Discussion ...47 3.6 Summary...53

Chapter 4 Conclusion...54

References...55

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Table Captions

Chapter 2 Experiments

Table 2-1 Experiment conditions of drain bias ...15 Table 2-2 Experiment conditions of pulse repetitions ...16 Table 2-3 Experiment conditions of transient time...16 Table 2-4 Experiment conditions of various pulse ranges and duty ratios..17

Chapter 3 Results and Discussion

Table 3-1 Experiment conditions of transient time...24 Table 3-2 DC offset of various pulse ranges with fixed pulse swing and

duty ratio ...40 Table 3-3 DC offset of various levels and duty ratios of AC Pulse ...43

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Figure Captions

Chapter 1 Introduction

Fig. 1-1 Stress voltage dependence of the Vth shift of the TFTs ...3 Fig. 1-2 Dependence of stress voltage on the Ion variation in the TFTs ...4 Fig. 1-3 A schematic diagram for degradation model of the N-type TFT ....5 Fig. 1-4 Previous researches of LTPS TFT reliability ...7

Chapter 2 Experiments

Fig. 2-1 The cross-section view of N-type LTPS TFT with LDD structure ... ..11 Fig. 2-2 TFT under gate AC stress with drain bias while source is grounded

...14 Fig. 2-3 Waveform and definition of the AC signal...15

Chapter 3 Results and Discussion

Fig. 3-1 Dependence of degradation on swing region of AC operation as source and drain were grounded ...18 Fig. 3-2 The transfer characteristics and the extracted mobility before and

after 100s stress under gate pulse of 0~15 V with various Vd...20 Fig. 3-3 Dependence of mobility degradation on various Vd with gate pulse stress of 0~15V ...20 Fig. 3-4 Time dependence of degradation under gate AC pulse with various

frequencies and fixed Vd of 15V ...22 Fig. 3-5 Dependence of degradation on the repetition number of the gate

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Fig. 3-6 The various transient time of the gate pulse with fixed duration of

Vgh and Vgl ...23

Fig. 3-7(a) Rising time dependence of the mobility degradation for AC stress with Vg of 0~15V and fixed Vd of 15V ...25

Fig. 3-7(b) Falling time dependence of the mobility degradation for AC stress with Vg of 0~15V and fixed Vd of 15V ...25

Fig. 3-8(a) The various high-levels of the gate pulse with fixed low-level voltage...26

Fig. 3-8(b) The various low-levels of the gate pulse with fixed high-level voltage...26

Fig. 3-9 Dependence of mobility degradation on various Vgh stress ...27

Fig. 3-10(a) Dependence of Vth shift on various Vgh stress ...28

Fig. 3-10(b) Dependence of S.S change on various Vgh stress ...28

Fig. 3-11 Dependence of mobility degradation on various Vgl stress ...30

Fig. 3-12(a) Dependence of Vth shift on various Vgl stress ...31

Fig. 3-12(b) Dependence of S.S change on various Vgl stress ...32

Fig. 3-13 The AC stress conditions of various Vg levels with fixed pulse swing ...33

Fig. 3-14 Dependence of mobility degradation on various Vg levels with fixed pulse swing ...33

Fig. 3-15(a) Dependence of Vth shift on various Vg levels with fixed pulse swing ...35

Fig. 3-15(b) Dependence of S.S change on various Vg levels with fixed pulse swing...35

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Fig. 3-17 Dependence of degradation on various duty ratios for the stress pulse with fixed swing of 10 V ...37 Fig. 3-18(a) Dependence of Vth shift on various duty ratios for the stress

pulse with fixed swing of 10 V ...37 Fig. 3-18(b) Dependence of S.S change on various duty ratios for the stress

pulse with fixed swing of 10 V ...38 Fig. 3-19 Dependence of mobility degradation on VGO with fixed pulse

swing of 5V and 10V ...40 Fig. 3-20(a) Dependence of Vth shift on VGO with fixed pulse swing of 5V

and 10V...42 Fig. 3-20(b) Dependence of S.S change on VGO with fixed pulse swing of

5V and 10V ...42 Fig 3-21 Dependence of mobility degradation on VGO with various levels

and duty ratios of the gate pulse ...44 Fig. 3-22(a) Dependence of Vth shift on VGO with various levels and duty

ratios of the gate pulse ...44 Fig. 3-22(b) Dependence of S.S change on VGO with various levels and

duty ratios of the gate pulse ...45 Fig. 3-23 Dependence of mobility degradation on various DC Vg with

fixed Vd of 15V ...48 Fig. 3-24(a) Dependence of Vth shift on various DC Vg with fixed Vd of

15V...48 Fig. 3-24(b) Dependence of S.S change on various DC Vg with fixed Vd of

15V...49 Fig. 3-25 Dependence of degradation on VGO of overall experiment

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conditions with various duty ratios ...50 Fig. 3-26 Dependence of mobility degradation between VGO under various

stress conditions and Vg of DC stresses with drain bias ...50 Fig. 3-27(a) Dependence of Vth shift between VGO under various stress

conditions and Vg of DC stresses with drain bias ...51 Fig. 3-27(b) Dependence of S.S change between VGO under various stress

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Chapter 1 Introduction

1.1 Overview of Low-Temperature Polycrystalline

Silicon Thin Film Transistors (LTPS TFTs)

In recent years, with the arrival of digital era and development of the flat panel display technology, the technology of low temperature polycrystalline silicon (LTPS) has become a pronoun of high-resolution displays. The LTPS thin-film transistors (TFTs) have attracted a great attention and have been used very successfully for active matrix displays, such as active matrix liquid crystal displays (AMLCDs) [1.1]-[1.6] and active matrix organic light emitting displays (AMOLEDs), due to allow for peripheral integration of driving circuits with pixel panel and a high current driving capability as compared to conventional amorphous Si (α-Si) TFTs [1.7]-[1.11].

Moreover, taking advantage from these features, poly-Si TFTs can be fabricated both as pixel TFTs and the peripheral circuits including n-channel and p-channel transistors. LTPS TFTs for displays have become a very mature and high yield manufacturing technology in the latest innovations underlining the unique capability. Advancing LTPS technology has led to the better display performance and up to now, several peripheral circuits have been successfully integrated on substrate [1.12]. Recently LTPS TFTs have been significant focus on the applications of the high level of device and circuit integration, such as Ambient Light Sensing, Integrated Touch, Ultra-Low Power Display Driving, and Advanced AMLCD Display Driving [1.13].

However, in spite of having superior applications, the degradation behavior of the poly-Si device is an important issue. Therefore, in order to realize the new applications and achieve those functions with LTPS TFTs, the improvement of the performance and the reliability of poly-Si TFTs is the most important requirement.

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1.2 Review of Degradation for TFT under DC and AC

Stress

In order to understand the degradation behavior of poly-Si TFTs, we briefly describe the mechanisms of device degradation under stress of different operating conditions as follows.

1.2.1 Degradation under DC Stress

Recently it was reported that poly-Si TFTs suffer from several degradation mechanisms, such as hot carrier effect [1.14]-[1.17], self-heating effect [1.18, 1.19], and photon-induced leakage current [1.20, 1.21]. In previous reports, Satoshi Inoue brought up the stress voltage dependence of the threshold voltage (Vth) shift in poly-Si

TFTs, as shown in Fig. 1-1. Also, Satoshi Inoue (2003) presented the degenerated phenomena were classified to two main degradation regions including the stress voltage of region A and region B as shown in Fig. 1-2. It shows the effect of stress voltage on the Ion variation in TFTs [1.22, 1.23]. The two main degradation

mechanisms of n-type TFTs are the hot carrier effect and the self-heating effect. In region A, the dominant degradation mechanism is self-heating, both the drain and gate voltages are high, typically over 10 V. Then, the dominant degradation mechanism is hot carrier in region B, where only the stress drain voltage is high, typically over 10 V, and gate voltage is low, typically from 2 V to 5 V.

At first, hot carrier degradation is considered to originate from the carriers under the high electric field around the drain; conduction carriers can obtain energy from the high electric field and become “hot” to cause the damage of the metal-oxide-semiconductor (MOS) interface and that of the channel near the drain of TFTs. Thus,

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Si, creating many defect states and oxide charges.

As the gate voltage increases and correspondingly the equivalent lateral electrical field decreases, the hot carrier effect will be reduced. Instead, the power dissipation in the device is becoming high, causing the increase of device temperature due to Joule heat, which is known as self-heating or thermal effects [1.24]. Since TFTs are fabricated on glass substrates which have the poor thermal conductivity, the heat dissipation to the substrate is relatively low compared with Si substrate and makes the degradation worse. Besides, the influence of self-heating effects will increase with the width of TFTs.

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Fig. 1-2 Dependence of stress voltage on the Ion variation in the TFTs

1.2.2 Degradation under AC Stress

Conventionally, dynamic stress (AC Stress) indicates the imposition of a gate pulse causing the repetition of channel ON/OFF. Under dynamic stress, TFTs in driving circuits are more similar to the actual switching operation that occurs in real panel than conventional DC stress. Even a small degradation cannot be allowed under high-frequency operation. Therefore, the degradation mechanism under dynamic operation should be understood in detail [1.25, 1.26].

In previous reports, Uraoka et al. attributed the dominant of degradation mechanism to hot electrons generated by trapped electrons exposed to the high electric field and gain energy from the electric field during AC stress. The mechanism was analyzed by using a pico-second emission microscope and device simulation to examine the transient current experimentally and theoretically, respectively.

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The degradation model under AC stress by Uraoka is described as follows. When the gate voltage is high (Vg=15V, ON state), the electrons gather to form a channel, as shown in Fig. 1-3 (a). When the gate voltage abruptly varies from high to low (Vg=15V→-15V), the electrons in the channel move rapidly to the source and drain, as show in Fig. 1-3(b). Some of the trapped electrons are exposed to the high electric field and gain energy from the field. Hot electrons are generated at this moment and form electron traps shown in Fig. 1-3 (c), result in the increase of density of state (DOS) in tail edge of poly-Si.

ON High (Vg=+15V) Low (Vg=-15V) OFF channel (low field) depletion (high field) Vg=+15V channel formation channel Vth

(a)

ON High (Vg=+15V) Low (Vg=-15V) OFF channel (low field) depletion (high field) Vg=+15V -15V

generation of hot carrier current

Vth

(b)

ON High (Vg=+15V) Low (Vg=-15V) OFF channel (low field) depletion (high field) Vg=-15V

generation of electron traps

Vth

(c)

Fig. 1-3 A schematic diagram for degradation model of the N-type TFT

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1.3 Motivation

While LTPS is developing towards integrated, system on panel (SOP) of high-efficiency, size of pixel and peripheral circuit shrink constantly, so extremely easy to destroy by the external force. Therefore, the quality of the device reliability has become the important key of deciding the issue of the battle. As compared to static stress, dynamic stress is closer to real operational condition and the enhanced degradation in poly-Si TFTs can be observed clearly. In addition, when the gate of the TFT is under dynamic operation, the drain-source voltage is usually present. Moreover, it is particularly important for circuit operation than pixel applications where drain biases of up to high voltage are necessary.

Although studies on static stress and dynamic stress for LTPS TFTs have been reported [1.27]-[1.32], to our knowledge a systematic study of the degradation in combination to that of dynamic and static stress has not been reported. The summary of previous researches is shown in Fig. 1-4. The purpose of the previous works was to better understand hot carrier degradation effects in the devices, and to be able to make reliable predictions of device lifetime. However, from the viewpoint of realizing devices of high reliability, hot-carrier-induced degradation under AC and DC stress is a critical issue.

In this thesis, the different aspects of the degradation in the characteristics of N-type poly-Si TFTs under gate pulse stress of the ON region with drain bias are described. Therefore, the investigation of N-type poly-Si TFT degradation phenomena including frequency, swing range, the profile of the gate pulse, and duty ratio will be discussed to verify the mechanisms under AC stress.

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1.4 Thesis Organization

Chapter 1 Introduction

1.1 Overview of Low-Temperature Polycrystalline Silicon Thin Film Transistors (LTPS TFTs)

1.2 Review of Degradation for TFT under DC and AC Stress 1.2.1 Degradation under DC stress

1.2.2 Degradation under AC stress 1.3 Motivation

1.4 Thesis Organization

Chapter 2 Experiments

2.1 Procedure of Fabrication of LTPS TFTs 2.2 Extraction of Device Electrical Parameters 2.3 Stress Conditions

Chapter 3 Results and Discussion

3.1 Degradation of the Transfer Characteristics

3.2 Dependence on the Number of Gate Pulse Repetition 3.3 Effect of the Transient Time

3.4 Dependence on Gate Pulse Profile 3.4.1 Pulse Range

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3.4.1.1 High-Level of the Gate Pulse 3.4.1.2 Low-Level of the Gate Pulse 3.4.1.3 Effect of the Pulse Level 3.4.2 Duty Ratio

3.4.3 DC Offset of the AC Pulse

3.4.2.1 Dependence on DC Offset of the AC Pulse with Fixed Swing Range

3.4.2.2 Dependence on DC Offset of the AC Pulse with Various Duty Ratio

3.4.4 Summary 3.5 Discussion 3.6 Summary

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Chapter 2 Experiments

2.1 Procedure of Fabrication of LTPS TFTs

LTPS TFTs used in the experiment were the conventional top-gate structure and fabricated on glass substrates. The process flow of TFTs is described below. First, the buffer oxide and 50 nm thick a-Si:H films were deposited on glass substrates with plasma-enhanced chemical vapor deposition (PECVD). The samples were then put into the oven for dehydrogenation. The XeCl excimer laser of wavelength 308 nm and energy density of 400 mJ/cm2 was applied to scan the a-Si:H film with the beam width of 4 mm and 98 % overlap to recrystallize the a-Si:H film to poly-Si. After poly-Si active area definition, 80 nm SiO2 and 40 nm SiNx films were deposited with PECVD

as the gate insulator. Next, the metal gate was formed by sputter and then defined. The

lightly doped drain (LDD) and the n+ source/drain doping were formed by PH3

implantation with dosage 2×1013 and 2×1015 cm2 of PH3, respectively. The LDD

implantation was self-aligned and the n+ regions were defined with a separate mask. Then the interlayer of SiNx was deposited. Subsequently, the rapid thermal annealing was conducted to activate the dopants. Meanwhile, the poly-Si film was hydrogenated. Finally, the contact holes formation and metallization were performed to complete the fabrication work.

In this study, N-type TFTs with a channel width of 20 µm and a channel length of 5 µm with an LDD structure of length 1.2 µm are fabricated. Figure 2-1 shows the cross-section structure of the N-type poly-Si TFT with LDD.

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n+

Glass substrate

buffer oxide

interlayer

metal

Gate

n-

n-insulator

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2.2 Extraction of Device Electrical Parameters

Here, we will introduce the methods of the typical electrical parameter extraction, including threshold voltage (Vth), field-effect mobility (

µFE

), subthreshold swing (SS).

Determination of the Threshold Voltage (V

th

)

For most of the researches on TFT, the constant current method is widely-used to determine the threshold voltage (

V

th). In this thesis, the Vth is determined by this

method, which extracts the rated current (IDt) from the drain current curve. Thus, the

corresponding voltage is the threshold voltage of the constant current. In general, the rated current is defined as

L W I

I_Dt = _DN (2-1) where IDN is normalized drain current, i.e. threshold current. Typically, the threshold

current is specified as 10 nA for |VDS| =0.1 V and 100 nA for. |VDS| =10 V.

Determination of the Field Effect Mobility (µ

FE

)

The transfer characteristics of poly-Si TFTs are similar to those of conventional MOSFETs. The MOSFETs can be applied to the poly-Si TFTs, so the first order I-V relation in the bulk Si. The field effect mobility (Mu,

µFE

) is derived from the maximum value of the transconductance (gm), which can be expressed as

(

)

_   − − = 2 2 1 D D th G ox FE D V V V V L W C I

µ

(2-2) where Cox is the gate capacitance per unit area, W is channel width, L is channel length,

Vth is the threshold voltage. If the drain voltage (VD) is much smaller as compared with

G th

V −V , i.e. V_D <<

(

V_G −V_th

)

, and V_G >V_th then the drain current can be approximated as

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D th G ox FE D V V V L W C I =µ ( − ) (2-3) From the above equation, the gm can be obtained,

D FE ox const V G D m

V

L

WC

V

I

g

D

µ

=

∂

=

₌ . (2-4)

Therefore, the field effect mobility with Eq. (2-4) can be rewritten as

m D ox FE g WV C L = µ (2-5) In other words, the field-effect mobility can be extracted by taking the maximum value of the gm into (2-5) when VD = 0.1 V.

Determination of the Subthreshold Swing (S.S)

When the gate voltage (Vg) is below the threshold voltage (Vth) and the channel

of poly-Si appears weak inversion or depletion, the corresponding drain current is called the sub-threshold current. The subthreshold region tells how sharply the current drops with gate bias. In general, the subthreshold current is exponentially dependent on

G th

V −V , so the subthreshold swing (S.S) is used for observing the characteristic of turning on and turning off about the TFT. It can be shown that the expression for S.S is given by

(

log

)

1 . −       ∂ ∂ = GS DS V I S S (2-6)

Here, we extract the minimum value of S.S at the Id-Vg curve for |Vds| =0.1 V. Clearly, the smaller value of S.S correlates to the better characteristic of transistor, which means a small change in the input bias can modulate the output current considerably.

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2.3 Stress Conditions

The Agilent 4156A precise semiconductor parameter analyzer with HP 41501B pulse generator was used to measure the I-V curve and stress the device with different conditions, respectively. The AC pulse voltage was performed on the gate electrode as the dynamic stress and the drain DC bias was applied with grounding source, which is shown in Fig.2-2. Regarding standard stress conditions, we used a rectangular pulse with amplitude of +15 V, duty ratio of 50 %, and frequency of 500 kHz, and both the rising time (Tr) and falling time (Tf) were fixed in 100 ns as shown in Fig.2-3. Furthermore, the drain bias and source were +15V and grounded respectively. The basic parameters of AC signal include frequency (F), i.e. the reciprocal of period (T), signal high level (Vgh), signal low level (Vgl), high-level time (T_vgh), low-level time (T_vgl), rising time (Tr), and falling time (Tf). Here, the definition of individual parameter is given as follows:

T = Tr + T_vgh + Tf + T_vgl (2-7)

F = 1 / T (2-8)

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Fig. 2-3 Waveform and definition of the AC signal

In the beginning, Vd is changed from 0 V to 20 V as listed in Table 2-1. With the increase in drain bias, the stress condition is observed to result in the significant degradation. Therefore, to investigate which parameter of the stress pulse dominates the degradation of the n-type Poly-Si TFTs, we measured the various experiment results including the effects of pulse frequency, transient time, gate pulse range, and duty ratio.

Table 2-1 Experiment conditions of drain bias

Stress Conditions

Experiment

Gate Pulse Drain Bias Frequency Duty Ratio Stress time

Drain Bias Vg=0~15V

Vd=0、、、、5、、、、

10、、、、15、、、、20V 500kHz 50% 100s

First, we change frequency of gate pulse from 5 kHz to 500 kHz for the gate pulse repetition study. The conditions are listed in table 2-2.

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Table 2-2 Experiment conditions of pulse repetitions

Stress Conditions

Experiment

Gate Pulse Drain Bias Frequency Duty Ratio Stress time

Pulse Repetition Vg=0~15V Vd=15V 5kHz 50kHz 500kHz 50% 100s 300s 500s

Next, the effect of transient time at fixed number of the pulse repetition for the degradation of the device is examined. Here, the Tr and Tf from 100 ns to 700 ns are changed. Meanwhile, the duration of signal high-level (T_Vgh) and signal low-level (T_Vgl) are fixed as 900 ns. The experiment conditions are listed in Table 2-3.

Table 2-3 Experiment conditions of transient time (T_Vgh = TVgl = 900ns)

Stress Conditions

Experiment

Gate Pulse Drain Bias Rising Time Falling Time Pulse Period

Pulse Repetition Number 100 ns 100 ns 2 us 300 ns 100 ns 2.2 us Rising Time Vg=0~15V Vd=15V 700 ns 100 ns 2.6 us 5.0E+07 100 ns 100 ns 2 us 100 ns 300 ns 2.2 us Falling Time Vg=0~15V Vd=15V 100 ns 700 ns 2.6 us 5.0E+07

Subsequently, in order to compare the effects of gate pulse in different range, we classified the swing ranges of gate pulse into two categories. Namely, fixed low gate voltage Vgl of 0 V, and fixed high gate voltage Vgh of 15 V. To clarify the effect of the pulse level for the degradation dependence, the stress conditions of various Vg levels with fixed pulse swing are examined and are further distinguished according to the

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duty ratio. Finally, we examine the dependence of degradation on DC offset of the gate pulse under various pulse ranges and duty ratios. The experiment conditions are summarized in Table 2-4.

Table 2-4 Experiment conditions of various pulse ranges and duty ratios Stress Conditions

Experiment

Gate Pulse Drain Bias Frequency Duty Ratio Stress time

Vg=0~5、、、10、、、、、 15、、、20V 、 (Fixed Vg_l=0V) Vd=15V 500kHz 25% 50% 75% 100s Pulse Range Vg=0、、、2、、、、、5、、、、 10~15V (Fixed Vg_h=15V) Vd=15V 500kHz 25% 50% 75% 100s Vg=0~5V Vg=5~10V Vg=10~15V Pulse Swing of 5V Vg=15~20V Vd=15V 500kHz 25% 50% 75% 100s Vg=0~10V Vg=5~15V Pulse Swing of 10V Vg=10~20V Vd=15V 500kHz 25% 50% 75% 100s Vg=0~15V Pulse Swing of 15V Vg=5~20V Vd=15V 500kHz 25% 50% 75% 100s

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Chapter 3 Results and Discussion

In previous research, Uraoka et al. proposed that the degradation of N-type poly-Si TFTs under gate AC operation as source and drain were grounded increases obviously with the variation of amplitude in the OFF region, as shown in Fig. 3-1 [3.1]. In the ON region, the degradation is negligible. However, with drain bias, the stress condition for gate AC operation is more similar to the actual switching operation that occurs in real panel. In order to further understand the phenomena, the degradation of N-type poly-Si TFTs under gate ON region AC stress with drain bias will be described and discussed in this chapter.

Fig. 3-1 Dependence of degradation on swing region of AC operation as source and drain were grounded

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3.1 Degradation of the Transfer Characteristics

Figure 3-2 shows the transfer characteristics and extracted mobility for the N-type poly-Si TFTs before and after 100 s stress under gate pulse of 0~15 V with various drain bias (Vd) from 0 V to 20 V. The drain voltage used in the measurement was 0.1 V. It is observed that devices remain almost unchanged in the subthreshold region. However, the changes of the mobility curve and the decrease of ON-current are relatively obvious in this case. The dependence of mobility degradation at various Vd is shown in Fig. 3-3. The mobility degradation is expressed by the ratio of degraded mobility (MuS) to the initial mobility (Mu0). It must be noted that the degradation is

significantly accelerated on Vd of 15 V and 20 V.

Therefore, we can recognize from the result that the degradation of N-type poly-Si TFTs under gate AC operation in the ON region with drain bias is important. To obviously demonstrate the degradation in the case, the drain bias for the other experiment conditions is set to be 15 V.

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-10 -5 0 5 10 15 20 1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 -10 -5 0 5 10 15 20 0 20 40 60 80 100 120 D ra in C u rr e n t (A ) Gate Voltage (V) Stress Vg=0~15V Measurement by Vd=0.1V Initial Vd=0V Vd=5V Vd=10V Vd=15V Vd=20V M o b il it y ( c m 2 /V -s e c ) Initial Vd=0V Vd=5V Vd=10V Vd=15V Vd=20V

Fig. 3-2 The transfer characteristics and the extracted mobility before and after 100s stress under gate pulse of 0~15 V with various Vd

0 5 10 15 20 0.0 0.2 0.4 0.6 0.8 1.0

M

u

S

/

M

u

0

Drain Bias (V)

Mobility Degradation

Stress condition

Vg=0~15V,

Freq.= 500kHz

duty ratio = 50%

Vd=0, 5, 10, 15, 20V, Vs=0

time = 100s

Fig. 3-3 Dependence of mobility degradation on various Vd with gate pulse stress of 0~15V

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3.2 Dependence on the Number of Gate Pulse

Repetition

Under gate AC pulse with various frequencies and fixed Vd of 15 V, the time dependence of the device degradation is shown in Fig. 3-4. Degradation is enhanced with the increase in frequency. And the degradation is changed violently in a shorter period of stress beginning for higher frequency. It occurs to us that the larger switching numbers take place in high frequency stress. Therefore, the number of the pulse repetition can be suggested as a reason for the degradation.

Then, the time dependence of the degradation for various frequencies is re-plotted as the repetition number dependence as shown in Fig. 3-5. The relationship between the degradation and the repetition number of the pulse is almost universal, and it is not apparently dependent on the frequency. As the slight degradation shift in the same number of repetition, we regard it as a consequence of the device variation. Since the degradation closely correlates with the number of gate pulse repetition, it is necessary to further investigate the transient effect. In the next section, the experiment conditions with various rising time and falling time will be performed.

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0 200 400 600 800 1000 0.0 0.2 0.4 0.6 0.8 1.0

Stress condition

Vg=0~15V @ ON region

Duty=50%, Vd=15V, Vs=0V

Stress time (s)

M

u

S

/

M

u

0

5kHz

50kHz

500kHz

Fig. 3-4 Time dependence of degradation under gate AC pulse with various frequencies and fixed Vd of 15V

1000000 1E7 1E8 1E9

0.0 0.2 0.4 0.6 0.8 1.0

M

u

S

/

M

u

0

Number of Repetition

5kHz

50kHz

500kHz

Stress condition

Vg=0~15V @ ON region

Duty=50%, Vd=15V, Vs=0V

Fig. 3-5 Dependence of degradation on the repetition number of the gate AC pulse with fixed Vd of 15V

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3.3 Effect of the Transient Time

In this section, we would like to investigate the effect of the transient time for the device degradation under ON region gate AC operation with drain bias. Here, we examine the transient time dependence for the degradation at fixed number of the pulse repetition. Because the duration of signal high-level (T_Vgh) and signal low-level (T_Vgl) are set the same as 900 ns. Therefore, as various stress conditions are set, the frequency could vary and the period (T) is about 2 ~ 2.6 us as illustrated in Fig. 3-6. The experiment conditions are listed in Table 3-1.

Fig. 3-6 The various transient time of the gate pulse with fixed duration of Vgh and Vgl

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Table 3-1 Experiment conditions of transient time (T_Vgh = TVgl = 900ns)

Stress Conditions

Experiment

Gate Pulse Drain Bias Rising Time Falling Time Pulse Period

Pulse Repetition Number 100 ns 100 ns 2 us 300 ns 100 ns 2.2 us Rising Time Vg=0~15V Vd=15V 700 ns 100 ns 2.6 us 5.0E+07 100 ns 100 ns 2 us 100 ns 300 ns 2.2 us Falling Time Vg=0~15V Vd=15V 100 ns 700 ns 2.6 us 5.0E+07

For those stress conditions with the rising time Tr from 100 ns to 700 ns at a fixed falling time Tf of 100 ns, no significant change in mobility degradation ratio (MuS/

Mu0) is observed as shown in Fig. 3-7(a). Similarly, the degradation of the device has

no obvious difference when we change the falling time Tf from 100 ns to 700 ns as shown in Fig. 3-7(b).

Based on the results of the pulse repetition number dependence and the pulse transient time dependence, we suggest that the degradation occurs mainly owing to the swing range of the gate pulse repetition. Therefore, the degradation behavior of the gate pulse range is interesting to be examined. Then, we measure different gate pulse ranges for the stress to validate the assumption in the next section.

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0 100 200 300 400 500 600 700 800 0.0 0.2 0.4 0.6 0.8 1.0 M u S

/

M u 0 Rising Time (ns) Tr=100ns,Tf=100ns Tr=300ns,Tf=100ns Tr=700ns,Tf=100ns Tr

Fig. 3-7(a) Rising time dependence of the mobility degradation for AC stress with Vg of 0~15V and fixed Vd of 15V 0 100 200 300 400 500 600 700 800 0.0 0.2 0.4 0.6 0.8 1.0 M u S

/

M u 0 Falling Time (ns) Tr=100ns,Tf=100ns Tr=100ns,Tf=300ns Tr=100ns,Tf=700ns

Tf

Fig. 3-7(b) Falling time dependence of the mobility degradation for AC stress with Vg of 0~15V and fixed Vd of 15V

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3.4 Dependence on Gate Pulse Profile

3.4.1 Pulse Range

To investigate which range in gate voltage of the stress pulse dominates the degradation of the N-type poly-Si TFTs in the ON operation, the swing range is separated into two; one is the high-level range, and the other is the low-level range. We modulated the pulse swing by fixing the start voltages to the low-level and high-level of the gate pulse as shown in Fig. 3-8(a) and (b). Finally, we set the pulse swing fixed with different Vg level to further estimate the pulse range dependence for the degradation. The duty ratio and frequency of the gate pulse are 50 % and 500 kHz, respectively. In this section, we will present the experimental phenomena and discuss the degradation of the devices under various pulse range stress.

Fig. 3-8(a) The various high-levels of the gate pulse with fixed low-level voltage

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3.4.1.1 High-Level of the Gate Pulse

The AC stress conditions with various high-levels of the gate pulse (Vgh) are illustrated in Fig.3-8(a). The low-level of the gate pulse (Vgl) is fixed at 0 V while Vgh varies from 5 V to 20 V. The dependence of mobility degradation on various Vgh stress is shown in Fig. 3-9. It is observed that the degradation increases with the decrease in Vg swing. The result obtained is contrary to our expectation. It is presumed that the device degradation would be enhanced as the Vg swing increases. As mention in section 1.2.1, with the increase in gate voltage, the power dissipation in the device is becoming high. The power dissipation causes the increase of device temperature due to Joule heat, which is known as self-heating or thermal effect. The degradation features of self-heating effect are increase in the amount of

V

th shift and S.S change. In view of

this, the degradation dependences of

V

th shift and S.S change are shown in Fig. 3-10(a)

and (b).

0

5

10

15

20

0.0

0.2

0.4

0.6

0.8

1.0 Vg High Level (V)

M

u

S

/

M

u

0

Vg=0~5V

Vg=0~10V

Vg=0~15V

Vg=0~20V

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0

5

10

15

20

0.0

0.5

1.0

1.5

2.0

2.5

3.0 Vg High Level (V)

V

th

s

h

if

t

(V

)

Vg=0~5V

Vg=0~10V

Vg=0~15V

Vg=0~20V

Fig. 3-10(a) Dependence of Vth shift on various Vgh stress

0

5

10

15

20

0.0

0.1

0.2

0.3

0.4

0.5

0.6 Vg High Level (V)

S

.S

c

h

a

n

g

e

(

V

/d

e

c

)

Vg=0~5V

Vg=0~10V

Vg=0~15V

Vg=0~20V

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With the increase in Vg swing, no significant change is observed on S.S change. However, the

V

th shift is slightly increased for stress conditions of various Vgh. In the

case of AC stress, these results lead us to the suggestion that the degradation is dominated by the lower Vg level. Therefore, the degradation caused by lower Vg level will be examined in detail later.

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3.4.1.2 Low-Level of the Gate Pulse

To further evidence the lower Vg level is the dominant cause of degradation. The AC stress conditions with various Vgl are performed as illustrated in Fig.3-8(b). The Vgh is fixed at 15 V while Vgl varies from 0 V to 10 V. Figure 3-11 shows the dependence of degradation on Vgl stress. It is observed that the mobility degradation is the worst as Vgl is between 0 V and 5 V, which are around the threshold voltage (Vth)

of the device. On the other hand, the mobility is relatively less degraded for the gate voltage swinging between 10 V and 15 V.

0

2

4

6

8

10

0.0

0.2

0.4

0.6

0.8

1.0 Vg Low Level (V)

M

u

S

/

M

u

0

Vg=0~15V

Vg=2~15V

Vg=5~15V

Vg=10~15V

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The

V

th shift is obviously increased at Vgl of 2V as shown in Fig. 3-12(a).

However, S.S change is no significantly increased as shown in Fig. 3-12(b) For the stress conditions with various levels of the gate pulse, the results reveal that the degradation is more important in accordance with the lower level of the gate pulse when drain bias is present. Compared with unitary gate AC stress, i.e. the AC pulse is performed on the gate electrode with the source and drain grounded [3.1], this dependence is a unique feature to our knowledge.

0

2

4

6

8

10

0.0

0.5

1.0

1.5

2.0

2.5

3.0 Vg Low Level (V)

V

th

s

h

if

t

(V

)

Vg=0~15V

Vg=2~15V

Vg=5~15V

Vg=10~15V

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0

2

4

6

8

10

0.0

0.1

0.2

0.3

0.4

0.5

0.6 S

.S

c

h

a

n

g

e

(

V

/d

e

c

)

Vg Low Level (V)

Vg=0~15V

Vg=2~15V

Vg=5~15V

Vg=10~15V

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3.4.1.3 Effect of the pulse level

In this section, we will clarify the effect of the pulse level for the degradation dependence. The AC stress conditions of various Vg levels with fixed pulse swing are examined as shown in Fig. 3-13. The dependence of mobility degradation on various Vg levels with fixed pulse swing is shown in Fig. 3-14.

Fig. 3-13 The AC stress conditions of various Vg levels with fixed pulse swing

0~5 5~10 10~15 15~20 0~10 5~15 10~20 0~15 5~20 0.0 0.2 0.4 0.6 0.8 1.0 M u S / M u 0

Pulse Swing Range

Pulse Swing of 5V Pulse Swing of 10V Pulse Swing of 15V

(V)

Fig. 3-14 Dependence of mobility degradation on various Vg levels with fixed pulse swing

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It is observed that the degradation strongly depends on Vg level. The degradation is relieved as the Vg at high level range no matter the increase in pulse swing. The dependences of

V

th shift and S.S change are shown in Fig. 3-15(a) and (b), respectively.

It is obviously found that the

V

th shift and S.S change are increased at high level range.

The degradation behavior of Vg at high level range is similar to the case of DC self-heating effect as mentioned in section 1.2.1. In addition, the worst mobility degradation occurs at lower level of the gate pulse, especially for swing range around the Vth of the device. It means that the degradation behavior of Vg at low level range is

similar to the case of DC hot carrier effect as mentioned in section 1.2.1. The hot carrier is generated by impact ionization under the high electric field which is induced by high Vd and low Vg around Vth. Based on the results of the pulse level for the

degradation dependence, it occurs to us that the DC components of the AC stress waveform might play an important role. Therefore, in the next section, the degradation behaviors induced by DC components of the AC stress waveform will be further analyzed.

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Pulse Swing Range 0~5 5~10 10~15 15~20 0~10 5~15 10~20 0~15 5~20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Pulse Swing of 5V Pulse Swing of 10V Pulse Swing of 15V (V) V th s h if t (V )

Fig 3-15(a) Dependence of Vth shift on various Vg levels with fixed pulse swing

0~5 5~10 10~15 15~20 0~10 5~15 10~20 0~15 5~20 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Pulse Swing of 5V Pulse Swing of 10V Pulse Swing of 15V

Pulse Swing Range

S .S c h a n g e ( V /d e c ) (V)

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3.4.2 Duty Ratio

To study the degradation behavior induced by DC components of the AC stress waveform (Vgl and Vgh), we modulate the duty ratio from 25 % to 75 % to understand the relation during the different stress periods of single pulse. The duty ratio of the AC waveform (T_Vgl and T_Vgh) is illustrated in Fig. 3-16.

Fig. 3-16 Different stress duration of the Vg pulse level

For the stress pulse with fixed swing of 10 V as set in section 3.4.2.3, the dependences of mobility degradation on various duty ratios are shown in Fig. 3-17. It is observed that the serious degradation occurs at Vg of 0 V to 10 V and 5 V to 15 V with the decrease in duty ratio. In other words, the more degradation occurs when Vgl is around Vth of the device and stays longer. On the other hand, an opposite dependence

trend on various duty ratios is found at Vg swinging between 10 V and 20 V. The degradation is enhanced with the increase in duty ratio. Moreover, the increase in the amount of

V

th shift and S.S change are observed at the same pulse range for longer

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25

50

75

0.0

0.2

0.4

0.6

0.8

1.0 Duty Ratio (%)

M

u

S

/

M

u

0

Vg=0~10V

Vg=5~15V

Vg=10~20V

Fig. 3-17 Dependence of degradation on various duty ratios for the stress pulse with fixed swing of 10 V

25

50

75

0.0

0.5

1.0

1.5

2.0

2.5

3.0 V

th

s

h

if

t

(V

)

Duty Ratio (%)

Vg=0~10V

Vg=5~15V

Vg=10~20V

Fig. 3-18(a) Dependence of Vth shift on various duty ratios for the stress pulse with fixed swing of 10 V

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25

50

75

0.0

0.1

0.2

0.3

0.4

0.5

0.6 Duty Ratio (%)

S

.S

c

h

a

n

g

e

(

V

/d

e

c

)

Vg=0~10V

Vg=5~15V

Vg=10~20V

Fig 3-18(b) Dependence of S.S change on various duty ratios for the stress pulse with fixed swing of 10 V

Base on the results, the degradation behavior of higher Vg level is quite similar to the DC self-heating effect and is induced during the stress period of Vgh. As lower Vg level is around Vth and stays longer during the stress period of Vgl, the degradation

behavior is similar to the DC hot carrier effect. It is reasonable to suppose that the difference in duty ratio dependence is attributed to the difference in degradation mechanisms. Therefore, it is presumed that the DC components of the AC stress waveform are the dominant cause of degradation behaviors in this case of AC stress. For the reason, the degradation behavior induced by AC stress will be analyzed based on its DC offset.

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3.4.3 DC Offset of the AC Pulse

As mentioned in section 3.4.1 and 3.4.2, the AC pulse levels are the dominant cause of the degradation under ON region gate AC operation with drain bias. Moreover, the degradation behavior is similar to the case of DC stress effect. Then, considering the DC effects induced by the AC pulse, we will further discuss the DC components of the AC waveform. Since the gate AC waveform actually contains two DC components (Vgh and Vgl) and correspondingly lasts for different durations, we will extract the equivalent DC Vg of the AC pulse in simpler terms. Therefore, we use DC offset as the index for the AC pulse with different amplitudes and duty ratios. The index (VGO) is

proposed as follows,

DC Vg Offset (VGO) = Vgh * duty % + Vgl * (1 – duty %)

First, we examine the dependence of degradation on VGO under various pulse

ranges with fixed pulse swing and duty ratio as set in section 3.4.1.3. Next, the stress conditions as set in section 3.4.1.1 and 3.4.1.2 with various duty ratios are discussed based on VGO dependence.

3.4.3.1 Dependence on DC Offset of the AC Pulse with Fixed Swing Range

For the various pulse levels with fixed pulse swing, the relative VGO are listed in

Table 3-2. The dependence of mobility degradation on VGO under various pulse levels

with fixed pulse swing and duty ratio is shown in Fig. 3-19. For VGO below 15 V, it can

be observed that the trend of degradation distribution is gradually relieved as VGO

increases. Furthermore, the degradation is the worst at pulse range of 0~5 V, whose VGO is 2.5 V around

V

th of the device. On the other hand, the degradation is enhanced

with the increase in VGO as VGO is greater than 15 V, which are high DC components of

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Table 3-2 DC offset of various pulse ranges with fixed pulse swing and duty ratio

Stress Conditions

DC Vg Offset(VGO)

Experiment

Pulse Range Duty 50% Vg=0~5V 2.5V Vg=5~10V 7.5V Vg=10~15V 12.5V

Fixed Pulse Swing of 5V

Vg=15~20V 17.5V

Vg=0~10V 5V

Vg=5~15V 10V

Fixed Pulse Swing of 10V Vg=10~20V 15V 0 5 10 15 20 0.0 0.2 0.4 0.6 0.8 1.0 0 5 10 15 20 0.0 0.2 0.4 0.6 0.8 1.0 M u S / M u 0 V_GO (V) Fixed Swing 10V Vg=0~10V Vg=5~15V Vg=10~20V Fixed Swing 5V Vg=0~5V Vg=5~10V Vg=10~15V Vg=15~20V

Fig 3-19 Dependence of mobility degradation on VGO with fixed pulse swing of 5V and 10V

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The dependences of

V

th shift and S.S change are shown in Fig. 3-20(a) and (b),

respectively. For lower VGO, no significant changes are observed on

V

th shift and S.S

change. However, it is noted that the

V

th shift and S.S change are obviously increased

at VGO of 15 V and 17.5 V, which are corresponding to high DC components of the AC

waveform.

As previous mentioned in section 1.2.1, the DC hot carrier effect occurs at high Vd and low Vg around

V

th. Here, the stress condition with low VGO around

V

th and

high Vd reflects the similar degradation behavior. With the increase in VGO, the stress

conditions with high VGO and high Vd cause increase in the amount of

V

th shift and S.S

change. The degradation behavior reveals the features of the DC self-heating effect. According to the results, it is reasonable to suppose that the degradation behaviors under ON region gate AC stress with drain bias are attributed to the DC effects. The DC effects induced by the DC components of the AC waveform with drain bias are based on its DC offset. Therefore, it is essential to further study the DC effects induced by the DC components of the AC waveform with drain bias. In the next section, the dependences of degradation based on VGO are performed with various duty ratios of

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0 5 10 15 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Vg=0~5V Vg=5~10V Vg=10~15V Vg=15~20V V th s h ift (V ) V_GO (V) Vg=0~10V Vg=5~15V Vg=10~20V

Fixed Swing 5V Fixed Swing 10V

Fig 3-20(a) Dependence of Vth shift on VGO with fixed pulse swing of 5V and 10V

0 5 10 15 20 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Vg=0~5V Vg=5~10V Vg=10~15V Vg=15~20V S .S c h a n g e (V /d e c ) V_GO (V)

Fixed Swing 5V Fixed Swing 10V

Vg=0~10V Vg=5~15V Vg=10~20V

Fig 3-20(b) Dependence of S.S change on VGO with fixed pulse swing of 5V and 10V

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3.4.3.2 Dependence on DC Offset of the AC Pulse with Various Duty Ratio

For the stress conditions as set in section 3.4.1.1 and 3.4.1.2 with various duty ratios, the relative VGO are summarized in Table 3-3. Based on the experimental data,

we plot the mobility degradation of the device stressed as the VGO dependence as

shown in Fig. 3-21. It can be observed that the trend of degradation distribution is gradually relieved as VGO increases. For lower VGO around Vth of the device, the severe

mobility degradation occurs during the longer stress period of Vgl. It is supposed that the DC effect induced by Vgl of the gate pulse is the dominant cause of degradation. With the increase in duty ratio and Vg level, namely, VGO is increased, the mobility

degradation is relieved due to the influence of the Vgl is decreased. The dependences of

V

th shift and S.S change are shown in Fig. 3-22(a) and (b). It is found that no

significant changes are observed in

V

th shift and S.S change. As mentioned is the last

section,

V

th shift and S.S change are obviously increased at higher VGO, that is, above

15 V. In this case, the relative VGO are smaller than or equal to 15 V. Thus, the

degradation phenomena are not revealed.

Table 3-3 DC offset of various levels and duty ratios of AC Pulse

Stress Conditions

DC Vg Offset

Experiment

Pulse Range

Duty 25% Duty 50% Duty 75%

Vg=0~5V 1.25V 2.5V 3.75V

Vg=0~10V 2.5V 5V 7.5V

Vg=0~15V 3.75V 7.5V 11.25V

High-Level of the Gate Pulse

Vg=0~20V 5V 10V 15V

Vg=2~15V 5.25V 8.5V 11.75V

Vg=5~15V 7.5V 10V 12.5V

Low-Level of the Gate Pulse

(58)

0

2

4

6

8

10

12

14

16

0.0

0.2

0.4

0.6

0.8

1.0 M

u

S

/

M

u

0

V

_GO

(V)

Vg=0~5V

Vg=0~10V

Vg=0~15V

Vg=0~20V

Vg=2~15V

Vg=5~15V

Vg=10~15V

Fig 3-21 Dependence of mobility degradation on VGO with various levels and duty ratios of the gate pulse

V_GO(V) 0 2 4 6 8 10 12 14 16 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Vg=0~5V Vg=0~10V Vg=0~15V Vg=0~20V Vg=2~15V Vg=5~15V Vg=10~15V V th s h if t (V )

(59)

0 2 4 6 8 10 12 14 16 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Vg-0~5V Vg=0~10V Vg=0~15V Vg=0~20V Vg=2~15V Vg=5~15V Vg=10~15V V_GO(V) S .S c h a n g e ( V /d e c )

Fig 3-22(b) Dependence of S.S change on VGO with various levels and duty ratios of the gate pulse