Conclusions

We had investigated the strain technique impact on device performance and reliability. In this work, devices with 700A HS CESL possess efficient mobility enhancement and hot-carrier reliability immunity than devices with 1100A HS CESL.

And we found that increasing the LOD will decrease the STI-induced compressive stress and enhance the device’s mobility especially for wide gate width devices. For narrow width devices, the impact of LOD will be unapparent due to the STI-induced edge leakage. In comparison with BC-SOI device, it was found that lower hot-carrier induced device degradation was happened on FB-SOI. We propose a method using BC-SOI device with I_B=0 to monitor V_B for SOI device. With body potential inspection for 90 nm SOI nMOSFETs, the narrower channel width in BC-SOI nMOSFETs will induce edge current, thus enhancing hot-carrier-induced device’s degradation. For FB-SOI nMOSFET, body potential suppresses electric field between body and drain, thus alleviates the hot-carrier-induced device degradation. Moreover, narrower width device of FB-SOI possesses lower body potential, causing higher electric field between body and drain, thus enhancing device’s capability and hot-carrier-induced device degradation apparently.

For RFIC system, the related active components (diode and MOSFETs) and passive components (resistors, capacitors, inductor and transmission lines) will affect the performance of the RFIC. In this work, efficient extracting method for wafer-level and packing-level inductor as well as MIM capacitor are presented. The lumped element equivalent model of the inductor with or without Flip-Chip BGA packaging has been introduced. The return-loss (S₁₁), insertion loss (S₂₁) and quality factor (Q) were fully

characterized. Reasonable modeling and measurement have been fitted well up to 12 GHz. The extracting method shown in this work can be repeated to perform different structure of integrated passive component and to evaluate RF performance of package-level passive components using in System-in-Package and module area.

Fig.2-1 Diagram of Hot Carrier Effect

Fig.2-2 Semiconductor Parameter Analyzer HP4156B

Fig.2-3 Agilent ICS Software

Fig.2-4 DC Probe Station

0.0 0.2 0.4 0.6 0.8 1.0 1.2 0

2 4 6 8 10 12 14 16

I

_DLIN

I

_DSAT

I

D

( μ A/ μ m) )

V

_D

(volts)

Vg=0.3 V Vg=0.75 V Vg=1.2 V

Fig.2-5 I

_D

-V

_D

characteristics with different gate voltage

Fig.2-6 I

_D

-V

_G

and G

_M

-V

_G

characteristics

BOX X Z

STI induced stress

STI

HS CESL induced stress HS CESL layer

HS CESL induced stress HS CESL layer

STI

STI induced stress

STI

HS CESL induced stress

HS CESL layer STI induced stress

STI

HS CESL induced stress HS CESL layer

STI

HS CESL induced stress

STI

HS CESL induced stress HS CESL layer

Fig.2-7 The schematic structure of SOI nMOSFETs( the HS CESL induced tensile stress and STI induced compressive stress)

Fig.2-8 I -V characteristics with different HS CESL

0.0 0.5 1.0 0

200 400

600 BC-SOI nMOSFET

L / W = 0.09 / 10

μ

m V

D

=0.05 V

high stress 1100A high stress 700A SiN 380

Fig.2-9 G

_M

-(V

_G

-V

_TH

) characteristics with different HS CESL

Fig.2-10 I

_D

-V

_G

characteristics with different HS CESL

Fig.2-11 I

_D

-V

_D

with different Stress time of 1100A

-0.5 0.0 0.5 1.0 0

200 400

600 HS CESL 1100A BC-SOI

Fig.2-13 G

_M

characteristics with different Stress time of 1100A

Fig.2-14 G

_M

characteristics with different Stress time of 700A

0.0 0.5 1.0

0

90 nm BC-SOI nMOSFETS Ref:SiN 380 W=10 μ m

Fig.2-15 I

_D

-Width characteristics with different HS CESL

Fig.2-16 V

_T

-Width characteristics with different HS CESL

Fig.2-17 G

_M

-Width characteristics with different HS CESL

Fig.2-18 I

_D

-LOD characteristics with different HS CESL

0

90 nm BC-SOI nMOSFETS Ref:SiN 380 W=10

μ

m

90 nm BC-SOI nMOSFETS Ref:SiN 380

W

Fig.2-19 G

_M

-LOD characteristics with different HS CESL

Fig.2-20 The schematic structure of SOI(vertical view) 0

90 nm BC-SOI nMOSFETS Ref:SiN 380

G_m=483 S/μm

LOD ( μ m)

Δ G

m MAX

( % )

^HS:1100A HS:700A

SiN 380

Fig.2-21 I

_G

-LOD characteristics with different HS CESL

Fig.2-22 V

_TH

-LOD characteristics with different HS CESL

0.01

Fig.2-23 Leakage path impact on V

_B

of nMOSFETs on PD-SOI Substrate

Substrate BOX

n ⁺ n ⁺

V B

STI

Vs I ^G V ^D

I ^EL I ^SB I ^DB

I ^II

0.0 0.2 0.4 0.6 0.8 1.0

0 100 200 300 400 500

V

_G

= 1V

Dr ai n C u rr ent I

D

(

μ

A/

μ

m)

L= 90nm

V

_D

(Volts)

W=1.2μ

m

W=5 μ

m

W=10 μ

m

Fig.2-25 V

_TH

characteristics with different width

Fig.2-26 I

_DSAT

degradation with different Stress time

0 2 4 6 8 10

0.530 0.535 0.540 0.545 0.550

L= 90nm

V

th

(v o lts )

Width ( μ m)

0 100 200 300

0 1 2 3 4 5

Stress Time (min)

W=1.2 μ

m

W=5 μ

m

W=10 μ

m Stress Voltage:

V

_G

=V

_D

=1.5V

BC-SOI, L

_G

=90nm

Δ I

Dsat

(% )

Fig.2-27 I

_G

degradation with different Stress time

Fig.2-28 I

_D

-V

_D

characteristics with different width for IB=0

0 100 200 300

Fig.2-29 G

_M

-(V

_G

-V

_TH

) characteristics with different width

Fig.2-30 V

_B

-V

_D

characteristics with different width

-0.4 0.0 0.4 0.8

Fig.2-31 V

_B

-V

_G

characteristics with different width

Fig.2-32 I

_D

-V

_G

characteristics with different width

-0.4 0.0 0.4 0.8 1.2

Fig.2-33 Width effect on lifetime of 90nm BC-SOI and FB-SOI nMOSFETs

0.5 1.0 1.5 2.0 2.5 3.0 3.5

10

²

10

³

10

⁴

10

⁵

BC-SOI

L

_G

=90nm V

_D

=1.5V ,

Δ

I

_D

=5%

L ife tim e (m in )

1/V

_G

(volts)

W=10 μ

m

W=5 μ

m

W=1.2 μ

m

0.5 1.0 1.5 2.0 2.5 3.0 3.5 10

³

10

⁴

10

⁵

FB-SOI L

_G

=90nm

stress V

_d

=1.5V ,

Δ

I

_D

=5%

L ife tim e (m in )

1/V

_G

(1/volts)

W=10

μ

m

W=5

μ

m

W=2

μ

m

Inductor A 7.08 nH

Inductor B 5.221 nH

Capacitor A 0.485 pF

Capacitor B 10.466 pF

Fig.3-1 Size Table

Fig.3-2 Inductor Model

Q Efficiency

Inductor ₁₁

11

( ) ( ) imag Y

real Y

−

11

( 1 ) imag Y

Capacitor ₂₁

21

( ) ( ) imag Y

real Y

( 21) imag Y

−

Fig.3-3 Formula of Q, Inductance and Capacitance

Fig.3-4 Three interconnection type of BGA structures

Fig.3-5 RF Probe Station

Fig.3-6 Network Analyzer 8364B

Fig.3-7 Microphotograph of an integrated spiral inductor

Fig.3-8 Microphotograph of a MIM capacitor

Fig.3-9 Top view of completed flip-chip BGA

Fig.3-10 Bottom of with completed flip-chip BGA

Fig.3-11 Lumped element model of inductor before packaging

Fig.3-12 Lumped element model of capacitor before packaging

C

p

R

p

L

_S

R

S1

R

S2

C

S1

C

S2

C

_S

R

_S

L

_S

C

_S1

C

_S2

Fig.3-13 Lumped element model of inductor after flip-chip packaging

Fig.3-14 Lumped element model of capacitor after flip-chip

Cp

Fig.3-15 Inductor A before package

Fig.3-16 Inductor A after flip-chip package

0 2 4 6 8 10 12

Fig.3-17 Measured and simulated S

₁₁

magnitude characteristic of spiral inductor A

Fig.3-18 Measured and simulated S

₂₁

magnitude characteristic of spiral inductor A

0 2 4 6 8 10 12

Fig.3-19 Measured and simulated S

₁₁

phase characteristic of spiral inductor A

Fig.3-20 Measured and simulated S

₂₁

phase characteristic of

spiral inductor A

Fig.3-21 Measured and simulated smith chart for S

₁₁

characteristic of spiral inductor A

Fig.3-22 Measured and simulated smith chart for S

₂₁

Inductor A S11 Before Package-Measure Before Package-Simulate After Package-Measure After Package-Simulate

Inductor A S21 Before Package-Measure Before Package-Simulate After Package-Measure After Package-Simulate

Fig.3-23 Measured and simulated inductance for spiral inductor A

Fig.3-24 Measured and simulated quality factor for spiral

inductor A

Fig.3-25 Inductor B before packaging

Fig.3-26 Inductor B after flip-chip package

Fig.3-27 Measured and simulated S

₁₁

magnitude characteristic of spiral inductor B

Fig.3-28 Measured and simulated S

₂₁

magnitude characteristic of spiral inductor B

0 2 4 6 8 10 12

Fig.3-29 Measured and simulated S

₁₁

phase characteristic of spiral inductor B

Fig.3-30 Measured and simulated S

₂₁

phase characteristic of

0 2 4 6 8 10 12

Fig.3-31 Measured and simulated smith chart for S

₁₁

characteristic of spiral inductor B

Fig.3-32 Measured and simulated smith chart for S

₂₁

characteristic of spiral inductor B

Inductor B S11 Before Package-Measure Before Package-Simulate After Package-Measure After Package-Simulate

Inductor B S21 Before Package-Measure Before Package-Simulate After Package-Measure After Package-Simulate

Fig.3-33 Measured and simulated inductance for spiral inductor B

Fig.3-34 Measured and simulated quality factor for spiral

0 3 6 9 12 15 18 21 24

Fig.3-35 Capacitor A before packaging

Fig.3-36 Capacitor A after flip-chip package

Fig.3-37 Measured and simulated S

₁₁

magnitude characteristic of MIM capacitor A

Fig.3-38 Measured and simulated S

₂₁

magnitude

0 2 4 6 8 10 12

Fig.3-39 Measured and simulated S

₁₁

phase characteristic of MIM capacitor A

Fig.3-40 Measured and simulated S

₂₁

phase characteristic of

MIM capacitor A

Fig.3-41 Measured and simulated smith chart for S

₁₁

characteristic of MIM capacitor A

Fig.3-42 Measured and simulated smith chart for S

₂₁

characteristic of MIM capacitor A

Capacitance A S11 Before Package-Measure Before Package-Simulate After Package-Measure After Package-Simulate

Capacitance A S21 Before Package-Measure Before Package-Simulate After Package-Measure After Package-Simulate

Fig.3-43 Measured and simulated capacitance for MIM capacitor A

Fig.3-44 Measured and simulated quality factor for MIM capacitor A

0 2 4 6 8 10 12 14 16 18 20 22 24 -14 -12

-10 -8 -6 -4 -2 0 2 4 6 8

Capacitance A

Ceff

Frequency(GHz)

Before Package-Measure Before Package-Simulate After Package-Measure After Package-Simulate

0 2 4 6 8 10 12 14

-10 10 20 30 40 50 60 70 80 90 0 100

Capacitance A

Q

Frequency(GHz)

Before Package-Measure Before Package-Simulate

Fig.3-45 Capacitor B before packaging

Fig.3-46 Capacitor B after flip-chip package

Fig.3-47 Measured and simulated S

₁₁

magnitude characteristic of MIM capacitor B

Fig.3-48 Measured and simulated S

₂₁

magnitude characteristic of MIM capacitor B

0 2 4 6 8 10 12

Fig.3-49 Measured and simulated S

₁₁

phase characteristic of MIM capacitor B

Fig.3-50 Measured and simulated S

₂₁

phase characteristic of

0 2 4 6 8 10 12

Fig.3-51 Measured and simulated smith chart for S

₁₁

characteristic of MIM capacitor B

Fig.3-52 Measured and simulated smith chart for S

₂₁

characteristic of MIM capacitor B

Capacitance B S11 Before Package-Measure Before Package-Simulate After Package-Measure After Package-Simulate

Capacitance B S21 Before Package-Measure Before Package-Simulate After Package-Measure After Package-Simulate

Fig.3-53 Measured and simulated capacitance for MIM capacitor B

Fig.3-54 Measured and simulated quality factor for MIM

capacitor B

LS

Fig.3-55 Parameters Table

References

[1] K. K. Young, "Short-channel effect in fully depleted SOI MOSFETs," Electron Devices, IEEE Transactions on, vol. 36, pp. 399-402, 1989.

[2] T. Tsuchiya, Y. Sato, and M. Tomizawa, "Three mechanisms determining short-channel effects in fully-depleted SOI MOSFETs," Electron Devices, IEEE Transactions on, vol. 45, pp. 1116-1121, 1998.

[3] T. Y. Chan, J. Chen, P. K. Ko, and C. Hu, "The impact of gate-induced drain leakage current on MOSFET scaling," 1987.

[4] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr,

"Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors," 2000.

[5] H. M. Nayfeh, C. W. Leitz, A. J. Pitera, E. A. Fitzgerald, J. L. Hoyt, and D. A.

Antoniadis, "Influence of high channel doping on the inversion layer electron mobility in strained silicon n-MOSFETs," Electron Device Letters, IEEE, vol. 24, pp. 248-250, 2003.

[6] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K.

Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M.

Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, "A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors," 2003.

[7] C. Mazure and I. Cayrefourcq, "Status of device mobility enhancement through strained silicon engineering," 2005.

[8] N. M. Nguyen and R. G. Meyer, "Si IC-compatible inductors and <e1>LC</e1>

passive filters," Solid-State Circuits, IEEE Journal of, vol. 25, pp. 1028-1031, 1990.

[9] R. R. Tummala, "Packaging: past, present and future," 2005.

[10] R. G. Werner, D. R. Frear, J. DeRosa, and E. Sorongon, "Flip chip packaging,"

1999.

[11] R. J. Pratap, D. Staiculescu, S. Pinel, J. Laskar, and G. S. May, "Modeling and

networks," Advanced Packaging, IEEE Transactions on [see also Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on], vol. 28, pp. 71-78, 2005.

[12] G. G. Shahidi, B. Davari, T. J. Bucelot, P. A. Ronsheim, P. J. Coane, S. Pollack, C.

R. Blair, B. Clark, and H. H. Hansen, "Indium channel implant for improved short-channel behavior of submicrometer NMOSFETs," Electron Device Letters, IEEE, vol. 14, pp. 409-411, 1993.

[13] S. Ogura, C. F. Codella, N. Rovedo, J. F. Shepard, and J. Riseman, "A half micron MOSFET using double implanted LDD," 1982.

[14] Y. Taur, S. Wind, Y. J. Mii, Y. Lii, D. Moy, K. A. Jenkins, C. L. Chen, P. J. Coane, D. Klaus, J. Bucchignano, M. Rosenfield, M. G. R. Thomson, and M. Polcari,

"High performance 0.1 &mu;m CMOS devices with 1.5 V power supply," 1993.

[15] 賴佑生,"Body Potential Measurement Methods and Pocket Implant Effect on PDSOI Devices," 國立交通大學 碩士論文, 94 學年度.

[16] 田昆玄, "Characteristics and Hot Carrier Reliability of n-channel Lateral Diffused Metal Oxide Semiconductor (LDMOS) Transistors with Different NDD Dosage,"

國立成功大學 碩士論文, 94 學年度..

[17] K. Goto, S. Satoh, H. Ohta, S. Fukuta, T. Yamamoto, T. Mori, Y. Tagawa, T.

Sakuma, T. Saiki, Y. Shimamune, A. Katakami, A. Hatada, H. Morioka, Y.

Hayami, S. Inagaki, K. Kawamura, Y. Kim, H. Kokura, N. Tamura, N. Horiguchi, M. Kojima, T. Sugii, and K. Hashimoto, "Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs," 2004.

[18] J. Welser, J. L. Hoyt, and J. F. Gibbons, "Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors," Electron Device Letters, IEEE, vol. 15, pp. 100-102, 1994.

[19] J. F. Zhang, H. K. Sii, G. Groeseneken, and R. Degraeve, "Hole trapping and trap generation in the gate silicon dioxide," Electron Devices, IEEE Transactions on, vol. 48, pp. 1127-1135, 2001.

[20] T. Irisawa, T. Numata, N. Sugiyama, and S. Takagi, "On the origin of increase in substrate current and impact ionization efficiency in strained-Si n- and p-MOSFETs," Electron Devices, IEEE Transactions on, vol. 52, pp. 993-998,

2005.

[21] V. Chan, R. Rengarajan, N. Rovedo, J. Wei, T. Hook, P. Nguyen, C. Jia, E. Nowak, C. Xiang-Dong, D. Lea, A. Chakravarti, V. Ku, S. Yang, A. Steegen, C. Baiocco, P.

Shafer, N. Hung, H. Shih-Fen, and C. Wann, "High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering," 2003.

[22] K. Ohe, S. Odanaka, K. Moriyama, T. Hori, and G. Fuse, "Narrow-width effects of shallow trench-isolated CMOS with n⁺-polysilicon gate," Electron Devices, IEEE Transactions on, vol. 36, pp. 1110-1116, 1989.

[23] G. Jing-Feng and P. C. H. Chan, "Flip-chip based 3-D high-Q integrated inductors," 2004.

[24] W. Z. Cai, S. C. Shastri, M. Azam, C. Hoggatt, G. H. Loechelt, G. M. Grivna, Y.

Wen, and S. Dow, "Development and extraction of high-frequency SPICE models for metal-insulator-metal capacitors," 2004.

[25] T. S. Horng, S. M. Wu, J. Y. Li, C. T. Chiu, and C. P. Hung, "Electrical performance improvements on RFICs using bump chip carrier packages as compared to standard small outline packages," 2000.

[26] C. P. Yue and S. S. Wong, "Physical modeling of spiral inductors on silicon,"

Electron Devices, IEEE Transactions on, vol. 47, pp. 560-568, 2000.

[27] J. Piquet, O. Cueto, F. Charlet, M. Thomas, C. Bermond, A. Farcy, J. Torres, and B. Flechet, "Simulation and characterization of high-frequency performances of advanced MIM capacitors," 2005.

[28] J. D. Arnould, P. Benech, S. Cremer, J. Torres, and A. Farcy, "RF MIM capacitors using Si/sub 3/N/sub 4/ dielectric in standard industrial BiCMOS technology,"

2004.

[29] H. Tzyy-Sheng, P. Kang-Chun, J. Je-Kuan, and T. Yu-Shun, "S-parameter formulation of quality factor for a spiral inductor in generalized two-port configuration," Microwave Theory and Techniques, IEEE Transactions on, vol. 51, pp. 2197-2202, 2003.

[30] U. Pfeiffer and B. Welch, "Equivalent circuit model extraction of flip-chip ball

Components Letters, IEEE, vol. 15, pp. 594-596, 2005.

在文檔中 先進主被動元件的分析與模型建立 (頁 39-91)