先進主被動元件的分析與模型建立

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(1)國立高雄大學電機工程學系(研究所) 碩士論文. 先進主被動元件的分析與模型建立 The analysis and modeling of advanced MOSFET and passive component. 研究生：許家維撰指導教授：葉文冠. 中華民國 96 年 6 月.

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(3) 先進主被動元件的分析與模型建立指導教授：葉文冠博士（教授）國立高雄大學電機工程學系. 學生：許家維國立高雄大學電機工程學所. 摘要在本篇論文中，我們探討兩種因結構與材料所造成不同之應力對於90奈米SOI 元件在<100>平面之矽基板上的載子遷移率的影響，此兩種應力分別為因高應力觸孔蝕刻停止層(HS CESL)厚度引起的拉伸應力，和因幾合學(擴散長度和閘極寬度) 所引起的壓縮應力。此外，我們也會觀察不同厚度的高應力觸孔蝕刻停止層所造成的不同應力，對元件的熱載子退化效應之影響，以及所造成元件缺陷的效應。本論文中，我們發現較窄的閘極寬度下，會有較高的操作驅動力因為邊緣電場效應，而且會造成較大的壓縮應力垂直於通道方向。且對於較短的擴散長度元件，會因為較嚴重的平行通道方向上之壓縮硬力，而使的元件效能退化。在本篇論文的第二部份，我們描述螺旋電感和 MIM 電容的等效電路模型，不但從螺旋電感中萃取等效π模型，也從 MIM 電容中萃取等效電路。最後我們討論對於此兩種被動元件經過覆晶球柵陣列封裝後的改變，更進一步的我們建立相關元件之封裝模型，來萃取與模擬封裝過後的電性參數。關鍵字：應力技術、螺旋電感、MIM 電容、電路模型、覆晶球柵陣列封裝. I.

(4) The analysis and modeling of advanced MOSFET and passive component Advisor(s): Dr.(Professor) Wen-Kuan Yeh Department of Electrical Engineering National University of Kaohsiung Student: Chia-Wei Hsu Department of Electrical Engineering National University of Kaohsiung ABSTRACT In this work, the thickness effects of high-tensile-stress contact etch stop layer (HS CESL) and impact of layout geometry (length of diffusion and gate width) on mobility enhancement of <100>/(100) 90 nm SOI nMOSFETs were studied. Additionally, we also inspected hot-carrier-induced device’s degradations with various thickness of HS CESL. We found that higher channel mobility can be obtained for device with thicker CESL layer. However, there is a limitation of CESL thickness because a serious stress-induced defect also happens on device with thicker CESL, resulting in device degradation. And we found that devices with narrow gate widths possess higher driving capacity because of larger fringing electric fields and higher compressive stress in direction perpendicular to the channel. Owing to the more serious impact of compressive stress in direction parallel to the channel, the device performance was degraded particularly for devices with shorter LOD. In the second part of this paper, we develop an equivalent circuit model for spiral inductor and MIM capacitor. On the one hand, we show an original method for extracting equations of conventional π model in spiral inductor and MIM capacitor before and after flip-chip Ball Grid Array Package (FC-BGA). Finally, related electrical parameters of package model for these passive elements were used to simulate this structure configuration. Keywords: Strain technology, Spiral inductor, MIM capacitor, Flip-chip Ball Grid Array Package(FC-BGA) II.

(5) Contents Chapter I. Introduction..…………………………………………………………....1. 1.1. Background……………………………………………………………………1. 1.2. Organization...…………………………………………………………………4. Chapter II 2.1. SOI nMOSFETs………………………………………………………..5. SOI nMOSFETs structure...…………………………………………………...6 2.1.1 The basic characteristic of SOI nMOSFETs................................………7 2.1.2 The basic hot carrier effect………………….……….…………………7. 2.2. Experiment………………...………………………………………………..…8 2.2.1 ID-VD measurement……………………………………………....……..8 2.2.2 ID-VG measurement.…………………………………………………….9 2.2.3 VT extraction…………………................................................................9. 2.3. Results…...………………...………………………………………..………..10 2.3.1 The Thickness Effect of HS CESL film on SOI nMOSFETs......……..11 2.3.2 The Effect of Devices Geometry on SOI nMOSFETs.………………..13 2.3.3 The Impact of Body-Potential on SOI nMOSFETs…………………...15. 2.4. Summary....……………………………………………………………..........17. Chapter III Modeling and Package Theory..........................................................18 3.1. Modeling Theory.……………………………………………………..……...18. 3.2. Ball Grid Array (BGA) Package…………………………….………..……...20 3.2.1 What is a BGA Package.……………………………………………....20 3.2.2 Flip Chip BGA……………………...………………………..………..21. Chapter IV Integrate Passive Components Modeling……………………..…..22 4.1. Experiment.……………………………………………………….…..……...23. 4.2. Wafer Level and Packaging Level Modeling.....…………….…………...…..24 4.2.1 Wafer Level.……………………………………...…………………....24 4.2.2 Packaging……………………...……………………………..………..25. III.

(6) 4.3. Spiral Silicon-Base Inductor and MIM Capacitor ………………………..…26 4.3.1 Spiral Silicon-Base Inductor...…………………………...…………....26 4.3.2 MIM Capacitor……………………...………………………..………..27. Chapter V. Conclusions.…………………………………………………...………29. References……………………………...………………...……………...…………..…77. IV.

(7) Figure Captions. Figure2.1. Diagram of Hot Carrier Effect……………………………….……...………31. Figure2.2. Semiconductor Parameter Analyzer HP4156B……………………..………32. Figure2.3. Agilent ICS Software…………………..…………………………...………33. Figure2.4. DC Probe Station…………………………………………….……...………34. Figure2.5. ID-VD characteristics with different gate voltage…………………………...35. Figure2.6. ID-VG and GM-VG characteristics…………………………………...………35. Figure2.7. The schematic structure of SOI nMOSFETs(the HS CESL induced tensile. stress and STI induced compressive stress) …………………………………......………36 Figure2.8. ID-VD characteristics with different HS CESL…………………………...…36. Figure2.9. GM-(VG-VTH) characteristics with different HS CESL……………………..37. Figure2.10 ID-VG characteristics with different HS CESL……………………….……37 Figure2.11 ID-VD with different Stress time of 1100A……………………………...…38 Figure2.12 ID-VD with different Stress time of 700A……………………………….…38 Figure2.13 GM characteristics with different Stress time of 1100A………………...…39 Figure2.14 GM characteristics with different Stress time of 700A…………….………39 Figure2.15 ID-Width characteristics with different HS CESL……………………....…40 Figure2.16 VTH-Width characteristics with different HS CESL……….....................…40 Figure2.17 GM-Width characteristics with different HS CESL…………………......…41 Figure2.18 ID-LOD characteristics with different HS CESL………..........................…41 Figure2.19 GM-LOD characteristics with different HS CESL………...….……………42 Figure2.20 The schematic structure of SOI(vertical view) ………............................…42 Figure2.21 IG-LOD characteristics with different HS CESL………...…….…………..43 Figure2.22 VTH-LOD characteristics with different HS CESL………...……………...43 Figure2.23 Leakage path impact on VB of nMOSFETs on PD-SOI Substrate……...…44 Figure2.24 ID-VD characteristics with different width………...……………………….44 Figure2.25 VTH characteristics with different width………...…………………………45 Figure2.26 IDSAT degradation with different Stress time………………………….....…45 Figure2.27 IG degradation with different Stress time………...………………………...46. V.

(8) Figure2.28 ID-VD characteristics with different width for IB=0……………….........…46 Figure2.29 GM-(VG-VTH) characteristics with different width………...………………47 Figure2.30 VB-VD characteristics with different width………...……………………...47 Figure2.31 VB-VG characteristics with different width………...……………………...48 Figure2.32 ID-VG characteristics with different width………...……………….………48 Figure2.33 Width effect on lifetime of 90nm BC-SOI and FB-SOI nMOSFETs…...…49 Figure3.1. Size Table………………………………………………………………...…50. Figure3.2. Inductor Model…………………………………………………………...…50. Figure3.3. Formula of Q, Inductance and Capacitance……………………………...…51. Figure3.4. Three different interconnection type of BGA structures………………....…51. Figure3.5. RF Probe Station…………………………………………………….…...…52. Figure3.6. Network Analyzer 8364B…………………………………………...…...…52. Figure3.7. Microphotograph of an integrated spiral inductor……………………......…53. Figure3.8. Microphotograph of a MIM capacitor…………………………………...…53. Figure3.9. Top view of completed flip-chip BGA………………………………......…54. Figure3.10 Bottom of with completed flip-chip BGA………………………….…...…54 Figure3.11 Lumped element model of inductor before packaging……………….....…55 Figure3.12 Lumped element model of capacitor before packaging………...............…55 Figure3.13 Lumped element model of inductor after flip-chip packaging……….....…56 Figure3.14 Lumped element model of capacitor after flip-chip packaging…….…...…56 Figure3.15 Inductor A before packaging………........................................................…57 Figure3.16 Inductor A after flip-chip package……………………………………....…57 Figure3.17 Measured and simulated S11 magnitude characteristic of spiral inductor A.58 Figure3.18 Measured and simulated S21 magnitude characteristic of spiral inductor A.58 Figure3.19 Measured and simulated S11 phase characteristic of spiral inductor A…….59 Figure3.20 Measured and simulated S21 phase characteristic of spiral inductor A….…59 Figure3.21 Measured and simulated smith chart for S11 characteristic of spiral inductor A………………………………………………………………………………………….60 Figure3.22 Measured and simulated smith chart for S21 characteristic of spiral inductor A………………………………………………………………………………………….60 Figure3.23 Measured and simulated inductance for spiral inductor A……………..….61. VI.

(9) Figure3.24 Measured and simulated quality factor for spiral inductor A…………..….61 Figure3.25 Inductor B before packaging………........................................................…62 Figure3.26 Inductor B after flip-chip package……………………………………....…62 Figure3.27 Measured and simulated S11 magnitude characteristic of spiral inductor B.63 Figure3.28 Measured and simulated S21 magnitude characteristic of spiral inductor B.63 Figure3.29 Measured and simulated S11 phase characteristic of spiral inductor B…….64 Figure3.30 Measured and simulated S21 phase characteristic of spiral inductor B….....64 Figure3.31 Measured and simulated smith chart for S11 characteristic of spiral inductor B………………………………………………………………………………………….65 Figure3.32 Measured and simulated smith chart for S21 characteristic of spiral inductor B………………………………………………………………………………………….65 Figure3.33 Measured and simulated inductance for spiral inductor B……………..….66 Figure3.34 Measured and simulated quality factor for spiral inductor B…………..….66 Figure3.35 Capacitor A before packaging……………………………………………..67 Figure3.36 Capacitor A after flip-chip package………………………………………..67 Figure3.37 Measured and simulated S11 magnitude characteristic of MIM capacitor A68 Figure3.38 Measured and simulated S21 magnitude characteristic of MIM capacitor A68 Figure3.39 Measured and simulated S11 phase characteristic of MIM capacitor A……69 Figure3.40 Measured and simulated S21 phase characteristic of MIM capacitor A……69 Figure3.41 Measured and simulated smith chart for S11 characteristic of MIM capacitor A………………………………………………………………………………………….70 Figure3.42 Measured and simulated smith chart for S21 characteristic of MIM capacitor A………………………………………………………………………………………….70 Figure3.43 Measured and simulated capacitance for MIM capacitor A…………...…..71 Figure3.44 Measured and simulated quality factor for MIM capacitor A……………..71 Figure3.45 Capacitor B before packaging……………………………………………..72 Figure3.46 Capacitor B after flip-chip package………………………………………..72 Figure3.47 Measured and simulated S11 magnitude characteristic of MIM capacitor B73 Figure3.48 Measured and simulated S21 magnitude characteristic of MIM capacitor B73 Figure3.49 Measured and simulated S11 phase characteristic of MIM capacitor B……74 Figure3.50 Measured and simulated S21 phase characteristic of MIM capacitor B……74. VII.

(10) Figure3.51 Measured and simulated smith chart for S11 characteristic of MIM capacitor B………………………………………………………………………………………….75 Figure3.52 Measured and simulated smith chart for S21 characteristic of MIM capacitor B………………………………………………………………………………………….75 Figure3.53 Measured and simulated capacitance for MIM capacitor B……...………..76 Figure3.54 Measured and simulated quality factor for MIM capacitor B……………..76 Figure3.55 Parameters Table………………………………………….........…………..77. VIII.

(11) Chapter I Introduction. Nowadays, the development of wireless technology grows rapidly. There are many applications in consumer electronics, such as Cellular Phone, Wireless LAN, Bluetooth, etc. Thus, wireless application becomes necessary in our lives. For wireless application, the radio frequency integrated circuit (RFIC) is key system. In order to design a high performance RFIC, it is important to analysis the components inside the circuit and improve its characteristic. How to design a light, small, and fast IC is the dream for IC industry, which lowering the costs, saving area and more friendly. However, it is a challenge to design an efficient component for RFIC. The components in RFIC are made of two categories, active components and passive components. The active components are diode, MOSFETs, and bipolar. And resistors, capacitors, inductors and transmission lines as passive components. These elements will affect the performance of the RFIC. Thus, the purpose of this paper is analyzing and extracting the properties of above elements, then modeling these components for RFIC design.. 1.1 Background In order to realize high performance MOS integrated circuit, the dimensions of MOSFETs have continued to scale down. Consequently, further scaling of MOSFETs is important to achieve higher-performance. As the channel length and gate oxide thickness are scaled down, short-channel effects (SCE) becomes more severe [1]. SCE causes the dependence of device characteristic, such as threshold voltage. SCE can be physically. 1.

(12) explained by the drain-induced barrier lowering (DIBL) effect. The barrier height for channel of the source near the surface is lowered by the drain electric field as the channel length becomes shorter. This increases the number of carriers injected into the channel from the source. As a result, the drain off-current increases, and the threshold voltage is lowered in shorter channel MOSFETs. The barrier height is affected by drain voltage in addition to gate voltage for shorter channel MOSFETs. It degrades the controllability of the gate voltage to drain current, which leads to the degradation of the subthreshold slope and the increase in drain off-current. It is a solution of preventing SCE to thin gate oxide and shallow source/drain layers [2]. However, with thin gate oxide, the gate direct tunneling current and the gate induced drain leakage current would become more apparent. Minimization of transistor off-state leakage current is an especially important issue for low-power circuit application. The leakage current for very thin gate oxide is the gate-induced drain leakage (GIDL) current caused by band-to-band tunneling in the gate/drain overlap region [3]. GIDL imposes a constraint for gate-oxide thickness scaling because the voltage required causing this band-to-band current decreases with decreasing gate oxide thickness. A shallow channel dopant profile formed by low-energy channel implantation is found to suffer from punch-through leakage. By simply using channel implantation energy, a properly deep channel dopant profile can be formed to result in a better control of short channel effects. In order to suppress the short channel effects by increasing in channel doping, it is difficult to maintain high drive current density due to the degradation of carrier mobility in channel region by higher ionized impurity scattering [4][5]. Therefore, high mobility technology is desired to achieve high performance devices. The used of strain technique to improve mobility has been known. 2.

(13) for years and many channel-strained technologies have been proposed. These strain technologies accompany an increase of significant process steps in conventional Si process, e.g., relaxed SiGe layer in the source and drain regions. A simple way that enhances devices mobility without accompanying the increase of process steps was required strongly. One of such attempts is modifying the thickness of high-tensile-stress contact etch stop layer (HS CESL), length of diffusion (LOD) and gate width [6] [7] to control the tensile and compressive stresses in channel region to improve the channel mobility. In RFIC design, designer needs good modern to simulate accurate electrical characteristic in order to achieve the standard of the production. RFIC circuit need active and passive components both in digital and analogy IC design. Passive components play important roles in impedance matching, tuning, and filtering [8]. It is important to build an accurate device model in RFIC design. In this work, we show spiral inductors and Metal-Insulator-Metal capacitors models. Spiral inductor and Metal-Insulator-Metal capacitors have been used in low-noise amplifier, power amplifier and voltage-controlled oscillators for radio frequency (RF) system. To successfully design a microwave circuit application, like 4G, WiMax, UWB and DVB equipment, accurate equivalent model for embedded passive components are necessary. Next, we refer to the packaging. IC packaging is a critical link in the design flow. Microsystems Packaging played two roles: 1) It provided I/O connections to devices, and 2) It interconnected both active and passive components on system level boards [9]. Moreover, Flip-chip technology is an attractive interconnect scheme for high frequency RF applications. Flip-chip interconnect technology provides higher packaging density (a greater number of I/Os), improved. 3.

(14) performance (shorter leads). In the past, semiconductors had little or no affect on the electronic package design or process. However, the effect of packaging can not be ignored in the high frequency, now. Electronic packaging is becoming one of the greatest challenges in manufacturability, performance, and reliability in advanced electronics applications [10]. Hence, precise modeling and characterization of these interconnections is important to optimize the performance of the flip-chip signal, to enhance the performance of microwave circuits [11].. 1.2 Organization There are five chapters in this thesis. Chapter 1 describes the background of scaling challenges of CMOS transistors and passive devices for RFIC applications. Chapter 2 gives physical geometry of 90 nm SOI nMOSFETs. It refers to the thickness effect, width effect, and body potential. Chapter 3 gives silicon-base inductor and MIM capacitor modeling. We discuss the structure, simulation and measurement for these components. Chapter 4 gives integrate passive components of packaging modeling for Flip-Chip Ball Grid Array package (FC-BGA) IC. Two types of passive component, spiral inductor and MIM capacitor after packaging are simulated and measured. Finally, the conclusions are shown in chapter 5.. 4.

(15) Chapter II SOI nMOSFETs. Because for low power-dissipation, complementary Metal-Oxide-Semiconductor (CMOS) device is better than other active device, bipolar junction transistor (BJT), etc in advanced Integrated-Circuit (IC) manufacturing. The CMOS device dimension is scaling down to gain higher circuit performance. However, as dimensions of semiconductor devices are continuously scaling down, some bottlenecks are appeared. Short channel effect results in high off-stage current. It is a problem to turn off the device because it would make the circuit error. As the channel length is scaled to 0.25 μm and below, background and channel doping must be raise to values of 3 × 1017 cm-3 and higher in order to control the SCE [12]. However, it will degrade channel mobility for channel concentration above 2 × 1018 cm-3, because of ionized impurity scattering. Channel implant or halo implant is used to reduce the short-channel [13][14] but it increase junction capacitance. As a result, RC time constant is increase and circuit speed degrades. Recently, silicon-on-insulator (SOI) MOSFETs have been investigated due to improve isolation and reduced parasitic capacitance and compared with bulk MOSFETs. For scaling devices into the deep-sub-micrometer region, SOI offers excellent options for the reduction of short channel effects. Moreover, almost technology used in bulk devices, such as high-k and channel-strained, can be extensively applied in SOI devices. There , I wrote a study for SOI MOSFETs.. 5.

(16) 2.1 SOI MOSFETs structure Full name of SOI is Silicon On Insulator [15], it grows a thin silicon film on SiO2, which the thickness of silicon layer in SOI wafer is different. It can be divided into two devices, Partially Depleted SOI and Fully Depleted SOI. As the silicon film is thicker than the maximum gate depletion width, it is belong to partially depleted SOI (PD-SOI). As the silicon film is thin enough that the entire film is depleted, it is belong to fully depleted SOI (FD-SOI). The silicon layer in PD-SOI is over 400 nm. With a thick silicon layer, there is a neutral region below the depletion layer in the substrate. If the neutral region is ground, the electrical characteristics of PD SOI device will be as the electrically acts of traditional bulk device. If the neutral region is left electrically floating, the kink effect and Parasitic Bipolar Transistor (PBT) effect will be happened. It is due to that the charges which are generated by impact ionization accumulated in the neutral region, resulting in lowering the potential between source and drain. It will make operating current and threshold voltage instable. Hence, it can avoid kink effect and PBT effect by neutral region grounding with the body contact (BC) design. However, the area of the device will be increased. The silicon layer in FD-SOI is about 200 nm. The advantages of FD-SOI are no kink effect, because entire silicon layer is inside the depletion layer. And the subthreshold slope of FD-SOI can be near the 60 mV/decade, which means FD-SOI could operate at low threshold voltage (VT) and low power condition. However, there are two major drawbacks for FD-SOI. First, VT is sensitive to the silicon thickness of FD-SOI, which is difficult to be precisely controlled. Second, short channel effect of FD-SOI is worse than that of PD-SOI because buried oxide acts as a wide depletion region. As a result, PD SOI. 6.

(17) is the device structure most suitable for the fabrication of commercial application.. 2.1.1 The basic characteristic of SOI nMOSFETs The difference between SOI device and traditional bulk device is that there is kink effect in SOI device. It is also called floating body effect. Without an additional contact, the device with floating body is smaller than the device with body contact, With body contact, BC-SOI has higher stability in suppressing kink effect, PBT effect and GIDL effect. For floating body SOI device, kink effect and PBT effect are major issues on circuit performance. Kink effect may occur when the device is biased in the saturation region and drain voltage exceeds a certain value, resulting in drain current suddenly rising. Kink effect affects the stability of the circuits using SOI devices, and will worsen the differential drain conductance of the devices. The bipolar effect is due to the transient enlarged body potential and the parasitic open base bipolar junction transistor (BJT) turn on, enhancing drain current during many picoseconds and impacting circuit operation. If body potential of the device is well controlled to near source voltage, the kink effect and the parasitic BJT effect will be reduced, and circuit will become more stable.. 2.1.2 The basic hot carrier effect The term ‘hot carrier’ refers to either holes or electrons that have gained very high kinetic energy after being accelerated by a strong electric field in areas of high field intensities within a semiconductor (especially MOS) device. Because of their high kinetic energy, hot carriers can get injected and trapped in areas of the device where they. 7.

(18) shouldn’t be, forming a space charge that causes the device to degrade or become unstable. The term ‘hot carrier effect’, therefore, refers to device degradation or instability caused by hot carrier injection. Today’s ULSI MOSFET devices feature extremely short channel lengths and high electric fields. In these high electric fields, carriers are accelerated to high velocities, reaching a maximum kinetic energy (hot) near the device drain. If the carrier energy is high enough, impact ionization can occur (Drain Avalanche Hot Carrier Effect), creating electron-hole pairs (Fig.2-1). These holes and electrons can attain enough energy to surmount the Si-SiO2 barrier and become trapped in the gate oxide. Trapped charges cause device degradation and enhanced substrate current (ISUB), resulting in shifts in measured device parameters, such as threshold voltage (VTH), transconductance (GM), and linear (IDLIN) and saturation (IDSAT) drain current.. 2.2 Experiment By referring previous study [16], we will introduce the measurement methodology and instruments applied in our experiments. The instrument we used is Agilent 4156B semiconductor parameter analyzer, which is shown in Fig.2-2. We apply an Interactive Characterization Software (ICS) to be a measurement system, which is shown in Fig.2-3, to control 4156B semiconductor parameter analyzer. The wafer was measured in probe station of 8 inch, which is shown in Fig.2-4.. 2.2.1 ID-VD measurement ID-VD characteristic is one of the most important parameter of transistors. In this. 8.

(19) work, the drain voltage (VD) is swept over for all operation voltage range from 0-1.5volt with gate voltage from 0-1.5volt, which is set at step mode. Fig.2-5 shows a single curve of ID-VD with various VG bias. Linear current (IDLIN) and saturation current (IDSAT).are indicative of the performance of the device in both linear and saturation region, respectively.. 2.2.2 ID-VG measurement For ID-VG measurement, VG is swept over operation voltage range with fixed VD bias. Fig.2-6 shows a typical ID-VG curve when VD bias is at 0.05V in order to observe the characteristics in linear region. From ID-VG measurement, IDLIN, transconductance (GM) and threshold voltage (VT), even subthreshold swing (SS) can be obtained. In this experiment, GM is defined as the slope of tangent in ID-VG curve at VD=0.5V; and we adopt maximum GM (GMMAX) extracted from the maximum slope of ID-VG curve to show the device performance. When gate voltage is below threshold voltage, device is in weak inversion region and the reciprocal of the slope of log(ID) verse VG curve is defined as subthreshold swing (SS). The corresponding drain current is called subthreshold current.. 2.2.3 VT extraction Roughly speaking, VT is the minimum gate voltage required to turn on the channel and can be extracted from ID-VG curve in the linear region. Several methods have been developed to extract VT for a MOS transistor: (1) the constant-current method; (2) the linear-extrapolation method, etc. The constant-current method is widely used in industry because of its simplicity. VT can be determined quickly with only one voltage. 9.

(20) measurement, but it has an evident disadvantage of being strongly dependent of the arbitary choice of current; that is, different gate voltages are taken to be VT at different drain current. The method we applied is the linear-extrapolation method, which is most extensively used by researchers. It is common practice to find the point of maximum slope by GMMAX, fit a straight line to the curve at that point, and extrapolate to ID=0, as illustrated in Fig.2-6. In this way, VT we get through this method is more accurate than the constant-current method.. 2.3 Results Three topics have been discussed in this section to study in strain technique and body potential: 1) the thickness effect of HS CESL film on SOI nMOSFETs, 2) the effect of devices geometry on SOI nMOSFETs and 3) the impact of Body-Potential on SOI nMOSFETs. The device in topic 1 and 2 is in the same wafer, which were fabricated with a 40 nm Si active layer and 200 nm buried oxide (BOX) on Implanted Oxygen (SIMOX) <100> channel orientation SOI substrate. After STI, 1.6nm nitride gate oxide was grown by rapid thermal oxidation in NO ambient. Next, composite oxide/SiN spacers via low-temperature processing and junctions were formed using arsenic (As) and boron (B) ion implantations. Furthermore, in order to investigate the interactive effect of tensile and compressive stress, devices were fabricated with various thickness of HS CESL (700 A, 1100 A and conventional SiN layer-SiN 380), LOD (0.45~4.5 μm) and gate width (0.18~10 μ m). Finally, devices were metalized using CoSi salicidation. The DC measurements were carried out on HP4156 under various drain voltages (VD=0~1.4 V) and gate voltages (VG=0~1.4 V); hot-carrier stressing was performed with VG=VD=1.2 V. 10.

(21) under room temperature (25℃) for 100 min. The device in topic 3 is in another wafer, which were fabricated with 90 nm thick SI active layers, 200 nm thick buried oxide (BOX), using the 90 nm process with STI isolation technology. SOI nMOSFETs with H-gate body-contact (BC-SOI) and without body-contact (FB-SOI) was compared for device performance inspection. Device HCE stressing and measurements were performed on probe station using various drain voltage (VD=0~1.5 V), and various gate voltages (VG=0~1.5 V) with 300 minutes stress time.. 2.3.1 The Thickness Effect of HS CESL film on SOI nMOSFETs The device structure is show in Fig.2-7; it indicates the orientations of stress caused by HS CESL and STI. In x axis, the HS CESL will induce a tensile stress in channel region, and STI will cause a compressive one. The intensity of tensile stress in channel region is related to the thickness of HS CESL film [17]. From previous studied [18], it had been reported that a tensile stress can be induced by the HS CESL, thus enhancing the channel electron mobility due to lighter effective mass of carriers in the strained-Si layer and reduced inter-valley scattering. Thus, thicker HS CESL will induce higher tensile stress, result in more mobility enhancement. However, we believed that a thicker HS CESL will also induce more damages to oxide and oxide/Si interface in channel region, degrading performance of the device. Therefore, device performance can not be improved by simply increasing the thickness of HS CESL. The ID-VD curves of 90 nm SOI nMOSFETs with various HS CESL thicknesses and conventional SiN layer (CN layer) were shown in Fig.2-8. It is apparent that devices with HS CESL possess larger ID than those with traditional CN layer. As the thickness of HS CESL is increased from 700. 11.

(22) A to 1100A, we found that the ID decreases because of the degradation of channel carrier mobility cause by inappropriate high tensile stress induced defects. The transconductance (Gm) versus VG – VTH is shown in the Fig.2-9. We found that the HS CESL will enhance the Gm and mobility. Similar to device’s ID-VD characteristic, the device with 700 A HS CESL possess has higher Gm than the device with 1100 A. Apparent degradation happens on device with 1100 A HS CESL is subject to the higher defect density caused by excess tensile stress. We believed that the HS CESL will induce more interface states; therefore, the VTH is on the rise as the thickness of HS CESL increased. The ID – VG curves were shown in Fig.2-10. In subthreshold region, devices with HS CESL possess larger leakage currents than those with CN layer apparently. This means the tensile stress induced by HS CESL will cause more defects in oxide and oxide/Si interface; which provide more leakage current paths and induce a larger gate induced drain leakage current (GIDL). In order to inspect the thickness of HS CESL on device’s hot-carrier-induced reliability, devices were stressed with 100 min hot-carrier stressing under VD=VG=1.2 V. Fig.2-11 and Fig.2-12 show the ID degradation characteristics of 90 nm BC-SOI nMOSFETs with 1100 and 700 A HS CESL. It is obvious that ID has an apparent rise during short time hot-carrier stressing especially for devices with 1100 A HS CESL and then ID degraded after long time hot-carrier stressing especially for devices with 1100 A HS CESL and then ID degraded after long time hot-carrier stressing. From previous studies [19], they reported that holes will be injected into the oxide from the substrate. By the gate tunneling [20], during hot-carrier stressing and these trapped holes are located close to the oxide/Si interface, resulting in device threshold voltage reduction. As the gate oxide continue downscaling, apparent trapped holes were form near the interface and will. 12.

(23) be increased during strain stress. Trapped holes in oxide/Si interface will decrease the VTH, result in increased ID. Compared to device with 700 A HS CESL and with 1100 A HSCESL, high tensile stress results in larger numbers of defects near to oxide/Si interface to trap holes, causing VTH degradation and enhancing the ID. Owing to higher impact ionization rate, it is apparently that the devices with 1100 A HS CESL were degraded more seriously after long time hot carrier stressing. The generated defects near to oxide/Si interface will provide more vacancies for charges trapping, resulting in larger gate leakage. GM degradations of devices with 1100 and 700 A HS CESL were shown in the Fig.2-13 and Fig.2-14. Obvious shift and decrease were found on the GM especially for devices with thicker HS CESL. Both shift and decrease in GM were attributed to the larger amount of trapped holes induced a lots of VTH lowering.. 2.3.2 The Effect of Devices Geometry on SOI nMOSFETs The STI induced compressive stresses were divided into x (parallel the channel direction) and y axes (perpendicular the channel direction). In x axis, the intensity of compressive stress for channel center region is related to the length LOD; in y axis, it is related to the gate width. Fig.2-15~Fig.2-17 show the △ID, VTH and △GM versus gate width of 90 nm SOI nMOSFETs with various HS CESL. In Fig.2-15, the ID (719 μA/μm)of device with W=10μm and SiN380 CN layer was used as reference to estimate the deviation of ID. It is apparent that the ID increases as the gate width decreases because the compressive stress (y axis) is increases with the gate width decreases [21]. Narrow gate width device possesses larger drain current density and off-state drain current density, degrading device’s subthreshold slope and lowering the threshold voltage as shown in 13.

(24) Fig.2-16. In Fig.2-17 (standard GMMAX =476 S/μm devices with W=10 μm and SiN380 CN layer), it is obvious that GMMAX (mobility) increase as the gate width reduces. Fig.2-18 and Fig.2-19 show the △ID and △GM versus LOD of 90 nm SOI nMOSFETs with various gate widths and HS CESL. In Fig.2-18, (reference ID = 735 μA/μm devices with W = 10 μm, LOD = 0.45 μm and SiN 380 CN layer), it is apparent that the ID of devices with wider gate widths (W = 10 μm) increases with the LOD increases because longer distance from gate to STI will weaken the impact of compressive stress (x axis) on channel region, increasing the impact of tensile stress (x axis) indirectly. However, the ID increases and become unapparent LOD dependence for devices with narrower width (W = 0.9 μm). In Fig.2-20, it is obvious that the total amount of compressive stress in x axis is related to the gate width. Decreasing the gate width will also reduce the amount of induced compressive stress and result an unapparent LOD dependence for ID increasing. Similar tendency can be found on device’s △GM versus LOD curves (Fig.2-19 reference GMMAX = 483 S/μm devices with W = 10 μm, LOD = 0.45 μm and SiN380 CN layer). For wider gate width devices, GMMAX is increased with LOD increased but the dependence is unapparent for narrower gate width devices. IG versus LOD of 90 nm SOI nMOSFETs with various gate widths and HS CESL was shown in Fig.2-21. It can be found that the LOD effect on gate leakage is very unapparent for all devices. The dominators for gate leakage are gate width and thickness of HS CESL. Devices with wider gate width and thicker HS CESL possess higher gate leakages. Fig.2-22 shows VTH decreases with LOD increase, and devices with 1100 A HS CESL possess a higher VTH than device with 700 A CESL, because higher stress CESL will induce more interface states for electron trapping and raise the VTH.. 14.

(25) 2.3.3 The Impact of Body-Potential on SOI nMOSFETs The leakage path impact on body-potential (VB) for FB-SOI nMOSFETs was shown in Fig.2-23, it is apparent that the VB can be affected by gate (IG), junction (IJ), impact-ionization (III) and STI edge (IEL) currents. Fig.2-24 shows the width effect on ID-VD characteristic of 90 nm BC-SOI nMOSFETs. The drain current density (ID/W) increases apparent as the channel width decreases due to the increase of channel edge current [22]. Fig.2-25 shows large channel edge current in narrow channel-width devices will lower the threshold voltage. Hence, for SOI nMOSFETs with width 1.2 μm, apparent ID degradation was happened especially with stressed VG=VD=1.5V. It is due to the large vertical electrical field will increase inversion channel charge and enhance hot carrier effect. Therefore, more serious valence-band electron tunneling was happened, increasing the interface state generation rate, resulting in serious IDSAT degradation (Fig.2-26) and gate leakage variation (Fig.2-27). We believed that the hot-carrier-induced defects at Si-SiO2 interface will cause device’s threshold voltage shift, and provide a gate leakage path for carrier tunneling. In this work, a method which setting BC-SOI device with IB=0 was used to monitor the VB of FB-SOI device, as shown in inset of Fig.2-28. Fig.2-28 shows that a kink effect will happen on BC-SOI nMOSFETs with IB=0; thus, we believed it is a reasonable way to monitor the characteristic of FB-SOI. Fig.2-29 shows the mobility will increase with channel width decrease for both SOI nMOSFETs. Fig.2-30 shows lower VB was found at narrower channel-width device especially at large VD, and is more sensitive with gate voltage because of gate-induced drain leakage and gate tunneling (Fig.2-31). In order to investigate channel edge leakage, we inspect the ID-VG plot with VB=VD without the. 15.

(26) impact of IJ and IG. Owing to IEL, it is apparent that large ID happens especially on narrower channel-width device, as shown in Fig.2-32. Compared with BC-SOI nMOSFETs, FB-SOI device possesses a larger ID due to serious kink effect. Besides, we found that the body potential was also affected by channel width. In this work, lower VB was found at narrower channel-width device; it is due presumably to fewer hole accumulated at neutral region of substrate. For FB-SOI nMOSFETs, narrower channel-width device possesses lower body potential; thus, higher electric field between body and drain happen, causing larger hot-carrier-induced device degradation. Fig.2-33 shows the lifetime of 90nm BC-SOI and FB-SOI nMOSFETs. Compared with BC-SOI nMOSFETs, FB-SOI device possesses similar trend but with larger lifetim because body potential happen. For 90 nm SOI nMOSFETs with ultra thin gate oxide (TOX = 1.6 nm), the hot carrier was more easy to induce defects at Si-SiO2 interface for narrow width device; which will make worse the IDSAT degradation especially at high stress gate voltage. Thus for narrow channel-width devices, the hot-carrier-induced degradation will increase with width decrease and with stress gate voltage increase. Moreover, for FB-SOI device, we believe that the body potential will suppress the field between drain to body, thus alleviate the hot-carrier-induced device degradation.. 2.4 Summary In the topic one and two, we talked about strain technique. The interactive stress effects between HS CESL thickness, LOD and gate width on device performance and hot-carrier induced degradations were investigated. For the inspection of CESL film thickness, devices with 700A HS CESL possess efficient mobility enhancement and 16.

(27) hot-carrier reliability immunity than devices with 1100A HS CESL. With improper tensile stress, the thicker HS CESL (1100A) will induce larger stress defects and damage the device’s channel lattice structure, thus degrading device characteristics. For the impact of device geometry layout (LOD and gate width), we found that increasing the LOD will decrease the STI-induced compressive stress and enhance the device’s mobility especially for wide gate width devices. For narrow width devices, the impact of LOD will be unapparent. At the last topic, we discussed body potential. For 90 nm BC-SOI nMOSFETs, the narrower channel width will induce edge current, thus enhancing hot-carrier-induced device’s degradation. But for FB-SOI nMOSFETs, the body potential caused by narrow width is the major factor for hot-carrier device degradation. In this work, we design a method using BC-SOI device with IB=0 to monitor VB for different narrow width device. For FB-SOI nMOSFETs, narrower width device possesses lower body potential, causing higher electric field between body and drain, thus enhancing device’s driving capability and hot-carrier-induced device degradation.. 17.

(28) Chapter III Modeling and Package Theory. Accurate passive model can not only speed up the production time but also increase yield for IC. In this work, we show passive component including spiral inductors and Metal-Insulator-Metal capacitors models with four size at Fig.3-1.. 3.1 Model Theory For inductor or capacitor, these passive components can be equalized to 2-port network, as shown in the Fig.3-2. We can get Q factor, inductance and capacitance extracted from 2-port network parameters (Z parameters, Y parameters) with the second port grounded. First, we consider the extraction of the spiral inductor. There are two way to extract inductance. 1) Y21 =. I2 1 =− V1 V =0 Req + jω Leq 2. −. 1 = Req + jω Leq Y12 imag (−. ⇒ Leq =. ⇒Q=. ω. ω Leq Req. 1 ) Y21. 1 ) imag (−Y21 ) Y21 = =− 1 real (−Y21 ) real (− ) Y21 imag (−. 2). Z in = Req + jω Leq. 18.

(29) Leq =. imag ( Z in ). ω. For any two port device, Z matrix can be listed.. V1 = Z11 × I1 + Z12 × I 2 V2 = Z 21 × I1 + Z 22 × I 2 However, the second must be grounded.. V2 = 0 ⇒ I 2 = −. Z 21 × I1 Z 22. ⎛ Z × Z 21 ⎞ V1 = Z11 × I1 + Z12 × I 2 = I1 ⎜ Z11 − 12 ⎟ Z 22 ⎠ ⎝. ⇒ Z in =. V1 Z × Z 21 1 = Z11 − 12 = I1 Z 22 Y11 imag (. ⇒ Leq =. ω. 1 ) Y11. 1 ) ω Leq imag ( Z in ) imag (Y11 ) Y11 ⇒Q= = = =− 1 Req real ( Z in ) real (Y11 ) real ( ) Y11 imag (. We can get Q factor and inductance from either method. Moreover, the Q factor of capacitor and capacitance also can be extracted by the same method.. ωCeq = imag (. ⇒ Ceq =. 1 1 ) = imag ( ) 1 1 − Y11 Y21. imag (Y11 ). ω. =. imag (−Y21 ). ω. 1 1 ) −imag (− ) −imag ( Z in ) Y11 Y21 Q= = = 1 1 real ( Z in ) real ( ) real (− ) Y11 Y21 −imag (. ⇒Q=. −imag ( Z in ) imag (Y11 ) imag (Y21 ) = = real ( Z in ) real (Y11 ) real (Y21 ). 19.

(30) Finally, we make a table about Q factor of inductor and capacitor, inductance and capacitance, as shown in Fig.3-3 [23] [24].. 3.2 Ball Grid Array (BGA) Package Recently, high integration, small size, low power-supply voltage, and high operating frequency, integrated circuits (ICs) have made innovations in packaging methods for high-speed digital and RF IC applications. Fine pitch, high pin-count and good heat dissipation are key issues of packaging design for passive component. In addition to the conventional reliability problem, the influence of package parasitic on IC signal is also an important issue of packaging industry. The main purpose of IC packaging is providing current path, to distribute output /input signals on chip and dissipate heat. With the level of integration rising, some integrated circuits will excess 100 pins.. For high pin count, high performance and good. heat dissipation, BGA packages have become and important choice for high-speed VLSI.. 3.2.1What is a BGA package? A Ball Grid Array or BGA package is a mount technology. The BGA package was developed for integrated circuits with large numbers of pins. The BGA packaging is an approach to the connection which is more useful than conventional surface mount connections. The Ball Grid Array, BGA, uses the underside of the package, where there is a substantial area for the connection. However, BGA can offer a lower thermal resistance between the silicon chips itself than quad flat pack (QFP) devices. Fig.3-4 shows the different interconnection types of BGA package, which connects between chip and. 20.

(31) substrate by wire-boding, tape-automated bonding (TAB), or flip-chip bumping.. 3.2.2 Flip chip BGA With a fine-pitch BGA, size of packaged passive component can be reduced quite effectively. In addition, Mini-BGA eliminates the die paddle design to allow for more room in routing traces, so the package size can be reduced almost the same as the chip size. Micro BGA uses flip-chip bumping instead of wire-bonding to make package unit small and thin. Pitch can be reduced to 50μm. Flip-chip bumping also can be used to replace wire-bonding and thus the signal path can be even shorter to reduce the parasitic effects [25].. 21.

(32) Chapter IV Integrate Passive Components of Packaging. Modeling. Spiral inductors and Metal-Insulator-Metal capacitors have been used in low-noise amplifier, power amplifier and voltage-controlled oscillators for radio frequency (RF) system. To successfully design a microwave circuit application, like 4G, WiMAX, UWB and DVB equipment, accurate equivalent model for embedded passive components were necessary. In addition, the effect of packaging can not be ignored. Since the package behaves as a passive element of low pass filter and affects the electrical characteristic of chip circuit. Thus, an accurate and board-band models for spiral inductor and MIM capacitor are required to match the characteristic of components in the chip and package. We consider the spiral inductor and the MIM capacitor as a two-port network. A method has been introduced to extract the electrical parameters for spiral inductor in π model [26] and a simple model has been developed to predict the performances of MIM capacitor [27] [28]. Accurate models we considered were extracted by vector network analyzer S-parameters measurement result. Besides, we derived a closed-form expression for Q factor for a spiral inductor in terms of two-port S parameters [29]. The equivalent lumped element model is very important in understanding the electrical behavior of the RF system design. The characteristic of the package is like that of passive element. Some researches have been done to simulate the configuration for flip-chip equivalent circuit model [30]. The purpose of this paper is to develop a simple package model which can be used in both spiral inductor and MIM capacitor. In this work, the measurements of S11 and S21 by 22.

(33) VNA and optimized models of the chip and FC-BGA packaging are shown. We had investigated the issue between the measurement and the simulation in the high frequency domain. It is apparent that we can make an accurately model a flip-chip packaging up to 12 GHz.. 4.1 Experiment In this work, inductor and capacitor were made by 0.25um process technology, with and without flip-chip packaging. As shown in Fig.3-5 and Fig.3-6, these devices were measured in Cascade microwave RF probes station using a network analyzer, and 2-ports S-parameters measurements were performed from 10 MHz to 12GHz. An integrated wafer-level spiral inductor and MIM capacitor before packaging are shown in Fig.3-7 and Fig.3-8. A 500-μm pitch RF probe is used to perform on wafer-level component measurement. Fig.3-9 and Fig.3-10 show the top and bottom view of this FC-BGA packaging for these passive components. The chip with solder balls was flipped and aligned to the substrate using the flip-chip bonding system. Bumped pitch is 500 and 100. μm in height respectively. All devices before and after packaging have been simulated using Agilent supporting advanced design system. In order to eliminate errors caused by the measurement system for obtaining accurate device characteristic, a standard Short-Open-Load-Thru (SOLT) calibration and de-embedding using a dummy open pads technique was used.. 23.

(34) 4.2 Wafer Level and Packaging Level Modeling 4.2.1Wafer Level Fig.3-11 shows the π lumped element model of spiral inductor before packaging. For wafer-level spiral inductor, the inductance was represented by Ls, and series resistances were represented by Rs1 and Rs2 with a RF resistance Rp.. There is a Cp parameter between the spiral in the high frequency because capacitance coupling. The oxide capacitances between the spiral and the silicon substrate were modeled by Cs1 and Cs2. The lumped element model of MIM capacitor before packaging was shown in the Fig.3-12; Cs is the main element of the capacitor and Ls is the parasitic inductance existing in the electrodes. The Rs models the parasitic losses in the dielectric. Cs1 and Cs2 represent the capacitance to ground. By referring to reference [26], if we ignored the losses from resistance in the model, the parameters of spiral-inductor before packaging could be found by the following equation.. 1 ⎡ ⎢ jωCs1 + jωCp + jω Ls Y =⎢ 1 ⎢ ⎢ − jωCp − jω Ls ⎣. ⎤ ⎥ ⎥ 1 ⎥ jωCs2 + jωCp + jω Ls ⎥⎦ − jωCp −. 1 jω Ls. (1). From equation (1), Ls is extracted as –image(1/Y21) in the low frequency and we can find the Cs1, Cs2, and Cp directly from real S-parameter measurement before packaging. Then, in consideration with the losses of spiral inductor, these losses parameters can be obtained by using modeling optimization. Then, a reasonable π model spiral inductor extracting by theoretically can be found.. 24.

(35) Next, the basic parameter of this capacitor model is Cs, we extract Cs by the –image(Y21) in the low frequency. Other parameters can also be extracted. Same method is used to determine each of the parameters in the MIM capacitor model.. 4.2.2Packaging Level Another purpose of this work is to develop complete spiral inductor model and MIM capacitor with packaging effect included. In addition, accurate parameters must to be extracted for the flip-chip packaging and match related electrical characteristic. For flip-chip packaging, package-structure can be considered as a transmission line, an additional RCL must be included to the packaging-level inductor and capacitor models. Fig.3-13 shows the model of spiral inductor after packaging. It is modified from the original wafer-level model. In order to fit packaging situation accurately, we use two stage RLC model. We can extract the spiral inductor parameters (Ls, Rp, Cp, Rs1, Rs2 Cs1, Cs2) from the wafer-level model. The package-level parameters (R1, L1, C1….) can be extracted from the measurement of inductor. Thus, we can develop package model of spiral inductor. Then same package-level parameters can be also used in the MIM capacitor modeling, as shown in Fig.3-14.. 25.

(36) 4.3 Spiral Silicon-Base Inductor and MIM Capacitor 4.3.1Spiral Silicon-Base Inductor For inductor A (7.08 nH), the models before and after package are in the Fig.3-15 and Fig.3-16. Fig.3-17 and Fig.3-18 show the measured and simulated result of S11 and S21 before (wafer-level) and after flip-chip BGA packaging for the spiral inductor. Related phase (Fig.3-19, Fig.3-20), and smith-chart (Fig.3-21, Fig.3-22) were also shown to compare the RF characteristic for inductor before (wafer-level) and after packaging. The Q factor and series inductance L can be extracted from the measured and simulated S-parameters using Y-parameters formulas:. Q=. −imag (Y11 ) real (Y11 ). LS =. (2). −imag (1/ Y21 ) 2π f. (3). The measured results of L and Q are compared with simulated results, as shown in Fig.3-23 and Fig.3-24. It is obvious that the measured data and the simulated data match very well in the frequency up to 12GHz. Slight discrepancy between the measured and simulated of smith–chart at higher frequencies is due to series resistance and RF resistance losses. There is a slight difference in the phase between die and packaging, which due to the parasitic capacitance effect in the additional RLC model for flip-chip BGA packaging. For inductor B (5.221 nH), the models before and after package are in the Fig.3-25 and Fig.3-26. Fig.3-27 and Fig.3-28 show the measured and simulated result of S11 and S21 before (wafer-level) and after flip-chip BGA packaging for the spiral inductor. 26.

(37) Related phase (Fig.3-29, Fig.3-30), and smith-chart (Fig.3-31, Fig.3-32) were also shown to compare the RF characteristic for inductor before (wafer-level) and after packaging. The measured results of L and Q are compared with simulated results, as shown in Fig.3-33 and Fig.3-34. It is also obvious that the measured data and the simulated data match very well in the frequency up to 12GHz. The electrical length after packaging is longer than the electrical length before packaging. It is due to package structure lengthens the transmission way. The electrical length of S11 before packaging almost is on the upper semicircle. It represents inductance characteristic. The inductor after packaging expresses capacitance characteristic in the high frequency.. 4.3.2MIM Capacitor The characteristic of MIM capacitor after packaging has been predicted in this section. We use the same package parameters (R1, L1, C1….) in the packaging model for MIM capacitor. For capacitor A (0.485 pF), the models before and after package are in the Fig.3-35 and Fig.3-36. Fig.3-37 and Fig.3-38 show the measured and simulated values of S11 and S21 before (wafer-level) and after flip-chip BGA packaging for MIM capacitor. Related phase (Fig.3-39, Fig.3-40), and smith-chart (Fig.3-41, Fig.3-42) are also shown to compare the RF characteristic for capacitor before (wafer-level) and after packaging. The Q factor and series capacitance C can be extracted from the measured and simulated S-parameters using Y-parameters formulas:. Q=. (4). imag (Y21 ) real (Y21 ). CS =. −imag (Y21 ) 2π f. (5). 27.

(38) The measured result of C and Q in comparison with simulated data was shown in Fig.3-43 and Fig.3-44. For capacitor B (10.466 pF), the models before and after package are in the Fig.3-45 and Fig.3-46. Fig.3-47 and Fig.3-48 show the measured and simulated values of S11 and S21 before (wafer-level) and after flip-chip BGA packaging for MIM capacitor. Related phase (Fig.3-49, Fig.3-50), and smith-chart (Fig.3-51, Fig.3-52) are also shown to compare the RF characteristic for capacitor before (wafer-level) and after packaging. The Q factor and series capacitance C can be extracted from the measured and simulated S-parameters using Y-parameters formulas: The measured result of C and Q in comparison with simulated data was shown in Fig.3-53 and Fig.3-54. Finally, we made a table of all parameters for inductor and capacitor in Fig.3-55. In this work, this extraction methodology for silicon-base spiral inductor and MIM capacitor with packaging effect is reasonable and workable.. 28.

(39) Chapter V. Conclusions. We had investigated the strain technique impact on device performance and reliability. In this work, devices with 700A HS CESL possess efficient mobility enhancement and hot-carrier reliability immunity than devices with 1100A HS CESL. And we found that increasing the LOD will decrease the STI-induced compressive stress and enhance the device’s mobility especially for wide gate width devices. For narrow width devices, the impact of LOD will be unapparent due to the STI-induced edge leakage. In comparison with BC-SOI device, it was found that lower hot-carrier induced device degradation was happened on FB-SOI. We propose a method using BC-SOI device with IB=0 to monitor VB for SOI device. With body potential inspection for 90 nm SOI nMOSFETs, the narrower channel width in BC-SOI nMOSFETs will induce edge current, thus enhancing hot-carrier-induced device’s degradation. For FB-SOI nMOSFET, body potential suppresses electric field between body and drain, thus alleviates the hot-carrier-induced device degradation. Moreover, narrower width device of FB-SOI possesses lower body potential, causing higher electric field between body and drain, thus enhancing device’s capability and hot-carrier-induced device degradation apparently. For RFIC system, the related active components (diode and MOSFETs) and passive components (resistors, capacitors, inductor and transmission lines) will affect the performance of the RFIC. In this work, efficient extracting method for wafer-level and packing-level inductor as well as MIM capacitor are presented. The lumped element equivalent model of the inductor with or without Flip-Chip BGA packaging has been introduced. The return-loss (S11), insertion loss (S21) and quality factor (Q) were fully. 29.

(40) characterized. Reasonable modeling and measurement have been fitted well up to 12 GHz. The extracting method shown in this work can be repeated to perform different structure of integrated passive component and to evaluate RF performance of package-level passive components using in System-in-Package and module area.. 30.

(41) Fig.2-1. Diagram of Hot Carrier Effect. 31.

(42) Fig.2-2. Semiconductor Parameter Analyzer HP4156B. 32.

(43) Fig.2-3. Agilent ICS Software. 33.

(44) Fig.2-4. DC Probe Station. 34.

(45) ID (μA/μm)). 16 14 12 10 8 6 4 2 0. Vg=0.3 V Vg=0.75 V Vg=1.2 V. IDLIN. 0.0 Fig.2-5. IDSAT. 0.2. 0.4 0.6 0.8 VD (volts). 1.0. 1.2. ID-VD characteristics with different gate voltage. Fig.2-6 ID-VG and GM-VG characteristics. 35.

(46) HS CESL induced stress STI induced stress. HS CESL layer. STI. STI Z. BOX Fig.2-7. X. The schematic structure of SOI nMOSFETs(the HS. CESL induced tensile stress and STI induced compressive stress). 1200. ID (μA/ μm). BC-SOI nMOSFET 1000 L / W = 0.09 / 10μm VG = 1.4 V 800 600. HS:1100A HS:700A SiN 380. 400 200 0 0.0. 0.5. 1.0. 1.5. VD (volts). Fig.2-8. ID-VD characteristics with different HS CESL 36.

(47) Gm (S/ μm). 600. BC-SOI nMOSFET L / W = 0.09 / 10μm VD=0.05 V. 400. high stress 1100A high stress 700A SiN 380. 200 0 0.0. Fig.2-9. 0.5 VG- VTH (volts). 1.0. GM-(VG-VTH) characteristics with different HS CESL 3. 10. BC-SOI nMOSFETs 1 10 L / W = 0.09 / 10μm VD=0.05 (volts) ID (μA/μm). -1. 10. HS: 1100A HS: 700A SiN 380. -3. 10. -5. 10. -7. 10. Fig.2-10. -0.5. 0.0. 0.5 VG (volts). 1.0. ID-VG characteristics with different HS CESL. 37.

(48) 700. HS CESL 1100A BC-SOI nMOSFET L / W= 0.09 / 10 μm. ID (μA/μm). 600. Stress VG=VD=1.2V. 500 400. fresh 20 min 40 min 60 min 80 min 100 min. 300 200 100 0 0.0. Fig.2-11 700 600 ID (μA/μm). 500. 0.4. VD (volts). 0.8. 1.2. ID-VD with different Stress time of 1100A. HS CESL 700A BC-SOI nMOSFET L / W= 0.09 / 10 μm Stress VG=VD=1.2V. 400 fresh 20 min 40 min 60 min 80 min 100 min. 300 200 100 0 0.0. 0.4. 0.8. 1.2. VD (volts). Fig.2-12. ID-VD with different Stress time of 700A. 38.

(49) Gm (S/μm). 600. HS CESL 1100A BC-SOI nMOSFET 400 L / W = 0.09 /10 μm. fresh 20 min 40 min 60 min 80 min 100 min. 200 Stress VG= VD= 1.2V. 0 -0.5. 0.0 0.5 VG-VTH (volts). 1.0. Fig.2-13 GM characteristics with different Stress time of 1100A HS CESL 700A BC-SOI nMOSFET L/W = 0.09/10 μm. Gm (μS/μm). 600. fresh str 20 min str 40 min str 60 min str 80 min str 100 min. 400 200 Stress VG= VD= 1.2V. 0 0.0. 0.5 VG-VTH (volts). 1.0. Fig.2-14 GM characteristics with different Stress time of 700A 39.

(50) 35 30. ΔID (%). 25. 90 nm BC-SOI nMOSFETS Ref:SiN 380 W=10μm ID=719 μA/μm. HS:1100A HS:700A SiN 380. VD=1.2V VG=1.2V. 20 15 10 5 0. Fig.2-15. 0.09. 0.18. 3.6. 10. ID-Width characteristics with different HS CESL. 0.6. Vt (volts). 0.5. 90nm BC-SOI nMOSFETS. 0.4. HS:1100A HS:700A SiN 380. 0.3 0.2 0.1 0.0. Fig.2-16. 0.09. 0.18. 3.6. 10. VT-Width characteristics with different HS CESL. 40.

(51) 35. ΔGm MAX (%). 30 25. 90 nm BC-SOI nMOSFETS Ref:SiN 380 W=10μm Gm MAX=476 S/μm. HS:1100A HS:700A SiN 380. 20 15 10 5 0. Fig.2-17. 0.09. 0.18. 3.6. Width (μm). GM-Width characteristics with different HS CESL. 35 30. 90 nm BC-SOI nMOSFETS Ref:SiN 380 ID=734 μA/μm. W=0.9 μm. HS:1100A HS:700A SiN 380. 25. ΔID (%). 10. 20. 30 25 20. W=10 μm. 15. 35. 15. 10. 10. 5. 5. 0. Fig.2-18. 0.45. 1.35. 2.7. 0.45 LOD (μm). 2.25. 4.5. 0. ID-LOD characteristics with different HS CESL. 41.

(52) 35. ΔGm MAX (%). 30. 90 nm BC-SOI nMOSFETS Ref:SiN 380 Gm=483 S/μm. W=0.9 μm. HS:1100A HS:700A SiN 380. 25 20. 30 25 20. W=10 μm. 15. 35. 15. 10. 10. 5. 5. 0. Fig.2-19. 0.45. 1.35. 2.7. 0.45 LOD (μm). 2.25. 4.5. 0. GM-LOD characteristics with different HS CESL L. G. LOD. W. Y X. Fig.2-20. The schematic structure of SOI(vertical view). 42.

(53) 10. 90nm BC-SOI nMOSFETS VD=0.05V VG=1.2V. IG (μA/μm). W=0.9 μm. HS:700A HS:1100A SiN 380. 1. 1. W=10 μm. 0.1. 0.1. 0.01. 0.01 0.45. Fig.2-21. 1.35. 2.7. 0.45 LOD (μm). 2.25. 4.5. IG-LOD characteristics with different HS CESL. 0.8 0.7. 0.8 W=0.9 μm. 90nm BC-SOI nMOSFETS HS:1100A HS:700A SiN 380. 0.6. Vth (volts). 10. 0.5. 0.6. W=10 μm. 0.4. 0.7 0.5 0.4. 0.3. 0.3. 0.2. 0.2. 0.1. 0.1 0.45. Fig.2-22. 1.35. 2.7. 0.45 LOD (μm). 2.25. 4.5. VTH-LOD characteristics with different HS CESL. 43.

(54) Vs. VD. IG. n+ ISB. III VB IDB BOX. n. +. IEL STI. Substrate Fig.2-23. Leakage path impact on VB of nMOSFETs on PD-SOI Substrate. 500. Drain Current ID (μA/μm). W=1.2μm W=5 μm 400 W=10 μm L= 90nm 300 VG= 1V 200 100 0 0.0. 0.2. 0.4. 0.6. 0.8. 1.0. VD (Volts). Fig.2-24. ID-VD characteristics with different width 44.

(55) 0.550 L= 90nm. Vth (volts). 0.545 0.540 0.535 0.530 0. 2. 4. 6 8 Width (μm). 10. Fig.2-25 VTH characteristics with different width. 5. Stress Voltage: VG=VD=1.5V. ΔIDsat (%). 4. BC-SOI, LG=90nm W=1.2 μm W=5 μm W=10 μm. 3 2 1 0. 0. 100. 200. 300. Stress Time (min). Fig.2-26. IDSAT degradation with different Stress time 45.

(56) 30. Stress Voltage: VG=VD=1.5V BC-SOI, LG=90nm. 25. ΔIG (%). 20. W=1.2 μm W=5 μm W=10 μm. 15 10 5 0 0. Fig.2-27. ID (μA/μm)). 600 400. 100. 200. Stress Time (min). IG degradation with different Stress time. W=10 μm W=0.9 μm VG=1 V IB=0 A. VG=0~1.2V VB=GND. S. 200 0 0.0. Fig.2-28. 300. IB=0A. 0.2. 0.4 0.6 VD (volts). VD=0~1.2V. G Body D Box. L=90nm 0.8 1.0 1.2. ID-VD characteristics with different width for IB=0. 46.

(57) 1200 Gm/ W (S/μm). 1000. VD=1 V. 800 W=10 μm W=10 μm, IB=0 A W=3.6 μm W=3.6 μm, IB=0 A W=0.9 μm W=0.9 μm, IB=0 A. 600 400 200 0 -0.4. Fig.2-29. 0.8. GM-(VG-VTH) characteristics with different width. 0.5 0.4 VB (volts). 0.0 0.4 VG- Vth (Volts). L =90nm VG=1V W=10 μm W=0.9 μm W=0.45 μm W=0.18 μm. 0.3 0.2 0.1 0.0 0.0. 0.2. 0.4. 0.6 0.8 VD (volts). 1.0. 1.2. Fig.2-30 VB-VD characteristics with different width. 47.

(58) 0.5. L =90nm VD=1V. VB (volts). 0.4 0.3. W=10 μm W=0.9 μm W=0.45 μm W=0.18 μm. 0.2 0.1 0.0 -0.1. -0.4. 0.0. 0.4 0.8 VG (volts). 1.2. Fig.2-31 VB-VG characteristics with different width. 1600. ID (μA/μm)). 1200. W=0.18 μm W=0.45 μm W=0.9 μm W=3.6 μm. W=10 μm. 800 400 L=90 nm VB=VD=1.2. 0 -0.4. Fig.2-32. 0.0. 0.4 VG (volts). 0.8. 1.2. ID-VG characteristics with different width. 48.

(59) 5. (min). BC-SOI L G =90nm. 10. 4. Lifetime. 10. 10. 3. V D =1.5V , Δ I D =5%. W =10 μ m W =5 μ m W =1.2 μ m. 2. 10 0.5. 1.0. 1.5. 2.0. 2.5. 1/V G (volts). 3.0. 3.5. 5. 10. Lifetime (min). FB-SOI LG=90nm. 4. 10. W=10 μm W=5 μm W=2 μm stress Vd=1.5V , Δ ID=5%. 3. 10 0.5. Fig.2-33. 1.0. 1.5 2.0 2.5 1/VG (1/volts). 3.0. 3.5. Width effect on lifetime of 90nm BC-SOI and FB-SOI nMOSFETs. 49.

(60) Inductor A. 7.08 nH. Inductor B. 5.221 nH. Capacitor A. 0.485 pF. Capacitor B. 10.466 pF. Fig.3-1. Fig.3-2. Size Table. Inductor Model. 50.

(61) Q. Inductor. Capacitor. −. imag (Y11 ) real (Y11 ). imag (Y21 ) real (Y21 ). Efficiency. imag (. 1 ) Y11. −imag (Y21 ). Fig.3-3 Formula of Q, Inductance and Capacitance. Fig.3-4. Three interconnection type of BGA structures 51.

(62) Fig.3-5. RF Probe Station. Fig.3-6 Network Analyzer 8364B. 52.

(63) Fig.3-7. Microphotograph of an integrated spiral inductor. Fig.3-8. Microphotograph of a MIM capacitor. 53.

(64) Fig.3-9 Top view of completed flip-chip BGA. Fig.3-10. Bottom of with completed flip-chip BGA. 54.

(65) Cp R S1. R S2. Rp LS C S1. Fig.3-11. C S2. Lumped element model of inductor before packaging. RS. LS. CS2. CS1. Fig.3-12. CS. Lumped element model of capacitor before packaging 55.

(66) Cp L3. R3. L1. R1. RS1. RS2. Rp. R2. L2. R4. L4. LS C3. C1. Fig.3-13. CS1. CS2. C2. C4. Lumped element model of inductor after flip-chip packaging. L3. R3. L1. C3. Fig.3-14. R1. RS. C1. LS. CS. CS2. CS1. R2. C2. L2. R4. C4. Lumped element model of capacitor after flip-chip packaging 56. L4.

(67) Fig.3-15. Fig.3-16. Inductor A before package. Inductor A after flip-chip package 57.