Chapter II SOI nMOSFETs
2.3 Results…
Three topics have been discussed in this section to study in strain technique and body potential: 1) the thickness effect of HS CESL film on SOI nMOSFETs, 2) the effect of devices geometry on SOI nMOSFETs and 3) the impact of Body-Potential on SOI nMOSFETs. The device in topic 1 and 2 is in the same wafer, which were fabricated with a 40 nm Si active layer and 200 nm buried oxide (BOX) on Implanted Oxygen (SIMOX) <100> channel orientation SOI substrate. After STI, 1.6nm nitride gate oxide was grown by rapid thermal oxidation in NO ambient. Next, composite oxide/SiN spacers via low-temperature processing and junctions were formed using arsenic (As) and boron (B) ion implantations. Furthermore, in order to investigate the interactive effect of tensile and compressive stress, devices were fabricated with various thickness of HS CESL (700 A, 1100 A and conventional SiN layer-SiN 380), LOD (0.45~4.5 μm) and gate width (0.18~10 μ m). Finally, devices were metalized using CoSi salicidation. The DC measurements were carried out on HP4156 under various drain voltages (VD=0~1.4 V)
under room temperature (25℃) for 100 min. The device in topic 3 is in another wafer, which were fabricated with 90 nm thick SI active layers, 200 nm thick buried oxide (BOX), using the 90 nm process with STI isolation technology. SOI nMOSFETs with H-gate body-contact (BC-SOI) and without body-contact (FB-SOI) was compared for device performance inspection. Device HCE stressing and measurements were performed on probe station using various drain voltage (VD=0~1.5 V), and various gate voltages (VG=0~1.5 V) with 300 minutes stress time.
2.3.1 The Thickness Effect of HS CESL film on SOI nMOSFETs
The device structure is show in Fig.2-7; it indicates the orientations of stress caused by HS CESL and STI. In x axis, the HS CESL will induce a tensile stress in channel region, and STI will cause a compressive one. The intensity of tensile stress in channel region is related to the thickness of HS CESL film [17]. From previous studied [18], it had been reported that a tensile stress can be induced by the HS CESL, thus enhancing the channel electron mobility due to lighter effective mass of carriers in the strained-Si layer and reduced inter-valley scattering. Thus, thicker HS CESL will induce higher tensile stress, result in more mobility enhancement. However, we believed that a thicker HS CESL will also induce more damages to oxide and oxide/Si interface in channel region, degrading performance of the device. Therefore, device performance can not be improved by simply increasing the thickness of HS CESL. The ID-VD curves of 90 nm SOI nMOSFETs with various HS CESL thicknesses and conventional SiN layer (CN layer) were shown in Fig.2-8. It is apparent that devices with HS CESL possess larger ID
than those with traditional CN layer. As the thickness of HS CESL is increased from 700
A to 1100A, we found that the ID decreases because of the degradation of channel carrier mobility cause by inappropriate high tensile stress induced defects. The transconductance (Gm) versus VG – VTH is shown in the Fig.2-9. We found that the HS CESL will enhance the Gm and mobility. Similar to device’s ID-VD characteristic, the device with 700 A HS CESL possess has higher Gm than the device with 1100 A. Apparent degradation happens on device with 1100 A HS CESL is subject to the higher defect density caused by excess tensile stress. We believed that the HS CESL will induce more interface states; therefore, the VTH is on the rise as the thickness of HS CESL increased. The ID – VG curves were shown in Fig.2-10. In subthreshold region, devices with HS CESL possess larger leakage currents than those with CN layer apparently. This means the tensile stress induced by HS CESL will cause more defects in oxide and oxide/Si interface; which provide more leakage current paths and induce a larger gate induced drain leakage current (GIDL).
In order to inspect the thickness of HS CESL on device’s hot-carrier-induced reliability, devices were stressed with 100 min hot-carrier stressing under VD=VG=1.2 V.
Fig.2-11 and Fig.2-12 show the ID degradation characteristics of 90 nm BC-SOI nMOSFETs with 1100 and 700 A HS CESL. It is obvious that ID has an apparent rise during short time hot-carrier stressing especially for devices with 1100 A HS CESL and then ID degraded after long time hot-carrier stressing especially for devices with 1100 A HS CESL and then ID degraded after long time hot-carrier stressing. From previous studies [19], they reported that holes will be injected into the oxide from the substrate. By the gate tunneling [20], during hot-carrier stressing and these trapped holes are located close to the oxide/Si interface, resulting in device threshold voltage reduction. As the gate oxide continue downscaling, apparent trapped holes were form near the interface and will
be increased during strain stress. Trapped holes in oxide/Si interface will decrease the VTH, result in increased ID. Compared to device with 700 A HS CESL and with 1100 A HSCESL, high tensile stress results in larger numbers of defects near to oxide/Si interface to trap holes, causing VTH degradation and enhancing the ID. Owing to higher impact ionization rate, it is apparently that the devices with 1100 A HS CESL were degraded more seriously after long time hot carrier stressing. The generated defects near to oxide/Si interface will provide more vacancies for charges trapping, resulting in larger gate leakage. GM degradations of devices with 1100 and 700 A HS CESL were shown in the Fig.2-13 and Fig.2-14. Obvious shift and decrease were found on the GM especially for devices with thicker HS CESL. Both shift and decrease in GM were attributed to the larger amount of trapped holes induced a lots of VTH lowering.
2.3.2 The Effect of Devices Geometry on SOI nMOSFETs
The STI induced compressive stresses were divided into x (parallel the channel direction) and y axes (perpendicular the channel direction). In x axis, the intensity of compressive stress for channel center region is related to the length LOD; in y axis, it is related to the gate width. Fig.2-15~Fig.2-17 show the △ID, VTH and △GM versus gate width of 90 nm SOI nMOSFETs with various HS CESL. In Fig.2-15, the ID (719 μA/μm)of device with W=10μm and SiN380 CN layer was used as reference to estimate the deviation of ID. It is apparent that the ID increases as the gate width decreases because the compressive stress (y axis) is increases with the gate width decreases [21]. Narrow gate width device possesses larger drain current density and off-state drain current density, degrading device’s subthreshold slope and lowering the threshold voltage as shown in
Fig.2-16. In Fig.2-17 (standard GMMAX =476 S/μm devices with W=10 μm and SiN380 CN layer), it is obvious that GMMAX (mobility) increase as the gate width reduces.
Fig.2-18 and Fig.2-19 show the △ID and △GM versus LOD of 90 nm SOI nMOSFETs with various gate widths and HS CESL. In Fig.2-18, (reference ID = 735 μA/μm devices with W = 10 μm, LOD = 0.45 μm and SiN 380 CN layer), it is apparent that the ID of devices with wider gate widths (W = 10 μm) increases with the LOD increases because longer distance from gate to STI will weaken the impact of compressive stress (x axis) on channel region, increasing the impact of tensile stress (x axis) indirectly. However, the ID increases and become unapparent LOD dependence for devices with narrower width (W
= 0.9 μm). In Fig.2-20, it is obvious that the total amount of compressive stress in x axis is related to the gate width. Decreasing the gate width will also reduce the amount of induced compressive stress and result an unapparent LOD dependence for ID increasing.
Similar tendency can be found on device’s △GM versus LOD curves (Fig.2-19 reference GMMAX = 483 S/μm devices with W = 10 μm, LOD = 0.45 μm and SiN380 CN layer). For wider gate width devices, GMMAX is increased with LOD increased but the dependence is unapparent for narrower gate width devices. IG versus LOD of 90 nm SOI nMOSFETs with various gate widths and HS CESL was shown in Fig.2-21. It can be found that the LOD effect on gate leakage is very unapparent for all devices. The dominators for gate leakage are gate width and thickness of HS CESL. Devices with wider gate width and thicker HS CESL possess higher gate leakages. Fig.2-22 shows VTH decreases with LOD increase, and devices with 1100 A HS CESL possess a higher VTH than device with 700 A CESL, because higher stress CESL will induce more interface states for electron trapping and raise the V
2.3.3 The Impact of Body-Potential on SOI nMOSFETs
The leakage path impact on body-potential (VB) for FB-SOI nMOSFETs was shown in Fig.2-23, it is apparent that the VB can be affected by gate (IG), junction (IJ), impact-ionization (III) and STI edge (IEL) currents. Fig.2-24 shows the width effect on ID-VD characteristic of 90 nm BC-SOI nMOSFETs. The drain current density (ID/W) increases apparent as the channel width decreases due to the increase of channel edge current [22]. Fig.2-25 shows large channel edge current in narrow channel-width devices will lower the threshold voltage. Hence, for SOI nMOSFETs with width 1.2 μm, apparent ID degradation was happened especially with stressed VG=VD=1.5V. It is due to the large vertical electrical field will increase inversion channel charge and enhance hot carrier effect. Therefore, more serious valence-band electron tunneling was happened, increasing the interface state generation rate, resulting in serious IDSAT degradation (Fig.2-26) and gate leakage variation (Fig.2-27). We believed that the hot-carrier-induced defects at Si-SiO2 interface will cause device’s threshold voltage shift, and provide a gate leakage path for carrier tunneling.
In this work, a method which setting BC-SOI device with IB=0 was used to monitor the VB of FB-SOI device, as shown in inset of Fig.2-28. Fig.2-28 shows that a kink effect will happen on BC-SOI nMOSFETs with IB=0; thus, we believed it is a reasonable way to monitor the characteristic of FB-SOI. Fig.2-29 shows the mobility will increase with channel width decrease for both SOI nMOSFETs. Fig.2-30 shows lower VB was found at narrower channel-width device especially at large VD, and is more sensitive with gate voltage because of gate-induced drain leakage and gate tunneling (Fig.2-31). In order to investigate channel edge leakage, we inspect the ID-VG plot with VB=VD without the
impact of IJ and IG. Owing to IEL, it is apparent that large ID happens especially on narrower channel-width device, as shown in Fig.2-32. Compared with BC-SOI nMOSFETs, FB-SOI device possesses a larger ID due to serious kink effect. Besides, we found that the body potential was also affected by channel width. In this work, lower VB
was found at narrower channel-width device; it is due presumably to fewer hole accumulated at neutral region of substrate. For FB-SOI nMOSFETs, narrower channel-width device possesses lower body potential; thus, higher electric field between body and drain happen, causing larger hot-carrier-induced device degradation. Fig.2-33 shows the lifetime of 90nm BC-SOI and FB-SOI nMOSFETs. Compared with BC-SOI nMOSFETs, FB-SOI device possesses similar trend but with larger lifetim because body potential happen. For 90 nm SOI nMOSFETs with ultra thin gate oxide (TOX = 1.6 nm), the hot carrier was more easy to induce defects at Si-SiO2 interface for narrow width device; which will make worse the IDSAT degradation especially at high stress gate voltage.
Thus for narrow channel-width devices, the hot-carrier-induced degradation will increase with width decrease and with stress gate voltage increase. Moreover, for FB-SOI device, we believe that the body potential will suppress the field between drain to body, thus alleviate the hot-carrier-induced device degradation.