6.1. Conclusions
There are several previous works addressing the influences of gate-tunneling current on nanoscale CMOS ICs. For the ICs implemented in nanoscale CMOS processes, the gate leakage issue needs to be taken into consideration due to the thin gate oxides. In this thesis, a new low-leakage power-rail ESD clamp circuit designed with the consideration of gate-leakage issue has been proposed and verified in 90-nm and 65-nm CMOS processes. In the proposed power-rail ESD clamp circuit, the leakage current is significantly reduced even though only thin-oxide devices are used.
Measured results have shown that the traditional designs have suffered such a serious leakage current. The leakage current under normal circuit operating conditions has been demonstrated to be significantly reduced in the proposed low-leakage power-rail ESD clamp circuit. Realized with only thin-oxide devices, the proposed power-rail ESD clamp circuit has much lower leakage current as compared with the traditional designs. Moreover, the ESD robustness is not deteriorated and the circuit area is not increased. In this thesis, the ESD clamping device in all power-rail ESD clamp circuits is the substrate-triggered SCR. Since the holding voltage of SCR is higher than the power-supply voltage, it can be used as the ESD clamping device without causing latchup issue.
6.2. Future Works
Although low leakage current and high ESD robustness have been achieved in the proposed power-rail ESD clamp circuit, there are still some drawbacks in the new proposed low-leakage power-rail ESD clamp circuit. Since the gate voltage of the MOS capacitor is biased by the diode-connected PMOS transistors, the ESD voltage is easily coupled to the gate terminal of the MOS capacitor during ESD stresses. Due to the capacitive coupling effect caused by the diode-connected PMOS transistors, the actual delay time provided by the RC timer is decreased than the expected value. As a result, the trigger ability during ESD stresses is degraded. Besides, using the
diode-connected PMOS transistors between VDD and VSS causes some static current flowing through them under normal circuit operating conditions. This static current is undesired and needs to be eliminated. In order to solve the problems in the proposed power-rail ESD clamp circuit, some techniques need to be developed in the near future.
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