ESD Robustness of Traditional and New Proposed Power-Rail ESD Clamp Circuits ESD Clamp Circuits

In test chip fabricated in a 65-nm CMOS process, when a 5-V ESD-like voltage pulse with 2-ns rise time and 100-ns pulse width is applied to the VDD node of three power-rail ESD clamp circuits, the VDD voltage is rapidly clamped to around 2 V within 5 ns, as shown in Fig. 4.17. The measured turn-on efficiency have demonstrated that the internal circuits can be well protected by the new proposed power-rail ESD clamp circuit. The human-body-model (HBM) and machine-model

(MM) ESD robustness among these three power-rail ESD clamp circuits have been characterized and listed in Table 4.4. The new proposed design has the ESD level of over 8 kV in HBM and 750 V in MM, respectively. Besides much lower leakage current, the proposed power-rail ESD clamp circuit can achieve comparable ESD robustness as compared with the traditional power-rail ESD clamp circuits.

The turn-on efficiency has also been investigated for the test chip fabricated in a 90-nm CMOS process. When a 5-V ESD-like voltage pulse with 2-ns rise time and 100-ns pulse width is applied to the VDD node of three power-rail ESD clamp circuits, the VDD voltage is rapidly clamped to ~ 2.5 V within 5 ns, as shown in Fig. 4.18.

Thus, the internal circuits can be also well protected by the new proposed power-rail ESD clamp circuit in a 90-nm CMOS process. With a holding of ~2.5 V, the SCR did not cause latchup trouble for 1-V IC applications. The HBM and MM ESD robustness among these three power-rail ESD clamp circuits fabricated in a 90-nm CMOS process are listed in Table 4.5. The new proposed design has the same ESD levels as those of the traditional power-rail ESD clamp circuits, which are over 8 kV in HBM and 500V in MM.

Table 4.1

MOS capacitor measured gate leakage current at VG = 1 V under different temperatures

Table 4.2

Measured leakage currents of power-rail ESD clamp circuits in a 65-nm CMOS process

Table 4.3

Measured leakage currents of power-rail ESD Clamp circuits in a 90-nm CMOS process

Table 4.4

HBM and MM ESD robustness of power-rail ESD clamp circuits in a 65-nm CMOS process

Table 4.5

HBM and MM ESD robustness of power-rail ESD clamp circuits in a 90-nm CMOS process

(a)

(b)

Fig. 4.1 65-nm CMOS process test chip: (a) Layout top view of the test chip (b) Die photo of the test chip.

(a)

Fig. 4.2. 90-nm CMOS process test chip: (a) Layout top view of the test chip (b) Die photo of the test chip.

Fig. 4.3. Measured gate leakage current of the 65-nm NMOS capacitor at different temperatures.

Fig. 4.4. Measured gate leakage current of the 65-nm PMOS capacitor at different temperatures.

(a)

(b)

Fig. 4.5. Substrate-triggered SCR: (a) Layout top view and (b) Cross-sectional view of the substrate-triggered SCR.

(a)

(b)

Fig. 4.6. SCR characteristics in a 65-nm CMOS process: (a) SCR leakage current at different temperatures. (b) SCR DC I-V curves at different temperatures.

(a)

(b)

Fig. 4.7. SCR characteristics in a 90-nm CMOS process: (a) SCR leakage current at different temperatures. (b) SCR DC I-V curves at different temperatures.

Fig. 4.8. Traditional power-rail ESD clamp circuit. SCR is used as the ESD clamping device.

Fig. 4.9. Traditional power-rail ESD clamp circuit with the PMOS restorer. SCR is used as the ESD clamping device.

Fig. 4.10. New proposed power-rail ESD clamp circuit with SCR as the ESD clamping device.

Fig. 4.11. Comparison of the leakage currents among the traditional and the new proposed power-rail ESD clamp circuits in a 65-nm CMOS process with different VDD biases at room temperature of 25 °C.

Fig. 4.12. Comparison of the leakage currents among the traditional and the new proposed power-rail ESD clamp circuits in a 65-nm CMOS process with different VDD biases at high temperature of 125 °C.

Fig. 4.13. Comparison of the leakage currents at 1-V VDD among the traditional and the new proposed power-rail ESD clamp circuits in a 65-nm CMOS process at different temperatures.

Fig. 4.14. Comparison of the leakage currents among the traditional and the new proposed power-rail ESD clamp circuits in a 90-nm CMOS process with different VDD biases at room temperature of 25 °C.

Fig. 4.15. Comparison of the leakage currents among the traditional and the new proposed power-rail ESD clamp circuits in a 90-nm CMOS process with different VDD biases at high temperature of 125 °C.

Fig. 4.16. Comparison of the leakage currents at 1-V VDD among the traditional and the new proposed power-rail ESD clamp circuits in a 90-nm CMOS process at different temperatures.

Fig. 4.17. Comparison of the turn-on efficiency among the three power-rail ESD clamp circuits in a 65-nm CMOS process under the applied 5-V voltage pulse with a rise time of 2ns and a pulse width of 100ns.

Fig. 4.18. Comparison of the turn-on efficiency among the three power-rail ESD clamp circuits in a 90-nm CMOS process under the applied 5-V voltage pulse with a rise time of 2ns and a pulse width of 100ns.

Chapter 5 Discussions

The proposed ESD-detection circuit (shown in Fig. 3.5) uses diode-connected PMOS string to reduce the voltage across the MOS capacitor. With the proposed design, the leakage current through the MOS capacitor is reduced and the turned-off ability of the trigger PMOS (M_P1) is enhanced under normal circuit operating conditions. Thus, the proposed design does not suffer incorrect function and generates large leakage current. Besides, the diode-connected PMOS string is a good voltage divider. Even if there is a large variation in temperature, it still provides a regular voltage value, as shown in Fig. 6.1. The difference between VB at 25 °C and 125 °C is only 8 mV. With the regular voltage of VB, the circuit function is not affected at high temperature under normal circuit operating conditions. Since MP1 is at the subthreshold region, slight increase of gate voltage causes significant subthreshold leakage current. The leakage current of the proposed ESD-detection circuit can be divided into three parts, the first part is through the diode-connected PMOS string; the second part is through the MOS capacitor, and the third part is through the trigger PMOS (MP1) and NMOS (MN1). The third part dominates the overall leakage current under normal circuit operating conditions due to the subthreshold leakage current of large trigger PMOS (MP1) transistor.

In the test chip in a 90-nm CMOS process, the leakage currents of these three power-rail ESD clamp circuits become close when the temperature is increased. The test chip was fabricated in a low-leakage 90-nm CMOS process, so the thick-oxide MOS capacitor does not have obvious gate-leakage current, as described in section 3.1. The leakage currents of different power-rail ESD clamp circuits are dominated by the subthreshold leakage current of MOS transistors. The proposed design enhances the turned-off ability of the trigger PMOS (M_P1), so the subthreshold current is smaller than that in the traditional designs under low temperatures. These three power-rail ESD clamp circuits use the same size of trigger PMOS (M_P1) and NMOS (M_N1), and the increase of subthreshold leakage current correlated closely with temperature. Since the subthreshold leakage current of MOS transistor dominate the overall leakage current, the leakage currents of these three power-rail ESD clamp

circuits became close when temperature is increased.

In the test chip in a 65-nm CMOS process, the thin-oxide MOS capacitor has large gate-leakage current, so the traditional ESD-detection circuit can not work correctly and it generates large leakage current, as the measured results shown in section 4.x. Although adding the PMOS restorer can enhance the turn-off ability of the trigger PMOS (MP1) and reduce the leakage current, the leakage current through the MOS capacitor is still too large. The overall leakage current in the proposed design is dominated by the subthreshold leakage current of MOS transistors, which is increased significantly as the temperature is increased, as shown in Fig. 6.2. Since the trigger MOS transistors in the traditional designs are already turned on under normal circuit operating conditions, the increase of leakage current is slighter than that of the proposed design as the temperature is increased.

Fig. 5.1. Voltage of V_B under different temperatures.

Fig. 5.2. Subthreshold leakage current of MP1 under different temperatures.

Chapter 6