Energy efficient and ultra-low voltage circuits is a key focus in emerging design trend.
In this thesis, a fully integrated area-efficient and ultra-low power temperature sensor is presented. It can provide vital environmental data to overcome PVT variations and enhance energy efficiency. With our sensor, a locking range compensation technique of near-/sub-threshold regions is applied for our DLL-based clock generator. A prototype test chip of ultra-low voltage FIFO memory in dynamic voltage frequency scaling (DVFS) platform is presented to combine the benefits of proposed energy efficient designs with a practical implementation of power management controller for energy efficient chips.
The previous works on energy efficient techniques and wireless body area sensor net-works (WBANs) applications are introduced in Chapter 2. A frequency-domain tem-perature sensor is presented in Chapter 3 to enable on-chip temtem-perature measurement.
The sensor was designed to achieve ultra-low voltage operation with reasonable process variation immunity. A test chip had been fabricated in TSMC general purpose 65nm CMOS technology meets the target to be capable of 0.4V supply voltage operation over the temperature range of 0◦C to 100◦C. The power consumption per conversion rate is 11.6pW/samples/sec, which is a hundredfold improvement over previous work [6.1, 6.2].
A programmable clock generator was proposed for a near-/sub-threshold dynamic volt-age and frequency scaling system. With the proposed PVT compensation technique, the clock generator could be prevented from the PVT variations under the ultra-low voltage operations from 0.2V to 0.5V. The proposed clock generator has been implemented in
UMC 65nm CMOS technology. The measurement results report the corresponding power consumptions are 5.17µW at 0.5V, 20MHz and 0.18µW at 0.2V, 625kHz, respectively.
It is suitable to be the clock source for emerging ultra-low voltage energy-constrained applications.
In Chapter 4, a 9T bit-cell is proposed to enhance write ability by cutting off the positive feedback loop of SRAM cross-coupled inverter pair. In read mode, an access buffer is designed to isolate storage node from read path for better read robustness and leakage reduction. Bit-interleaving scheme is allowed by incorporating the proposed 9T SRAM bit-cell with additional write-wordlines (WWL/WWLb) for soft error tolerance.
A 1Kbit 9T 4-to-1 bit-interleaved SRAM is implemented in 65nm bulk CMOS technology.
The experimental results demonstrate that the test chip minimum energy point occurs at 0.3V supply voltage. It can achieve an operation frequency of 909kHz with 3.51µW active power consumption. Meanwhile, an ultra-low power (ULP) 16Kb SRAM-based first-in first-out (FIFO) memory is proposed for wireless body area networks (WBANs).
The proposed FIFO memory is capable of operating in ultra-low voltage (ULV) regime with high variation immunity. An ULP near-/sub-threshold 10 transistors (10T) SRAM bit-cell is proposed to be the storage element for improving write variation in ULV regime and eliminate the data-dependent bit-line leakage. The proposed SRAM-based FIFO memory also features adaptive power control circuit, counter-based pointers, and a smart replica read/write control unit. The proposed FIFO is implemented to achieve a minimum operating voltage of 400mV in UMC 90nm CMOS technology. The write power is 2.09µW at 50kHz and the read power is 2.25µW at 625kHz.
An ultra-low voltage asynchronous first-in first-out (FIFO) memory is proposed for wireless body area networks (WBANs) in Chapter 5. For the ultra-low power consid-eration, a novel ultra-low power subthreshold 8-transistor (8T) SRAM cell is presented, which improves write margin and reduces write variation in subthreshold regime. Reverse short-channel effect (RSCE) is utilized in read-buffer and write access transistor to im-prove read/write ability. In addition, an adaptive write-word-line window control scheme is proposed for lower write power and process-voltage-temperature (PVT) tracking. A 1kb dynamic voltage scaling 8T SRAM-based FIFO memory is implemented to operate
between 0.5V (near-threshold) and 0.3V (subthreshold) in UMC 65nm technology with 0.535µW at 625kHz and 0.163µW at 20kHz power consumption, respectively. The pro-posed DVS FIFO memory can provide up to 69.5% power savings when low-power mode is always engaged, and there is no power overhead if the period of low-power mode is longer than 48.66µs. It is suitable for healthcare applications equipped with DVFS capability.
Figure 6.1: Proposed power management system architecture.
In this work, only fixed dual voltage supply scheme is chosen because it is enough for energy efficient WBANs applications. However, dynamic multiple voltage supply scheme is preferred for minimum energy point tracking. In order to provide multiple voltage sources for DVFS energy efficient chips, we presented a power management system for solar energy harvesting applications in [6.3]. It receives power from photovoltaic (PV) cell and generate different voltage levels, they are 1V-0.3V for analog circuitry and low power digital circuitry, -1.2V for super-cutoff technique in memory circuitry, and 10V for FLASH memory or I/O components. Among the proposed power management system, high power efficient switched capacitor (SC) DC-DC converter and voltage regulator are two key components. Fully digital controlled voltage regulator was first presented in [6.4].
It has high current efficient of 99.8% with only 164.5µA quiescent current. However, the accuracy of the digital error detector in the proposed voltage regulator is heavily affected by PVT variations. Therefore, variation-aware voltage regulator and SC DC-DC converter require more research efforts for DVFS platform.
Another interesting research topic is utilizing the proposed temperature sensor in Chapter 3 for our proposed DVFS platform shown in Fig. 6.2 and TSV 3D-IC package
Figure 6.2: PVT-aware ultra-low voltage DVFS FIFO system.
Figure 6.3: PVT sensors for 3D-IC package technology.
technology shown in Fig. 6.3. Our high area-/energy-efficient temperature sensor can be deployed several hundred sensors within every layers of 3D-IC chips. With rich temper-ature information, an advanced dynamic tempertemper-ature management unit is an interesting research topic to provide a smart solution for hot-spot issue.