Chapter 3 A BIST Scheme for Detecting Crosstalk Faults Using Squarewave Test
3.5 Fault Coverage Estimation through Fault Simulation
3.5.1 Symbol Definition and Operation
To perform fault simulation, a set of symbols are first introduced and defined and a set of
operation rules on them are defined for each type of gates. The set of symbols are shown in
Figure 2-2, where C, and C* are fault effect signals which are to be propagated and detected at
the output, PF and PF* are potential fault effects which could be 1 or C and 0 or C*
respectively, S and S* are oscillation squarewave signals which are to be applied at the fault
site, and x represents for an “unknown” value. Figure 2-2(b) shows examples on how these
symbols are operated through an & (AND) gate. For examples, C & C* results in PF* and C
& C results in C. Figure 2-2(c) shows the truth tables for AND and OR operation respectively.
In the table, it can be seen that these sets of operations are rather conservative. For examples,
when S operates on S (or S*), an x is given, which indicates an “unknown”, while for
practical cases, most often an S (or S*) is obtained.
3.5.2 Fault Simulation
For fault simulation, when a test pattern is applied to the circuit, a fault free logic is
firstly computed with the set of variables and operation rules defined above. Then a fault is
injected to see if the aggressor line is at the S (oscillation) path. If the aggressor line is at the
oscillation path, the victim line of the fault site is set to C, and it is propagated toward the
output of the circuit. If the propagation is successful, the crosstalk fault is detected by the
pattern and another fault is injected. The above process is repeated until all faults are injected
and another pattern is simulated.
3.6 Experimental Results
Firstly, the circuit level simulation for the proposed detection circuit was done. Figure
3-8 shows the simulation results of the modified boundary scan-out cell of Figure 3-5 under
the patterns of Figure 3-3. In the figure, the clock signal TCK, the squarewave test signal Sq,
the control signals DMLE and Detck for DM and ED respectively are displayed with the
simulated signals at FC (the input of the cell where the induced glitches comes in), F (the
output from XOR2), and Out (the output of the detector of the boundary cell). When DMLE
is “high”, i.e., the circuit is at the stable logic latch phase, for which Detck is at “high”, even
there is an induced glitch at FC (at 3.3 ns) the DM does not detect the glitch and the output of
the boundary cell, Out is “low”. When DMLE is “low” (the oscillation test phase), if the
glitch occurs at the time slot when Detck is “low” (at 7 ns), it is detected by the circuit and
Out is “high”.
TCK
S
DMLE
Detck
FC
Out F
Phase 1 2 3 2
Figure 3-8. Hspice simulation waveforms of modified boundary scan-out cell in Figure 3-5.
To estimate the efficiency of random test patterns to detect crosstalk faults, we did
experiments on randomly generating patterns to apply to benchmark circuits [22] for which
crosstalk faults are randomly injected to be detected by the patterns. A fault simulator based
on the symbols and operation rules in the previous section was implemented to evaluate the
fault coverage of the patterns. In the experiment, for each circuit, two different
non-overlapped separate sets of random crosstalk faults were generated, and the number of
faults is twice the number of gates. For each fault set, two separate sets, each with different
seed for pattern generation, of random patterns were generated. Figure 3-9 shows results for
some benchmark circuits (C2670, C5315, C6288, S13207c, S15830c, and S35932c, where c
represents for the combinational part of the circuit) where fault coverage curves are plotted
with respect to the number of patterns/fault. In the figure, S1 and S2 represent for two
different fault sets and RP1 and RP2 represent for two different sets of random patterns. It can
be seen that, similar to the stuck-at fault random testing, the fault coverage increases fast
C5315, 4970 faults
0 0.002 0.004 0.006 0.008 0.01
patterns / fault
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 patterns / fault
S1RP1 S1RP2 S2RP1 S2RP2
Figure 3-9. The fault coverages versus the number of patterns/number of faults for circuits C5315, C6288, S13207c, S15830c, S35932c, and S38584 respectively.
initially for some initial number of patterns and when it reach a “saturated” number it then
increases slowly afterward. The saturated fault coverage depends strongly on the type of the
circuit.
For examples, for circuits: C5315, S13207c, S15830c, and S35932c, which mainly are
circuits of larger sizes, it can easily reach 90%, but for circuit C6288, which is a multiplier, it
can only reach 30%. Also, since the faults were randomly selected, some of them may be
untestable faults. The fault coverage also depends somewhat on the set of random test patterns
which are generated with different seeds of LFSRs. However, the difference of the fault
coverage between two sets of patterns is generally small, which is within 2%. This means that
for an arbitrary set of random patterns, it can detect crosstalk fault quite efficiently. This
makes this BIST scheme very attractive in the practical application.
Table 3-1 compiles more detail simulation results of some benchmark circuits, in
addition to the above four circuits. In the table, similarly, for each circuit, the number of faults
is twice the number of gates of the circuit and the faults were randomly selected. The column
of “Saturated Pattern” is the number of random patterns which were generated by the
software LFSR when the fault coverage reaches the “saturated” value, which is shown in the
column “ Saturated Fault Coverage”. The “Potential Detectable Fault Coverage” is the
fault coverage for which the faults were potentially detected when one (or more) PF or PF* is
detected at the circuit output(s). In the table, it can be seen that for most of circuits, the
saturated fault coverage can be reached over 90% with a number of patterns considerable less than the number of faults.
Table 3-1. Fault simulation results of the proposed BIST scheme for crosstalk faults.
c2670 157 2700 2700 69.07 7.11
c3540 50 3438 3426 83.33 8.20
c5315 178 4970 4899 94.81 2.90
c6288 32 4896 3741 28.82 13.01
c7552 206 7436 3896 90.14 3.28
s3271c 142 3428 2430 97.52 0.90
s3330c 172 3922 3879 79.40 0.33
s3384c 209 3788 2352 93.98 0.37
s4863c 153 4990 4115 94.71 0.54
s5378c 214 5986 3918 97.24 0.60
s6669c 312 6784 1643 98.28 0.25
s9234c 247 11688 1718 83.10 0.48
s13207c 650 17202 436 92.34 0.11
s15850c 600 20744 419 92.98 0.10
s35932c 1763 35656 87 96.85 0.44
s38584c 1462 41430 94 90.61 1.51
Saturated
In this chapter, a BIST scheme to detect crosstalk faults in the boundary scan
environment for deep sub-micron VLSI is proposed. The scheme uses an oscillating
squarewave signal, which can be easily either generated locally or supplied externally, to test
crosstalk faults of the circuit if they possibly exist, with no need of any external ATE. It needs
only minor modification on boundary scan cells, which are transformed into a signal
generator and some simple detection circuit to detect pulses which are induced by crosstalk
faults of the circuit. Simulation results show that the scheme can detect most of the crosstalk
faults, up to a fault coverage over 90%, with a small number of random patterns for most of
large size of circuits.
Chapter 4
Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle
4.1 Preliminary
As mentioned in the Introduction chapter, as the process technology enters the deep
sub-micron SoC era, asides the conventional stuck-at fault testing, delay and crosstalk of a
circuit are two important issues to be tested to guarantee the performance of a semiconductor
chip. For the delay testing, it is to detect timing defects to ensure that the manufactured chips
meet the desired timing specifications. For the crosstalk testing, it is to test if the desired
function of a circuit goes erroneously or even corrupted due to interference between internal
lines or nodes within the circuit when the circuit operates at the specified frequency. Much
research had been dedicated to topics of testing these two types of faults [10, 14, 22, 28, 33,
41, 43, 49, 58, 62, 76-88].
For delay fault testing, fault models were first issue considered [76]. Among many delay
fault models, the path delay fault model is considered to be the most realistic model since it
covers cumulative effects of defects occurring on a path, either on devices or interconnection
lines, caused by wafers themselves or various process misalignments. Test generation and
fault simulation targeting for this fault model had been extensively investigated [76-85]. For
examples, Smith, in addition to first addressing the path delay fault, presented a framework
for its fault simulation [76]. Test generation for robust path delay faults was addressed by Lin
and Reddy [77], and also by Hsieh, et al [78]. An ATPG system for path delay fault was
proposed in [79]. Pseudo-random test generation approach was also investigated [80].
Simulation issues on delay faults were discussed in [81]. An approach by formulating the
delay testing problem as an energy minimization problem was also proposed in [82].
Statistical issues and approaches on detecting delay faults were also presented [83-85]. For
example, in [83], a technique to statistically estimate path delay fault coverage is presented. In
[840], a framework to diagnose parametric path delay faults based on statistical timing
analysis is proposed, and in [85], a statistically timing analysis based on Monte Carlo
simulation is presented. In all the approaches of testing the path delay fault, two patterns are
needed, i.e., the first pattern is to initialize the path and the second pattern is to activate the
path and propagate the fault effect to be observed at the output. Also, very often a special
timing consideration should be taken in applying the above two patterns.
In [94], an innovative scheme was proposed and demonstrated to detect path delay faults.
The scheme, instead of applying a two-vector pattern, propagating it along the
path-under-detect (PUD) and observing the transition at the output of the PUD at the specified
time, applies a pulse to the input of the PUD. The pulse has a critical width which contains
just enough energy to conquer the path delay inertia to be propagated to the output of the PUD.
Since the path delay of the PUD is proportional to the path delay inertia of the PUD, any
erratically longer delay on the PUD will increase the path delay inertia of the PUD. As a result,
the pulse can not be propagated to and detected at the output of the PUD. Hence, by detecting
the pulse of the critical width, we can tell if the PUD has a path delay exceeding the specified
value. Figure 4-1 is an inverter chain example of the test scheme. The simulation waveforms
at the nodes B and C, which are the nodes before and after the connected latch, of an inverter
chain for which several pulses of different widths are applied. In the figures, the horizontal
axis is time and the vertical axis is voltage amplitude of waveforms. The pulses, as
propagating along the chain, deteriorate gradually. For the pulses of their widths are not large
enough, they deteriorate to a degree that they can not trigger the latch (pulse widths: 33 and
63 ps). For the pulse of the width of 123 ps, it can propagate through the inverter chain of 20
stages. Since the delay of the chain is directly related to the length of the chain (Figure 4-1(b)),
by controlling the width of the applied pulse and observing the triggering of the latch, one can
tell if the path delay exceeds the specified value. The scheme is very simple in detecting the
delay faults of a circuit since it eliminates the complicated timing issues in generating and
applying two-vector patterns.
(a)
(b)
Figure 4-1. (a) Two inverter chains of 10 stages and 20 stages applied with input pulses of different widths and the simulated waveforms at nodes B and C; (b) The propagation delays of two inverter chains. The horizontal axis is time and the vertical axis is the amplitude voltage of the waveforms
In this chapter, we extend the above mentioned scheme to detect the crosstalk faults of
interconnects of SoC. This makes the detection of crosstalk faults be simple and effective. In
the text which follows, we first describe the basic idea how the scheme can be extended to
detect the crosstalk fault in section 4-2; then we present the sensitivity analysis of the scheme
in section 4-3; and then present the experimental results of the scheme in section 4-4.
4.2 Basic Idea of the Detection Scheme
As mentioned previously, the scheme is based on the path delay inertia principle. In the
following, a transmission line model is utilized to explain the working principle of this
scheme.
Figure 4-2 shows two transmission lines, one of which is the aggressor line and the other
is the victim line and there is a coupling capacitance, i.e., coupling fault, in-between these two
lines. In the figure, Rs and Cs are distributed intrinsic resistance and capacitance of
transmission lines respectively, Cc is the intrinsic distributed coupling capacitance between
two interconnection lines and Cf is the coupling capacitance which causes the crosstalk fault.
For the victim line, there is a pulse detector connected at the output. As the victim line is
applied a pulse with large enough width, the pulse will be propagated along the line and be
detected by the pulse detector. However, if the width of the pulse is not large enough, i.e., it
contains not enough energy to “conquer” the path delay inertia of the victim line, the pulse
will not be detected by the detector. The critical width of the pulse is called “critical width”,
CW, and the pulse of the critical width is called “critical width pulse”, CWP. Figure 4-3 shows
the SPICE simulation of two pulses applied at the input of the victim line (Figure 4-3(a)),
where Pa has a pulse width smaller than the CW and Pb has a width larger than CW. The Pa
pulse, when propagating to the output of the line, has a degraded shape (Figure 4-3(b)) and
not able to trigger the detector (Figure 4-3 (c)), while Pb can still maintain its shape, i.e.,
contains enough energy to trigger the detector.
Ai
Figure 4-2. The transmission lines model used to explain the technique, where one is the aggressor line and the other is the victim line, and Cf is the crosstalk capacitance which causes the crosstalk fault.
Figure 4-3. The SPICE simulation waveforms of two pulses, Pa and Pb, of various widths (a) at the input and (b) at the output of the victim line and (c) at the output of the detector.
Now, in figure 4-2, as the victim line has been applied a CWP pulse which causes
triggering of the pulse detector, but a transition signal which transits in the opposite polarity
of the CWP pulse is applied at the aggressor line. This transition signal will affect the CWP
pulse in shape. Figure 4-4 shows the SPICE simulation waveforms of the interconnection
lines of Figure 4-2 with a transition wave applied at the aggressor line of node A1 (Figure
4-4(a)). The CWP pulses arrive at the node V2 of victim line (Figure 4-4(b)) and the output of
the detector (Figure 4-4(c)) are also shown. In Figure 4-4 (b), there are two CWP pulses
applied at two different time. For the CWP pulse where there is no transition wave applied at
the aggressor line, it maintains its original shape, but for the CWP where a transition wave
applied at the aggressor line at the same time, its waveform is the superposition of its original
wave and the induced glitch caused by the aggressor line transition wave through the crosstalk
capacitance [14]. This affected CWP pulse can not trigger the detector anymore. The larger Cf,
the more the CWP is affected. To make the CWP able to trigger the detector again, it needs to
increase the width of the CWP. That is, the presence of Cf and the applied transition testing
pattern at the aggressor line have changed the CW of the CWP of the victim line! Hence, by
applying a CWP to the victim line and an opposite-polarity transition pattern to the aggressor
line, we can detect the crosstalk fault by observing the switching of the pulse detector.
Figure 4-4. The SPICE simulation waveforms of (a) the applied transition wave at the node A1 of the aggressor line, (b) the affected CWP pulses of the victim line at the node V2, and (c) the output of the detector.
4.3 Analysis of the Scheme via Simulation
This section shows the analysis of the scheme via SPICE simulation for an
interconnection line pair. The parameters for the transmission line model are: transmission
lines are 400um long, 0.23um wide with a 0.23um line spacing, Rs = 7.8*10-2 Ω/□, Cs =
1.987*10-2 fF/um and Cc = 1.05*10-1 fF/um.
4.3.1 Relationship of CW of Pulse versus the Crosstalk Fault
It is first to investigate the relationship between the CW of the CWP with respect to the
magnitude of the crosstalk fault. The simulation is for both cases that the victim line is applied
a “1” pulse (P1) and a “0” pulse (P0) respectively and the aggressor line is applied an opposite
transition wave respectively. Figure 4-5 shows the results where the CW of the pulses is
plotted in terms of the magnitude of the crosstalk fault, Cf. It is seen that the relationship is
linear. The Cf = 0 corresponds to the case that there is no crosstalk fault coupling between the
aggressor line and the victim line. For example, to detect a crosstalk fault of 45 fF, which is
about the value of the intrinsic coupling capacitance between the two interconnection lines,
the P1 CWP to be applied to the input needs to have a CW of 0.228 ns as compared to the
original CW = 0.161 ns for which there is no crosstalk fault. The results for P1 and P0 are
somewhat different. For the P0 case, it needs a larger CWP than that of the P1 case, but the
slope, the P1 case (1.48ps/fF) has a higher value than that of the P0 case (0.83ps/fF). This is
because, for the P1 pulse, the rising edge of the pulse needs the pMOS of the driver of the
interconnection line to charge the line but the pMOS has a less driving ability than that of the
corresponding nMOS of the driver. To facilitate the crosstalk fault testing, the higher
sensitivity pattern, i.e., P1, is preferred since this makes differentiate crosstalk easy.
sam e tim e (400um )
Figure 4-5. The CW plotted in terms of the crosstalk fault, Cf, for the cases of P1 and P0. The slope for the P1 case is 1.48 ps/fF and that for the P0 case is 0.83 ps/fF.
Figure 4-6 plots the same CW curves with respect to Cf for P1 and P0 cases for
several different lengths of interconnection lines. It is seen that the longer
interconnection lines, the larger CWP’s, but the slope is the same.
0.100 several different lengths of interconnection lines.
4.3.2 Relationship between Induced Victim Line Delay and Crosstalk Fault
Crosstalk faults induce delay on the victim line when the aggressor line is applied
an opposite-polarity going transition wave [10, 33, 73, 79, 88]. The relationship
between the induced delay and the magnitude of the crosstalk fault of the system in
Figure 4-2 is also investigated. Figure 4-7 shows the results for the P1 case for several
lengths of the interconnection line. The relationship is also linear as it is apparent to
see since the system in Figure 4-2 is a linear system. In the figure, the points Cf = 0
correspond to the case that no crosstalk faults exist and the delays are the original
delays of each interconnection line. For example, for the 400 um interconnection line,
the delay on the victim line without the crosstalk fault is about 0.284 ns, and for a 45
fF crosstalk fault, it will increase to 0.330 ns.
Victim line transition at the sam e tim e
0.25
Figure 4-7. The simulated induced delay on the victim line of different lengths in terms of the magnitude of the crosstalk fault when the aggressor line is applied an opposite-polarity going transition.
The slope of each line in the figure is about 1.02ps/fF. Combing this value with that of
the P1 case, which is 1.48 ps/fF, of Figure 4-5, we can derive the sensitivity of the CW of the
CWP applied to the victim line for crosstalk fault testing with respect to the induced delay
caused by the aggressor line to be 1.45. This indicates that, to detect 1 ps induced delay
caused by the aggressor line to the victim line, it needs to extend 1.45 ps of the original CW
of the applied CWP. Hence if the specified allowable crosstalk induced delay is 0.1 ns,
of the applied CWP. Hence if the specified allowable crosstalk induced delay is 0.1 ns,