Chapter 2 A Test Scheme for Crosstalk Faults Based on the Oscillation Test Signal
2.5 Summary
In this chapter, we propose a test scheme to test crosstalk faults. It uses an oscillation
signal applied on an aggressor line and detects induced pulses on a victim line if a crosstalk
fault exists between these two lines. It is simple and eliminates the complicated timing issue
during test generation for the crosstalk fault. The scheme is very simple and easy to be
implemented. Two test generation approaches, i.e., the guided random test generation and the
deterministic test generation are described and experimental results are presented. The
experimental results show that the proposed test generation approach, i.e., it first uses the
guided random test generation then a deterministic approach can effectively generate crosstalk
fault test patterns for circuits.
Chapter 3
A BIST Scheme for Detecting Crosstalk Faults Using Squarewave Test Signal in Boundary Scan Environment
3.1 Preliminary
The basic difficulty on testing crosstalk faults is that they are pattern-dependent and are
highly unpredictable in nature. To generate test patterns to deterministically detect them, a
timing analysis program of high precision needs to be employed, and this takes much
computation time. In chapter 2, a test scheme which is based on an oscillation signal was
proposed. In the scheme, the oscillation test signal is applied on the aggressor line and the
induced glitches at the victim line are detected if a crosstalk fault between these two lines
exists. The scheme eliminates the need to consider the timing issue of faults, since as long as
the induced glitches, which are induced by the crosstalk fault and usually are induced
unexpectedly, exist, they will be detected at the output of the victim line. A guided random
test pattern generation was also proposed in subsection 2.3.1 of chapter 2, and the test scheme
was shown in Figure 2-3. It is very suitable to apply the test scheme to be BIST, because the
random pattern can be generated by LFSR. The simulation result for the test scheme was list
in table 2-3. It showed that the test scheme had high fault coverage for most benchmark
circuits except the C6288.
In this chapter, the test scheme is modified to be applied to test this type of crosstalk fault
of the unexpected glitches of embedded circuits in the boundary scan environment of a VLSI.
The scheme tests crosstalk faults with the squarewave test signal under applied random
patterns which are generated by the LFSR which is trans-configured by boundary scan cells of
the embedded circuit. The scheme is very simple in test generation and test application with
no need to consider the timing issue of fault occurrence. Experimental results show that
considerable high (> 90%) fault coverage can easily be obtained for detecting the induced
glitch type of crosstalk fault for large size benchmark circuits [75]. In the following sections,
the test scheme is described in section 3.2, and the detail BIST circuit is shown in section 3.3.
The boundary scan circuits, including boundary scan-in cells and boundary scan-out cells,
should be modified for implementing the test scheme. The modified boundary scan cells and
the detection circuit are described in section 3.4. In section 3.5, the experimental results which
are simulated by C program are shown to manifest the practicability of the test scheme.
3.2 The Test Scheme
The basic idea, which is similar to the idea shown in chapter 2, behind the test scheme is
described in subsection 3.2.1. In subsection 3.2.1, the test scheme architecture which is based
on the boundary scan environment.
3.2.1 Basic Idea
Figure 2-1 is a circuit example which demonstrates the basic idea of the detection of
crosstalk faults by using the oscillation squarewave signal. In the figure, A, B, C, D and E are
inputs, O1, O2 and O3 are outputs, line X is the aggressor line, line Y is the victim line, and the
coupling capacitor C represents a coupling fault between lines X and Y. A random test pattern,
{1, S, 1, 0, 0}, where S stands for an oscillation square wave signal, is applied to the input and
the output will be {O1, O2, O3 = S, 0, 1} if the circuit is fault free, where O1 = S means that an
oscillation squarewave signal appears at O1. However, if the coupling fault C exists between
the line X and the line Y, a pulse train will be induced at line Y. The induced pulse train will
be propagated to output O3 and detected under the applied pattern. The coupling fault C is
thus detected.
3.2.2 Test Architecture in Boundary Scan Environment
Figure 3-1 shows the architecture of the test scheme in the boundary scan environment.
The input cells store a random pattern, which is generated randomly by an LFSR which is
transformed from boundary scan cells. When testing is started, the first bit of the input scan
cells is flipped in polarity and all the outputs of the circuit are checked to see if there are any
polarity changes on them. If there are any output changes, say on outputs Ok’s, this indicates
that there are sensitized paths existing between the outputs Ok’s and the input. Then, an
oscillation squarewave signal S is applied to the input. At this time if any pulse trains are
detected at any outputs other than Ok’s, there exist coupling faults between the sensitized
paths and victim lines and the coupling faults are detected by this pattern. When the above
testing is finished, the above procedure is repeated again to the second bit of the inputs.
Additional coupling faults will be caught if they do exist. And this procedure is repeated for
all inputs until to the last bit. At this moment, another new random pattern is generated and
stored in the input cells and another run of the above testing procedure is done again. When p
random patterns are applied, m x p testings are applied, where m is the number of the inputs.
Hence, it can be expected that the detection efficiency of patterns should be very high and this
is verified by the experiment results of the later section.
In the above, the oscillation square wave signal can be provided by an oscillator, which
can be either built in locally or provided by the SOC chip in which the CUT is embedded.
CUT S 1
1 0 1
Figure 3-1. The architecture of the squarewave test scheme for crosstalk faults in the boundary scan environment. For one random test pattern applied to the inputs of the circuit, the excitation signal S is scanned from the first bit to the last bit of the inputs.
3.3 Detail BIST Circuits
The general description about the test scheme is first described in the following
subsection 3.3.1. In this subsection, the timing diagram of control signals and oscillation
squarewave signal S are shown to explain how the test scheme operates.
3.3.1 General Description of the Circuits
Figure 3-2 shows the more detail circuit for the BIST test architecture of the previous
section. The circuit contains a random pattern generator block and a detector block, which
are located at the input and output of the CUT, which has m inputs and n outputs, respectively.
The random pattern generator block contains an m-bit LFSR, where clock TCK0 is the signal
which controls the LFSR to change its state and Sq is the oscillation squarewave, which as
mentioned previously could be built-in locally or provided externally by other circuits in the
SOC. The shift register is to shift a single logic 1 value from its lowest bit to its highest bit.
The outputs of shift register are connected to an m-bit 2-to-1 multiplexer, of which the outputs
could be from the LFSR or from Sq. The detector block contains two D-type flip-flops, which
are output boundary cells of the CUT and are to store the test results of the output, two
Exclusive-OR gates (Xor1 and Xor2), a detection mode latch (DM), which is enabled by the
signal DMLE to latch the output of Xor1, and an error detector (ED), which is to detect risky
pulses of the output signal.
As described previously, for the circuit, there are three operation phases, i.e. the random
test pattern generation phase, the oscillation signal port selection and stable logic latch phase,
and the oscillation test phase. In the first phase, one pulse arrives at TCK0, and LFSR
changes its state to apply a random pattern to the CUT. Shift register (SR) begins to load first
logic 1 from its LSB, and the multiplexor selects its LSB to be Sq. In the second phase, it is to
identify the sensitized path and Sq applies “0” and “1” in sequence to the CUT. The output
result of the first “0” is stored in DFF1, which is a positive-edge-triggered flip flop, and the
output result of the second “1” stays at the output of the CUT. Xor1 compares these two bits
and its output is latched at DM, which is enabled by the signal DMLE at the beginning of this
phase. If DM is “1”, it means the output of the CUT is a sensitized path. In the third phase,
which is the oscillation test phase, Sq is applied an oscillation square wave signal at the rising
edge of test clock to test the circuit. The capture clock, update clock and detection clock
(Detck) of boundary scan cells are synchronized with the test clock (see Figure 3-3 of timing
diagrams of all the signals). The circuit operates at the normal speed, and its output data are
shifted into DFF1 and DFF2. Xor1 compares the outputs of DFF1 and DFF2. If DM = 0,
which means the output is not a sensitized output, but the error detector detects a “1”, an
unexpected pulse induced by a crosstalk fault is detected.
In the above, it can detect the glitches which propagate to DFF1 when DFF1 is activated
at the rising edge of Capcko. This is the case that the crosstalk-induced glitches affect the
circuit operation in the normal mode. The glitches which arrive before or after the triggering
edge of Capcko are not considered since they do not affect the circuit operation.
m bits 2 to1 Multiplexor
Figure 3-2. The detail circuit of the BIST architecture for the crosstalk fault detection scheme.
TCK
Figure 3-3. The timing diagrams of the BIST circuit. The procedure is in three phases, i.e., the test pattern generation phase, the oscillation signal port selection and stable logic latch phase, and the oscillation test phase, for one pattern.
Figure 3-3 shows timing diagrams of all the signals of the circuit for the test procedure,
where TCK is the test clock which may be the system clock of the CUT, and EDR, Capcko,
and Updatecko, are the error detector reset signal, the capture register, the update register
signals of the boundary scan cell.
It is to be mentioned that, the scheme is to detect crosstalk induced glitch faults of a
combinational block. To apply it to a sequential circuit, similar to the case of stuck-at fault
testing, the sequential circuit needs to be scan-designed and only the combinational part is to
be tested.
3.4 The Boundary Scan Cell Design
Since in the above circuit, the input and output sub-circuits are transformed from the
boundary scan cells, the original designs of the scan cells need to be modified.
3.4.1 Boundary Scan-in Cell
The boundary scan-in cells of this scheme should be able to implement the function of
LFSR in addition to their original shifting function. Figure 3-4 shows the modified 4-bit
boundary scan-in cell design, where the boundary scan cells are conventional boundary scan
cells with a 3-to-1 multiplexor added to each cell, and Cap and Update are capture registers
and update registers respectively. When transformed into the LFSR mode, it has a seed of the
primitive polynomial 1 + x + x4. As described above, in the first phase, TCK0 =1 and the cells
are in the LFSR state, where LFSR/shift_mode and scan_in/reload are set to “1”. The
capture clock Capcki (= TCK0) at this moment starts to clock capture registers until the
capture register’ outputs (i.e., the random pattern) are finally stored into update registers when
the update clock Updcki arrives. In the second phase, the capture registers become shift
registers with LFSR/shift_mode set to “0” and boundary_scan_in is set to “0”. Also,
Coupling_test_mode and test_mode are set to “1” in this phase. The 3-to-1 MUX will select Sq as its input when the corresponding Cap’s output is “1”. The truth tables for the 2-to-1
MUX and the 3-to-1 MUX are also shown in Figure 3-4.When scan_in/reload is set to “1”
and LFSR/shift_mode is set to “0”, the modified boundary scan-in cells still support the
original boundary scan-in function.
test_mode, Cap coupling_test_mode
0xx From PIN
10x Update
0 3 to 1 MUX 110 Update
1 previous Cap 111 Sq
3 to 1 MUX scan_in/reload 2 to 1 MUX
(b)
Figure 3-4. (a) The modified 4-bit boundary scan-in cells and (b) truth tables for the 2-to-1 MUX and 3-to-1 MUX.
When scan_in/reload is set to “1” and LFSR/shift_mode is set to “0”, the modified
boundary scan-in cells still support the original boundary scan-in function.
3.4.2 Boundary Scan-out Cell
Figure 3-5 shows the detail design of the boundary scan-out cell for the detector block.
In the figure, EDR is detector clock and error detector reset. The error detector is reset to “0”
by EDR which was set to “1” in the first phase of the circuit operation. As described
previously, in the second phase, DMLE was set to “1”, Sq is applied a sequence of “1” and
“0” alternatively to determine the sensitized output, and a pulse arrives at Capcko to capture
the first “1” output to be compared with the second “0” output which appears at line A by
Xor1. Finally, DMLE returns to “0”. In the third phase, Capcko, update clock of boundary
scan out cell (Updcko), and Detck are clocked synchronously with the test clock. The outputs
are latched at the Cap and Update registers in the normal operation speed in this phase. Two
consequent outputs are compared by Xor1 which gives a “1” if these two outputs differ from
each other. The detection_mode latch, DM, which is controlled by DMLE, is shown in Figure
3-6. The error detector circuit is shown in Figure 3-7, which samples its input F when Detck
Figure 3-5. The modified boundary scan-out cell.
DMLE
Figure 3-7. The error detector circuit. Line F is sampled when Detck is “0”.
3.5 Fault Coverage Estimation through Fault Simulation
For this test scheme, to evaluate the fault coverage of the randomly generated patterns,
fault simulation needs to be done.
3.5.1 Symbol Definition and Operation
To perform fault simulation, a set of symbols are first introduced and defined and a set of
operation rules on them are defined for each type of gates. The set of symbols are shown in
Figure 2-2, where C, and C* are fault effect signals which are to be propagated and detected at
the output, PF and PF* are potential fault effects which could be 1 or C and 0 or C*
respectively, S and S* are oscillation squarewave signals which are to be applied at the fault
site, and x represents for an “unknown” value. Figure 2-2(b) shows examples on how these
symbols are operated through an & (AND) gate. For examples, C & C* results in PF* and C
& C results in C. Figure 2-2(c) shows the truth tables for AND and OR operation respectively.
In the table, it can be seen that these sets of operations are rather conservative. For examples,
when S operates on S (or S*), an x is given, which indicates an “unknown”, while for
practical cases, most often an S (or S*) is obtained.
3.5.2 Fault Simulation
For fault simulation, when a test pattern is applied to the circuit, a fault free logic is
firstly computed with the set of variables and operation rules defined above. Then a fault is
injected to see if the aggressor line is at the S (oscillation) path. If the aggressor line is at the
oscillation path, the victim line of the fault site is set to C, and it is propagated toward the
output of the circuit. If the propagation is successful, the crosstalk fault is detected by the
pattern and another fault is injected. The above process is repeated until all faults are injected
and another pattern is simulated.
3.6 Experimental Results
Firstly, the circuit level simulation for the proposed detection circuit was done. Figure
3-8 shows the simulation results of the modified boundary scan-out cell of Figure 3-5 under
the patterns of Figure 3-3. In the figure, the clock signal TCK, the squarewave test signal Sq,
the control signals DMLE and Detck for DM and ED respectively are displayed with the
simulated signals at FC (the input of the cell where the induced glitches comes in), F (the
output from XOR2), and Out (the output of the detector of the boundary cell). When DMLE
is “high”, i.e., the circuit is at the stable logic latch phase, for which Detck is at “high”, even
there is an induced glitch at FC (at 3.3 ns) the DM does not detect the glitch and the output of
the boundary cell, Out is “low”. When DMLE is “low” (the oscillation test phase), if the
glitch occurs at the time slot when Detck is “low” (at 7 ns), it is detected by the circuit and
Out is “high”.
TCK
S
DMLE
Detck
FC
Out F
Phase 1 2 3 2
Figure 3-8. Hspice simulation waveforms of modified boundary scan-out cell in Figure 3-5.
To estimate the efficiency of random test patterns to detect crosstalk faults, we did
experiments on randomly generating patterns to apply to benchmark circuits [22] for which
crosstalk faults are randomly injected to be detected by the patterns. A fault simulator based
on the symbols and operation rules in the previous section was implemented to evaluate the
fault coverage of the patterns. In the experiment, for each circuit, two different
non-overlapped separate sets of random crosstalk faults were generated, and the number of
faults is twice the number of gates. For each fault set, two separate sets, each with different
seed for pattern generation, of random patterns were generated. Figure 3-9 shows results for
some benchmark circuits (C2670, C5315, C6288, S13207c, S15830c, and S35932c, where c
represents for the combinational part of the circuit) where fault coverage curves are plotted
with respect to the number of patterns/fault. In the figure, S1 and S2 represent for two
different fault sets and RP1 and RP2 represent for two different sets of random patterns. It can
be seen that, similar to the stuck-at fault random testing, the fault coverage increases fast
C5315, 4970 faults
0 0.002 0.004 0.006 0.008 0.01
patterns / fault
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 patterns / fault
S1RP1 S1RP2 S2RP1 S2RP2
Figure 3-9. The fault coverages versus the number of patterns/number of faults for circuits C5315, C6288, S13207c, S15830c, S35932c, and S38584 respectively.
initially for some initial number of patterns and when it reach a “saturated” number it then
increases slowly afterward. The saturated fault coverage depends strongly on the type of the
circuit.
For examples, for circuits: C5315, S13207c, S15830c, and S35932c, which mainly are
circuits of larger sizes, it can easily reach 90%, but for circuit C6288, which is a multiplier, it
can only reach 30%. Also, since the faults were randomly selected, some of them may be
untestable faults. The fault coverage also depends somewhat on the set of random test patterns
which are generated with different seeds of LFSRs. However, the difference of the fault
coverage between two sets of patterns is generally small, which is within 2%. This means that
for an arbitrary set of random patterns, it can detect crosstalk fault quite efficiently. This
makes this BIST scheme very attractive in the practical application.
Table 3-1 compiles more detail simulation results of some benchmark circuits, in
Table 3-1 compiles more detail simulation results of some benchmark circuits, in