Chapter 1 Introduction
1.3 Outline of Dissertation
In Chapter 2, a random test pattern generator and deterministic test pattern generator are
developed and described to detect the crosstalk effect caused by coupling capacitors. The
deterministic test pattern generator is based on the oscillation ring test scheme [69-70]. Unlike
[69], where one of the CUT’s outputs is connected one of its output for generating oscillation
signals, the oscillating signal here is directly applied at one of the CUT’s inputs. If there is
any aggressor line located at the oscillation path, there will induce a crosstalk fault effect. It is
to activate the fault and propagate the fault effect to the output.
In chapter 3, the application of the oscillation ring test scheme is extended to the
boundary scan environment, and a BIST scheme is proposed to detect crosstalk faults in cores.
With modifying the boundary scan registers and the test patterns are applied by the LFSR, the
test scheme can operate self test mechanism. Some simulations for the test scheme are made,
and the simulation results show that the fault coverage are up to 90% for most of benchmark
circuits. The self test scheme will reduce the memory requirement on the ATE for testing the
crosstalk fault.
In chapter 4, the crosstalk faults between interconnects were studied and a test scheme
based on the path delay inertia principle is proposed. In the test scheme, a pulse is applied at
the input of interconnection line. If there is a coupling capacitor which exceeds the limit of
specification, the pulse will not propagate to the output.
Finally, in chapter 5 conclusions are made for the dissertation.
Chapter 2
A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal
2.1 Preliminary
In 1996, an oscillation test methodology was first proposed to test the analog circuit and
mixed-signal IC [71-72]. Under the test mode, the CUT is converted to be an oscillation
circuit. If there is any fault (including the catastrophic or the soft fault) in the CUT, the
observed oscillation frequency will deviate from the normal oscillation frequency. The test
scheme is easy for the test engineer by only observing the oscillation frequency of the CUT
without applying any test vector. In 1997, the oscillation test methodology was first applied
on the digital circuits [69], which was called oscillation ring test. The test scheme firstly
found the sensitized paths. When the circuit under the test mode, the output of one of
sensitized path is connected to its input either directly or with inserting an inverter by
considering the polarity of input and output are same or opposite respectively. The test
scheme could detect all stuck faults on the oscillating path, and some faults on side inputs.
In this work, a test scheme which is based on an oscillation square wave signal is
proposed. In the scheme, the oscillation signal is applied on the aggressor line and the
induced pulses at the victim line are detected if a crosstalk fault between these two lines exists.
The scheme eliminates the need to consider the timing issue of faults, since as long as the
induced pulses, which are induced by the crosstalk fault and usually induced unexpectedly,
exist, they will be detected at the output of the victim line. This makes test generation for
faults very simple with no need to consider timing of fault occurrence. Test generation and
fault simulation for crosstalk faults based on the scheme are described and experimental
results are presented.
2.2 The Testing Scheme Based on the Oscillation Test Signal
Figure 2-1 (a) is an example circuit with which the idea of the proposed testing scheme is
demonstrated, where a crosstalk fault exists between aggressor line X and victim line Y. A test
pattern, which includes an oscillating square signal, is applied to inputs of the circuit and the
oscillation signal is propagated to the aggressor line X. Due to the crosstalk fault, a series of
induced pulses will appear at the victim line. When the induced pulses are propagated to the
output under the applied pattern and detected, the crosstalk fault is detected. Once the fault is
detected, another pattern is applied to the circuit to test another coupling fault. The timing
diagram of the pattern is shown in Figure 2-2(b), where another pattern is also included for
demonstration. As it is easily seen that, in order to observe a clean pulse train at the output of
the victim line, patterns applied to inputs of the circuit should be a “hazard-free” patterns. The
patterns are very similar to those which are used to detect the path delay fault of the circuit
[73].
Figure 2-1. (a) A circuit example to demonstrate the test scheme for crosstalk fault detection; (b) The timing diagram of the applied patterns.
2.3 Test Generation and Fault Simulation
As it was mentioned above, the test patterns for this test scheme should be the
“hazard-free” pattern. In order to generate the test patterns, a set of symbols are first
introduced and a set of operation rules are defined for each type of gates to guarantee
“hazard-free”. The set of symbols are shown in Figure 2-2(a), where C, and C* are fault effect
signals which are to be propagated and detected at the output, PF and PF* are potential fault
effects which could be 1 or C and 0 or C* respectively, S and S* are oscillation signals which
are to be applied at the fault site, and x represents for an “unknown” value. Figure 2-2(b)
shows examples on how these symbols are operated through an & (AND) gate. For examples,
C* & C* or C & C* results in PF* and C & C results in C. Figure 2-2(c) shows the truth tables
for AND and OR operation respectively. In the table, it can be seen that these sets of
operations are rather conservative. For examples, when S operates on S (or S*), an x is given,
which indicates an “unknown”, while for practical cases, most often an S (or S*) is obtained.
0 : static 0
S*, S : oscillation signals x : Unknown value
AND-gate
Figure 2-2. (a) The symbol table for test generation and fault simulation for crosstalk faults; (b) examples of symbol operation through an AND gate; (c) truth table for the AND and OR operations.
With the set of variables and operation rules defined above, the conventional stuck-at
fault test generation is used to generate test patterns. The patterns generated will be ones
which do not create re-convergent sensitized path. However, also due to the stringent
conditions imposed above, patterns are sometimes very difficult to be generated and the test
generation is time consumed. And very often, undetected or aborted faults are resulted during
the test generation process.
For the reason stated above, to generate patterns for this test scheme, a random test
generation is first adopted and the generated patterns are crosstalk fault simulated to
determine the fault coverage. After the fault coverage has reached a certain value, the
remaining undetected faults are then applied a deterministic test generation procedure to
generate remaining test patterns. This reduces the test generation time and increases the test
generation efficiency. In the following, the two approaches to generate test patterns to
crosstalk faults are described:
2.3.1 Random Test Pattern Generation
For this approach of test generation, no specific fault is targeted and random patterns are
generated and fault simulated to find detected faults (out of a fault list). However, as
experimental results show that this approach is generally inefficient, i.e., the generated
patterns detect only a few patterns, resulting much wasted fault simulation time, a guided
random pattern generation method is used.
For the guided random pattern generation, the circuit is firstly processed with the input
cone of the aggressor line of each fault identified (shown in Figure 2-3). At first, a random
pattern is generated and applied to the circuit with one of inputs of the input cone applied with
signal S. The pattern is then fault simulated to see if S is propagated to the faulty site and a
faulty effect C is induced and propagated to any of outputs. If it fails, S is applied to the next
input of the input cone and another fault simulation is done. With all the inputs of the input
cone scanned by S, if the pattern still does not detect any fault, another random pattern is
generated and the above process is repeated to see if the generated pattern is a test. Due to the
fact that S is guidedly applied to the input cone of the aggressor line, the chance to achieve a
successful pattern is much enhanced.
Figure 2-4 shows an example that a pattern is simulated and a fault (f1) is detected by the
pattern and another fault (f2) is potentially detected. For this random test generation process,
as no “justification” step is involved, it is usually very fast as compared to the approach of the
deterministic test generation which is to be explained in the later section.
a
sweeping space 10110…1011100101.
Figure 2-3. The example to show the input cones of aggressor lines A1 and A2, where V1 and V2 are victim lines of crosstalk faults f1 and f2 respectively. be potentially detected at G.
2.3.2 Deterministic Test Pattern Generation
For this approach of test generation, a specific fault is targeted. The test generation
process is similar to that of the conventional stuck-at fault test generation except that, as
mentioned previously, the sensitized path of the fault activation does not intersect with that of
the fault propagation.
Figure 2-5 shows the flow chart of the test generation procedure. In the procedure, a cost
function and observability [74] for C for all faults are computed respectively to aid the later
test generation. Then a target fault is selected to be generated the test pattern. For the selected
targeted fault, another similar computation for the cost function and observability [74] for the
activation line S is done. Then a fault analysis step is performed to avoid the intersection of
the potential sensitized activation path and the potential sensitized propagation path during the
later justification. An example circuit is shown in Figure 2-6 to explain the above step. In the
figure, Y is the victim line which is at value C which has three paths to be propagated to the
outputs of the circuit. Line X is the aggressor line which is assigned value S. Both C and S
need to be justified later. Through the fault analysis, for line X, its input lines are assigned NC
and N1, which mean that they can not be signal C and 1 respectively since the output of the
OR gate is S signal. Similarly, the output line of gate X can not be C, 1, or 0, so NC, N1, and
N0 are assigned. All these values are then propagated backwardly and forwardly respectively
Yes Select one fault in fault list
& injection of one fault.
Fault Analysis
Figure 2-5. Flow chart of the deterministic test pattern generation
0
Figure 2-6. An example circuit to demonstrate the fault analysis step, where X is the aggressor line which is at S and Y is the victim line which is at C.
to find the feasible sensitized paths. During propagating these values, the cost functions and
observabilities computed previously for C and S will be used as reference to determine the
propagation path. After this step justification of paths are done, which are in two phases. In
phase 1, the justification for fault propagation is done and in phase 2, the justification for the
fault activation is done. Once the pattern is found, it is fault simulated to see if it can detect
other faults.
Figure 2-7. Flow chart of the fault simulation
For the fault simulation, when a test pattern is applied to the circuit, a fault free logic is
firstly computed with the set of variables and operation rules defined above. Then a fault is
injected to see if the aggressor line is at the S (oscillation) path. If the aggressor line is at the
oscillation path, the victim line of the fault site is set to C, and it is propagated toward the
output of the circuit. If the propagation is successful, the crosstalk fault is detected by the
pattern and another fault is injected. The above process is repeated until all faults are injected
and another pattern is simulated. The flow chart of the fault simulation is shown in Figure 2-7.
2.4 Experimental Results
The above two approaches were applied to benchmark circuits [75] to generate test
patterns for crosstalk faults. Both of them were implemented in C language and run on SUN
Ultra60. Table 2-1 shows results for the random test pattern generation approach where both
the results of the conventional random pattern generation approach and the guided random
pattern generation approach are listed. In the experiment, since crosstalk faults are dependent
on the circuit layout, which was not available, 100 crosstalk faults, some of them might be
undetectable, were randomly assumed and injected and 100 patterns were randomly generated.
In the table, for each circuit, the number of inputs is listed, where PD is the potential detected
faults, FC (fault coverage) includes the PD faults, and TG is the total test generation time
which mainly is the fault simulation time. From the table, it is seen that for this random test
generation approach, fairly high FC, over 85% in average, can be obtained, especially for
larger size circuits such as s13207c ~ s38584c. The test generation time in general is
acceptable and the guided approach has less test generation time than does the conventional
approach, especially for larger circuits which have large number of inputs.
Table 2-2 shows the results of the deterministic test generation. In the table, the faults
injected were the same as those of Table 1, and UD represents for identified undetectable
Table 2-1. Test generation results of both the conventional and guided s3271c 142 0 96 0.33 0.17 s3330c 172 0 59 0.45 0.26 s3384c 209 0 90 0.49 0.13 s4863c 153 0 91 0.83 0.52 s5378c 214 0 89 0.55 0.22 s6669c 312 0 98 1.44 0.19 s9234c 247 1 77 0.88 0.50 s13207c 650 2 86 2.82 0.43 s15850c 600 0 89 2.81 0.62 s35932c 1763 0 94 19.49 1.59 s38584c 1462 0 92 13.19 1.19
F.C.
(%)
TG time(sec) Circuits No. of
PI PD
Table 2-2. Test generation results of deterministic test pattern generation approach
Circuits UD Abort F.C.
c6288 26 47 27 53% 516.48
c7552 7 1 92 99% 4.46
faults and Abort represents for faults aborted when their test generation time exceeded for a
certain limit (10 seconds for c6288 and 1 second for all other circuits). It is seen that for most
of circuits, the test efficiency are 100%, i.e., UD faults can be identified and all faults can be
generated test patterns. The test generation time for each circuit is usually longer than that of
the guided random test generation approach but the fault coverage obtained is generally
somewhat higher than that of Table 1.
Table 2-3. Test generation results of the guided random pattern generation approach (*) combined with the deterministic test pattern generation approach (**).
* ** * ** * **
Table 2-3 shows the results that at first the guided random test pattern generation
approach was applied with 100 generated patterns and then the deterministic test pattern
generation method was applied again to generate more test patterns to test the remaining
faults. In the table, Total Pattern means the total number of patterns generated which include
the guided random patterns approach and the deterministic patterns. It can be seen that further
improvement can be obtained by combining these two approaches to generate test patterns for
crosstalk faults. The total test generation time is acceptable for all circuits except for c6288,
which is a multiplier circuit with many XOR gates.
2.5 Summary
In this chapter, we propose a test scheme to test crosstalk faults. It uses an oscillation
signal applied on an aggressor line and detects induced pulses on a victim line if a crosstalk
fault exists between these two lines. It is simple and eliminates the complicated timing issue
during test generation for the crosstalk fault. The scheme is very simple and easy to be
implemented. Two test generation approaches, i.e., the guided random test generation and the
deterministic test generation are described and experimental results are presented. The
experimental results show that the proposed test generation approach, i.e., it first uses the
guided random test generation then a deterministic approach can effectively generate crosstalk
fault test patterns for circuits.
Chapter 3
A BIST Scheme for Detecting Crosstalk Faults Using Squarewave Test Signal in Boundary Scan Environment
3.1 Preliminary
The basic difficulty on testing crosstalk faults is that they are pattern-dependent and are
highly unpredictable in nature. To generate test patterns to deterministically detect them, a
timing analysis program of high precision needs to be employed, and this takes much
computation time. In chapter 2, a test scheme which is based on an oscillation signal was
proposed. In the scheme, the oscillation test signal is applied on the aggressor line and the
induced glitches at the victim line are detected if a crosstalk fault between these two lines
exists. The scheme eliminates the need to consider the timing issue of faults, since as long as
the induced glitches, which are induced by the crosstalk fault and usually are induced
unexpectedly, exist, they will be detected at the output of the victim line. A guided random
test pattern generation was also proposed in subsection 2.3.1 of chapter 2, and the test scheme
was shown in Figure 2-3. It is very suitable to apply the test scheme to be BIST, because the
random pattern can be generated by LFSR. The simulation result for the test scheme was list
in table 2-3. It showed that the test scheme had high fault coverage for most benchmark
circuits except the C6288.
In this chapter, the test scheme is modified to be applied to test this type of crosstalk fault
of the unexpected glitches of embedded circuits in the boundary scan environment of a VLSI.
The scheme tests crosstalk faults with the squarewave test signal under applied random
patterns which are generated by the LFSR which is trans-configured by boundary scan cells of
the embedded circuit. The scheme is very simple in test generation and test application with
no need to consider the timing issue of fault occurrence. Experimental results show that
considerable high (> 90%) fault coverage can easily be obtained for detecting the induced
glitch type of crosstalk fault for large size benchmark circuits [75]. In the following sections,
the test scheme is described in section 3.2, and the detail BIST circuit is shown in section 3.3.
The boundary scan circuits, including boundary scan-in cells and boundary scan-out cells,
should be modified for implementing the test scheme. The modified boundary scan cells and
the detection circuit are described in section 3.4. In section 3.5, the experimental results which
are simulated by C program are shown to manifest the practicability of the test scheme.
3.2 The Test Scheme
The basic idea, which is similar to the idea shown in chapter 2, behind the test scheme is
described in subsection 3.2.1. In subsection 3.2.1, the test scheme architecture which is based
on the boundary scan environment.
3.2.1 Basic Idea
Figure 2-1 is a circuit example which demonstrates the basic idea of the detection of
crosstalk faults by using the oscillation squarewave signal. In the figure, A, B, C, D and E are
inputs, O1, O2 and O3 are outputs, line X is the aggressor line, line Y is the victim line, and the
coupling capacitor C represents a coupling fault between lines X and Y. A random test pattern,
{1, S, 1, 0, 0}, where S stands for an oscillation square wave signal, is applied to the input and
the output will be {O1, O2, O3 = S, 0, 1} if the circuit is fault free, where O1 = S means that an
oscillation squarewave signal appears at O1. However, if the coupling fault C exists between
the line X and the line Y, a pulse train will be induced at line Y. The induced pulse train will
be propagated to output O3 and detected under the applied pattern. The coupling fault C is
thus detected.
3.2.2 Test Architecture in Boundary Scan Environment
Figure 3-1 shows the architecture of the test scheme in the boundary scan environment.
The input cells store a random pattern, which is generated randomly by an LFSR which is
transformed from boundary scan cells. When testing is started, the first bit of the input scan
transformed from boundary scan cells. When testing is started, the first bit of the input scan