Chapter 1 Introduction
2.2 Device Fabrication
Fig. 2-1 shows the process flow of the D-SAGRSD TFT structure. First, a 300-nm α-Si layer for active region was deposited by low pressure chemical vapor deposition (LPCVD) system using SiH4 at 550°C on 500-nm thermal oxidized silicon wafers. After patterning, the active region was formed using reactive ion etching (RIE) at this mask step. Then, the first (650-nm) plasma enhanced chemical vapor deposition (PECVD) tetraethoxysilane (TEOS) oxide layer was deposited at 350 °C.
Chemical-mechanical polishing (CMP) process was employed to planarize the first TEOS oxide surface, as shown in Fig. 2-1(a). The thickness of the first TEOS oxide above the active region after polishing is about 300-nm. After patterning, the RIE process was used to etch the α-Si layer and then selective BOE etching was used to form a T-sharp gutter, as shown in Fig. 2-1(b). Because the α-Si layer had no stopper layer, the α-Si thin channel region thickness was controlled by etching rate (8.33 Å/sec). Additionally, the α-Si film thickness was determined by Ellipsometer, and the thickness of the thin channel region was accurately controlled, with an error of within ±3% (50 ± 1.5 nm). After etching, the thickness of the active region became 50-nm. After the photoresist was removed, the α-Si film was annealed in nitrogen ambient at 600°C for 24 h to become the poly-Si film. After recrystallization, the etching damages of the channel surface were recovered and the surface roughness is approximately 3 nm. A 50-nm plasma enhanced chemical vapor deposition (PECVD) TEOS gate oxide layer was deposited at 350 °C, and then a 300-nm LPCVD Poly-Si film was deposited. After CMP process was employed to planarize the Poly-Si film surface to form the T-sharp gate as shown in Fig. 2-1(c), the 50-nm TEOS gate oxide and the first TEOS oxide were removed by BOE solution. Then, Gate, Source and Drain regions were formed by ion implantation
of Phosphorous(Dose = 5 x 1015 cm-2 at 50 keV) and then activated in nitrogen ambient at 600 °C for 24 h, as shown in Fig. 2-1(d). After the source, drain and gate activation, the second (500-nm) passivation TEOS oxide was deposited by PECVD. Contact holes were opened using wet etching of the passivation oxide layer. A layer of aluminum was then deposited by thermal coater system with
a thickness of 600 nm. After metal patterning, a forming gas anneal is performed at 400°C for 30 min. The total masks of our fabrication processes are four masks, which are less than those of conventional processes in a RSD poly-Si TFT [2.8],[2.9]. For comparison, the conventional co-planar poly-Si TFTs with 50-nm channel thickness were also fabricated in the same run. The total channel length of the proposed TFT is shown in Fig. 2-2.
2.3 RESULTS AND DISCUSSION
The Ids-Vgs transfer characteristics of the proposed D-SAGRSD TFT structure compared with the conventional co-planar TFT were shown in Fig. 2-3. It can be observed that, even though the D-SAGRSD TFT has a slightly lower ON-state current and a slightly higher minimum
OFF-state current, much lower OFF-state leakage current (Vgs = -10 V and Vds = 5 V) can be also obtained. The proposed TFT has two symmetrical thick channel regions near source and drain sides.
These thick channel regions have much more grain boundary traps than the thin channel region, and these grain boundary traps would cause the ON-state current decreasing and minimum OFF-state current increasing. Besides, as shown in Fig. 2-4(a), the current flow lines of the conventional co-planar TFT in the ON-state are uniform distribution in the inversion layer near the oxide/channel interface. However, for the proposed D-SARSD TFT, even most of the carriers can transport in the inversion layer near the oxide/ Poly-Si interface, some carriers still can directly transport to the
drain region in the thick channel region, as shown in Fig. 2-4(b). This phenomenon may be due to the variation of the lateral electric field in the thick channel region near the drain side. Figs. 2-5 and 2-6 show the simulation positions of the lateral electric field of the conventional co-planar TFT and the proposed D-SAGRSD TFT simulated by MEDICI, respectively. The simulation results of the conventional co-planar TFT and the proposed D-SAGRSD TFT are shown in Table 2-1. It can be observed that the maximum lateral electric field of the proposed D-SAGRSD TFT in the point C of Fig. 2-6 is remarkable larger than that of the conventional co-planar TFT in ON-state. Therefore, we can conclude that, for the proposed D-SAGRSD TFT, carriers in the thick channel region can transport to the drain region via the inversion layer near the oxide/ Poly-Si interface, and directly transport to the drain region due to high lateral electric field near the drain side. Moreover, the proposed TFT would have a higher threshold voltage and a larger sub-threshold swing than those of the conventional TFT due to bad channel control in the corners of the channel and bad oxide/Poly-Si interface of the vertical channel region.
For the OFF-state current measured at higher drain and reverse gate bias (Vds = 5 V, Vgs = -10 V), the main reason of much lower OFF-state current of the proposed D-SAGRSD TFT is that the leakage current is determined by the electron-hole pair generation rate in the depletion region at the drain edge. The pair generation rate is strongly dependent on the number of trap-states in the forbidden gap, lateral electric field and a generation volume of the depletion region [2.10]-[2.12].
Although a thick drain region causes the generation volume of the D-SAGRSD TFT to increase, the
maximum lateral electric field near the drain region of the D-SAGRSD TFT, as shown in Fig. 2-7, is also largely dropped (see Table 2-2) due to thick source/drain regions [2.13]. At higher drain and
reverse gate bias (Vds = 5 V, Vgs = -15 V), the leakage current would be due to the thermionic field emission via grain boundary defects [2.14]. Even though the generation volume would be increased, the D-SAGRSD TFT, therefore, would have a lower OFF-state leakage current than that of the conventional TFT because the maximum lateral electric field near the drain region is notably
reduced. Fig. 2-8 shows the Ids - Vds curves of the proposed TFT compared with the conventional TFT. In the insert plots, it can be observed that the proposed TFT has a lower source/drain parasitic
resistance due to steeper slopes of Ids - Vds of the proposed TFT in the linear region. However, in the saturation region, the ON-state current of the proposed TFT is lower than that of the conventional TFT; it is because the maximum lateral electric field of the proposed TFT is also dropped due to thick source/drain regions (see Table 2-1).
2.4SUMMARY
In this chapter, a novel four mask steps n-channel self-aligned gate raised source/drain Poly-Si TFT formed by damascene process was proposed and investigated. Remarkable OFF-state current can be obtained and good ON/OFF current ratio can be maintained for the proposed D-SAGRSD TFT. The self-aligned gate and raised source/drain regions can be formed without the additional
mask step and therefore reduce the lateral electric field near the drain side to suppress the OFF-state current. This new TFT structure may be an attractive device structure for future high-performance large-area device applications.
References
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“Anomalous leakage current in LPCVD polysilicon MOSFET’s,” IEEE Trans. Electron
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[2.3] Jun-In Han and Chul-Hi Kan, “A self-aligned offset polysilicon thin-film transistor using photoresist reflow,” IEEE Electron Device Letters, vol. 20, pp. 476-477, Sept. 1999.
[2.4] Po-Sheng Shih, Chun-Yen Chang, Ting-Chang Chang, Tiao-Yuan Huang, Du-Zen Peng, and Ching-Fa Yeh, “A novel lightly doped drain polysilicon thin-film transistor with oxide sidewall spacer formed by one-step selective liquid phase deposition,” IEEE Electron
Device Letters, vol. 20, pp. 421-423, Aug. 1999.
[2.5] Tiao-Yuan Huang, I-Wei Wu, Alan G. Lewis, Anne Chiang, and Richard H. Bruce,
“Device sensitivity of field-plated high-voltage TFT’s and their application to low-voltage operation,” IEEE Electron Device Letters, vol. 11, pp. 541-543, Nov. 1990.
[2.6] Keiji Tanaka, Kenji Nakazawa, Shiro Suyama, and Kinya Kato, “Characteristics of field-induced-drain (FID) poly-Si TFT’s with high on/off current,” IEEE Trans. Electron
Devices, vol. ED-39, pp. 916-920, April 1992.
[2.7] Kwon-Young Choi, and Min-Koo Han, “A novel gate-overlapped LDD poly-Si thin film
transistor,” IEEE Electron Device Letters, vol. 17, pp. 566-568, Dec. 1996.
[2.8] Makoto Yoshimi, Minoru Takahashi, Tetsunori Wada, Kouichi Kato, Shigeru Kambayashi, Masato Kemmochi, and Kenji Natori, “Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 37, no. 9, pp.
2015-2021, Sept. 1990.
[2.9] Shengdong Zhang, Chunxiang Zhu, Johnny K. O. Sin, and Philip K. T. Mok, “A Novel Ultrathin Elevated Channel Low-temperature Poly-Si TFT,” IEEE Electron Device Letters, vol. 20, no. 11, pp. 569-571, Nov. 1999.
[2.10] O. K. B. Lui, M. J. Quinn, S. W-B. Tam, T. M. Brown, P. Migliorato and H. Ohshima,
“Investigation of the Low Field Leakage Current Mechanism in Polysilicon TFT’s,” IEEE
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[2.11] O. K. B. Lui and P. Migliorato, “A new generation recombination model for device simulation including the Poole-Frenkle effect and phonon-assisted tunneling,” Solid-State
Electronics, vol. 41, no. 4, pp. 575-583, 1997.
[2.12] S. D. Brotherton, J. R. Ayres and M. J. Trainor, “Control and analysis of leakage currents in poly-Si thin-film transistors,” J. Appl. Phys., vol. 79, issue 2, pp. 895-904, Jan. 1996.
[2.13] Anish. Kumar K.P., Johnny K. O. Sin, Cuong T. Nguyen, and Ping K. Ko, “Kink-Free Polycrystalline Silicon Double-Gate Elevated Channel Thin-Film Transistors,” IEEE
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[2.14] Chul Ha Kim, and Ki-Soo Sohn, “Temperature dependent leakage currents in polycrystalline silicon thin film transistors,” J. Appl. Phys., vol. 81, no. 12, pp. 8084-8090, June. 1997.
650 nm 300 nm
(a)
50 nm
300 nm 250 nm 300 nm
(b)
50 nm 50 nm
(c) (d)
Thermal Oxide
TEOS
Oxide α-Si Poly-Si P. R.
Doping Region
250 nm
300 nm
50 nm 50 nm 300 nm
Fig. 2-1 (a)-(d) Schematic cross sections of the major fabrication steps of the proposed n-channel D-SAGRSD TFT.
L lateral L vertical
L ch =L lateral +2L vertical
Fig. 2-2 Cross-section view of the proposed D-SAGRSD TFT structure.
-20 -10 0 10 20 30 40 10-14
10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5
10-4 Wch/Lch = 10/9.9 (µm/µm) No hydrogenation
Vds = 0.1 V
Dr ain Cu rr ent, ( A )
Gate Voltage,(V)
Conv. coplanar D-SAGRSD
Vds = 5 V
Fig. 2-3 Ids – Vgs transfer characteristics of the proposed D-SAGRSD TFT and the conventional co-planar TFT.
(a)
(b)
Fig. 2-4 Simulation current flow lines of (a) the conventional co-planar TFT; (b) the proposed D-SAGRSD TFT.
Gate
Drain
10 nmThermal
Oxide
TEOS
Oxide Metal Poly-Si
Doping Region
Fig. 2-5 Simulation position of the lateral electric field of the conventional co-planar TFT.
Drain Thermal
Oxide
TEOS
Oxide Metal Poly-Si
Doping Region
B:
130 nmA:
10 nmC:
10 nmGate
Fig. 2-6 Simulation positions of the lateral electric field of the proposed D-SAGRSD TFT.
Table 2-1 Maximum lateral electric field of the conventional and proposed TFT structures in the ON-state.
0.421
10.6 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4
Fig. 2-7 Simulated lateral electric field distribution of the proposed D-SAGRSD TFT and the conventional co-planar TFT in the OFF-state.
Table2-2 Maximum lateral electric field of the conventional and proposed TFT structures in the OFF-state.
0.338
0 5 10 15 20 25
Fig. 2-8 Ids – Vds output characteristics of the proposed D-SAGRSD TFT and the conventional co-planar TFT. The insert plots are the Ids – Vds output characteristics of the proposed D-SAGRSD TFT and the conventional co-planar TFT in the linear region.
Chapter 3
A Novel Four-Mask Step Low-Temperature Polysilicon Thin-Film Transistors with Self-Aligned Raised Source/Drain
(SARSD)
3.1. INTRODUCTION
Low-temperature polycrystalline silicon (LTPS) TFTs appear to be one of the most promising technologies for the ultimate goal of building large area electronic systems on glass substrate [3.1].
In flat panel liquid crystal, electroluminescent, and plasma displays, as well as other applications such as high-speed printers and page width optical scanners, poly-Si TFTs can be used to integrate peripheral driver circuits on glass for system integration [3.2]. In order to integrate peripheral driving circuits on the same glass substrate, both a large current drive and a high drain breakdown voltage are necessary for poly-Si TFT device characteristics. It has been previously reported that the use of a thinner active channel film is beneficial for obtaining a higher current drive [3.3],[3.4].The use of thin active channel layer, however, inevitably results in poor source/drain contact and large parasitic series resistance. An ideal TFT device structure, therefore, should consist of a thin active channel region, while maintaining a thick source/drain region. The thick source/drain region serves on not only to reduce the lateral electric field, thus maintaining the breakdown voltage [3.5],[3.6],
but to reduce the source/drain series resistance. Pervious methods used to fabricate such ideal structures with thin active channel and thick source/drain region, however, are not self-aligned in nature, and require additional masks [3.5],[3.6], when compared to the conventional co-planar TFTs.
In chapter 2, the D-SAGRSD TFT has been proposed. However, this structure has a slightly low ON-state drain current and a low ON/OFF current ratio, even the OFF-state leakage current can be suppressed. In this chapter, a novel TFT with self-aligned raised source/drain (SARSD) structure is proposed. The new device features a thin, wider active channel region and a thick source/drain region. This new device also has a higher ON-state drain current and a higher ON/OFF current ratio than those of the D-SAGRSD TFT. Moreover, the OFF-state leakage current of the SARSD TFT is as low as that of the D-SAGRSD TFT. The RSD regions of this new device are self-aligned and no additional mask is needed.
3.2. DEVICE FABRICATION
The fabrication processes of the novel n-channel poly-Si SARSD TFT were as follows: A 350-nm thick α-Si layer for active region was deposited by low pressure chemical vapor deposition (LPCVD) system using SiH4 at 550°C on 500-nm thermal oxidized silicon wafers. After patterning, the thin α-Si (50 nm) regions and the thick α-Si (350 nm) regions were formed using reactive ion
etching (RIE) at this mask step, as shown in Fig. 3-1(a). The widths of the thick α-Si (350 nm) regions were 5 µm. Then the deposited α-Si film was annealed in nitrogen ambient at 600°C for 24 h to become the poly-Si film. After recrystallization, the etching damages of the channel surface were recovered and the surface roughness is approximately 3 nm. A 50-nm plasma enhanced chemical vapor deposition (PECVD) gate oxide layer was deposited at 350 °C, and then a 300-nm
LPCVD poly-Si gate was deposited. After defined the undoped gate region (gate mask area = Lch x Wch, as shown in Fig. 3-2), the remnant 50-nm oxide film and 50-nm poly-Si film would be further removed using the RIE system to form an isolated active region, as shown in Figs. 3-1(b) and 3-1(c).
After the photoresist was removed, Gate, Source and Drain regions were formed by ion
implantation of Phosphorous (Dose = 5 x 1015 cm-2 at 50 keV) and then activated in nitrogen ambient at 600 °C for 24 h, as shown in Fig. 3-1(c). It is worth pointing out that the gate region
width (Wch) is larger than that of the source/drain region (Wsd). Therefore, a thin and wider active region would be formed below the whole of gate region, as shown in Fig. 3-2. After the source, drain and gate activation, the 500-nm passivation oxide was deposited by PECVD. Contact holes were opened using wet etching of the passivation oxide layer. A layer of aluminum was then deposited by thermal coater system with a thickness of 600 nm. After metal patterning, a forming gas anneal is performed at 400°C for 30 min. The total masks of our fabrication processes are four masks, which are less than those of conventional processes in a RSD poly-Si TFT [3.5],[3.6]. For comparison, the conventional co-planar poly-Si TFTs with 50-nm channel thickness were also
fabricated in the same run.
3.3RESULTS AND DISCUSSION
Fig. 3-3 shows SEM photograph of the proposed SARSD TFT structure. To ensure that current flow of the proposed SARSD structure would be as shown in Fig. 3-2, the 2-D numerical simulator MEDICI was used. Fig. 3-4 shows the simulated current flow lines of the conventional co-planar and proposed SARSD poly-Si TFT structures in ON-state. The channel length and width of the simulated conventional co-planar structure are 15 µm and 5 µm, respectively. From the simulation results in Fig. 3-4(a), the simulated current flow lines of the conventional structure are uniform distribution in the channel region and source/drain regions. However, for the proposed SARSD structure as shown in Fig. 3-4(b), the current flow paths are different from the conventional sample in ON-state. It is because that the channel width is wider than source/drain width, and wide channel width would obtain a high drain current. Therefore, it can be convinced that the proposed RSD structure would obtain a higher drain current than that of conventional co-planar one.
As shown in Fig. 3-5, the proposed SARSD TFT has a higher ON-state current (Vgs = 30V) and a lower OFF-state leakage current (Vgs = -15V) than those of the conventional TFT. In ON-state, the main reasons of high ON-state current are due to wide channel width (Wch = 33 µm) and small source/drain parasitic resistances [3.6]. On the contrary, in OFF-state, the minimum
OFF-state leakage current of the proposed SARSD TFT is only slightly larger than that of the conventional TFT. It is because that the leakage current is determined by the electron-hole pair generation rate in the depletion region at the drain edge. The pair generation rate is strongly dependent on the number of trap-states in the forbidden gap, lateral electric field and a generation volume of the depletion region [3.7]-[3.9]. Although a thick drain region causes the generation
volume of the SARSD TFT (must be approximately Wsd x thickness of the depletion region) to increase, the maximum lateral electric field near the drain region of the proposed SARSD TFT is largely dropped from 2.13 MV/cm to 1.57 MV/cm due to thick source/drain region [3.10]. At high
drain and reverse gate bias (Vds = 5 V, Vgs = -15 V), the leakage current would be due to the thermionic field emission via grain boundary defects [3.11]. Therefore, the proposed SARSD TFT has a lower OFF-state leakage current than that of the conventional TFT because the maximum lateral electric field near the drain region is largely dropped, even though the generation volume would be increased. As shown in Fig. 3-6, the proposed SARSD TFT has a higher saturation current and a lower parasitic resistance than those of the conventional one for different gate bias.
Fig. 3-7 shows the Ids - Vgs transfer characteristics of the proposed SARSD TFT with different channel width. Fig. 3-8 shows maximum ON-state current and minimum OFF-state leakage current of the proposed SARSD TFT with various the side channel width, and the conventional co-planar TFT. It is obvious that the ON-state current is increased with increasing the channel width. However, as shown in Fig. 3-8, the minimum OFF-state leakage current is also
increased with increasing the channel width. Fig. 3-9 shows the OFF-state leakage current of the proposed SARSD TFT with various the side channel width, and the conventional co-planar TFT
measured at Vgs = -15 V and Vds = 5 V. In Fig. 3-9, it is obvious that the OFF-state leakage current of the proposed SARSD TFT is significant lower than that of the conventional co-planar TFT for different channel width. Moreover, as shown in Fig. 3-10, the optimum condition of the
SARSD TFT for the case of Lch /Wsd = 15 µm/ 5 µm is Wsc = 2 µm.
3.4. SUMMARY
In this chapter, a novel four mask steps n-channel low-temperature poly-Si TFT with a self-aligned raised source/drain region and a thin channel was proposed and investigated. The gate mask was used to form a large area thin-channel region below the gate region, and the self-aligned raised source/drain region can be formed without the additional mask step. A lower off-sate leakage current and a higher ON/OFF current ratio can be obtained for the proposed SARSD TFT. The TFT
In this chapter, a novel four mask steps n-channel low-temperature poly-Si TFT with a self-aligned raised source/drain region and a thin channel was proposed and investigated. The gate mask was used to form a large area thin-channel region below the gate region, and the self-aligned raised source/drain region can be formed without the additional mask step. A lower off-sate leakage current and a higher ON/OFF current ratio can be obtained for the proposed SARSD TFT. The TFT