Thesis Organization

In this thesis, we concentrate our efforts on new TFT structure development, and discuss the effect of channel wide widening on a Poly-Si TFT which will occur when the channel width is larger than the source/drain width.

Chapter 1 describes the background and motivation. In chapter 2, we apply the damascene process to develop a novel TFT structure with a self-aligned gate and raised source/drain. 2-D simulation tool, MEDICI, is also used to verify that the electric field near the drain region will be reduced by using this novel TFT structure. In chapter 3, another new TFT structure is proposed. For this new structure, thick source/drain regions and a thin channel region could be achieved with only four mask steps, which are less than that in conventional raised SD TFT’s. Moreover, the channel width of the proposed structure would be larger than its source/drain width. Wide channel width will improve the ON-state current due to carrier will flow from the source to the drain via new current flow paths occurred in the side channel region. Therefore, in chapter 4, the effect of channel width widening on a Poly-Si TFT in the linear region are thus studied carefully.

Finally, in chapter 5, a conclusion is given for this thesis, and some future works about this thesis are proposed.

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Fig. 1-1 Ids – Vgs transfer characteristics of the conventional co-planar TFT with thicker (100nm) and thinner (30nm) channel thicknesses.

Fig. 1-2 Ids – Vds output characteristics of the conventional co-planar TFT with thicker (100nm) and thinner (30nm) channel thicknesses.

S

G

Thin channel

D

Thick channel Thick

channel

Thick Drain Thick Drain

Fig. 1-3 Proposed new RSD TFT structure.

Chapter 2

A Novel Low-Temperature Polysilicon Thin-Film Transistors with a Self-Aligned Gate and Raised Source/Drain Formed by

Damascene Process

2.1 INTRODUCTION

Low-temperature polycrystalline silicon (LTPS) TFT’s have been widely investigated for several years [2.1]. However, the undesired OFF-state leakage current for a poly-Si TFT is much higher than that of an amorphous TFT. It is well known that the OFF-state leakage current mechanism is the field emission via grain boundary traps due to high electric field in the drain depletion region [2.2]. Thus, suppressing the off-state leakage current by reducing the drain electric field is required. Several methods have been proposed to achieve this purpose, such as offset gated structure [2.3], lightly doped drain structure [2.4] and field induced drain structure [2.5], [2.6]. In the lightly doped offset drain structure, the On-state current is significantly suppressed at the same time [2.7]. In the field induced drain structure, an additional photo masking step is required and unavoidable photo masking misalignment error will occur [2.5], [2.6]. It also has been previously reported that the thick source/drain region not only serves to reduce the lateral electric field, thus maintaining the breakdown voltage [2.8],[2.9], but also to reduce the source/drain series resistance.

Pervious methods used to fabricate such structures with thin active channel and thick source/drain regions, however, are not self-aligned in nature, and require additional masks [2.8],[2.9], when compared to the conventional co-planar TFTs.

In this chapter, a novel four mask steps self-aligned gate RSD Poly-Si TFT structure formed by the damascene process (D-SAGRSD TFT) is proposed. The new device features a thin active channel region and a thick source/drain region. The Gate and RSD regions are self-aligned and no additional mask is needed. Moreover, we use the 2-D numerical simulator MEDICI for device analysis to study the variation of the lateral electric field influenced by device structure in both ON-state and OFF-state. For the sake of simplicity, the single crystalline silicon model already available in MEDICI is used to just estimate the electric field effects of these two Poly-Si TFT structures.