Device Level Improvement

4.2 Device Level Improvement

There have been several approaches to increase the SNM, such as the use of larger V_DD and increase the cell ratio or the V_th of transistors. Figure 4.4 shows the static transfer curve of 16-nm-gate planar SRAM with 350 mV V_th. The SNM is increased to 92 mV and the normalized SNM fluctuation induced by RDF and PVE are reduced to 41.7% and 18%, respectively. Since the SNM fluctuation is too large to ensure the accurate operation of the SRAM cell, to further suppress the RDF induced SNM fluctuation, vertical doping profile engineering, as shown in Fig. 4.5, has been implemented to reduce the RDF-induced fluc-tuations in planar SRAM cells with high V_th. 758 dopants are firstly randomly generated in a large rectangular solid (x, y, z : 16 nm × 2000 nm × 16 nm ), in which the equiva-lent doping concentration is 1.48 × 10¹⁸ cm⁻³, as shown in Fig. 4.5(a). The distribution of the generated dopants’ position in the direction of channel depth follows the normal distribution, as shown in Fig. 4.5(b). Both the mean position and the three sigma of this distribution are eight nanometers, which can be controlled by the manufacturing processes of ion implementation and thermal annealing. The inset of Fig. 4.5(b) shows the nominal case of the improved vertical doping profile, where the darker region indicates the higher doping concentration. The large rectangular solid is then partitioned into 125 sub cubes of 16 nm³ cube and mapped into device channel for discrete dopant simulation, as shown in Fig. 4.5(c). The number of dopants may vary from zero to 14, and the average number is

six, as shown in Fig. 4.5(d). The longitudinal dopant distribution of the improved and the original doping profile, are studied in Figs. 4.5(e) and 4.5(f), respectively. The inset of Fig.

4.5(f) shows the distribution of doping concentration for the original doping profile. The distribution of dopant number in channel depth is uniform. We notice that the threshold voltages of the nominal devices for both the improved and original doping profiles, whose channel doping profile is continuously doped with 1.48 × 10¹⁸ cm⁻³, are adjusted to be the same value 140 mV. Result shows that numbers of dopant appearing near the channel surface for the improved doping profile is significant less than that of the original doping profile, and thus may induce less surface potential fluctuation than the other. Figure 4.6 shows the static transfer characteristics of 16 nm planar SRAM with higher V_th devices with vertical doping profile. The result shows that vertical doping profile engineering can further suppress RDF induced SNM fluctuation from 41.7 % to 30.5 %; however, it may also suffer from more serious short channel effect (SCE), which reduces the SNM to 71 mV. Additionally, the PVE-induced SNM fluctuation is increased from 18 % to 24.4 %.

4.2 : Device Level Improvement 61

Figure 4.4: Nominal and fluctuated static transfer characteristics of improved 6T SRAM cells, where the Vthof devices were raised to 350 mV. The SNM increased to 92 mV, PVE and RDF induced fluctuation are 16.6 mV and 38.3 mV, respectively.

Figure 4.5: There will be 758 dopants are within a large rectangular solid, in which the equivalent doping concentration is 1.48 × 10¹⁸cm⁻³. The dopant distribution in the direction of channel depth, follows the normal distribution (b). The partitioned cubes are equivalently mapped into channel region for dopant position/number-sensitive device

simulation (c). Similarly, dopants within the 16 nm³ cubes may vary from zero to 14 (the average number is six) (d).

The vertical dopant distribution of the improved and the original doping profile, are shown in (e) and (f).

4.2 : Device Level Improvement 63

Figure 4.6: Nominal and fluctuated static transfer characteristics of 16 nm with higher V_thdevices and vertical doping profile engineering, where the SNM is 71 mV, PVE and RDF induced fluctuation are 17.3 mV and 21.7 mV, respectively.

The reduced SNM and increased PVE induced fluctuation are result from enhanced short channel effect (SCE).

Though the use of high V_thand vertical doping profile engineering can enlarge the SNM and reduce SNM fluctuation. The increased V_thalso reduce the write noise margin and slow down the operation speed. Therefore, based on the same layout area as 16-nm-gate planar MOSFETs, a 16-nm-gate SOI FinFETs with an aspect ratio (defined by the fin height / the fin width) of two is then adopted to replace the planar MOSFETs to examine associ-ated fluctuation resistivity against RDF and PVE. Without losing generality, the equivalent doping concentration is 1.48 × 10¹⁸ cm⁻³. 1516 dopants are generated in a large cube (80 nm × 80 nm × 160 nm) and partitioned into sub-cubes (16 nm × 16 nm × 32 nm), as shown in Figs. 4.7(a) and 4.7(b), respectively. The number of dopants in a sub-cube may vary from 2 to 24, and the average is 13, as shown in Fig. 4.7(c). These sub-cubes are equivalently mapped into the 16-nm-gate SOI FinFET, as shown in Fig. 4.7(d). To compare the device characteristics on a fair basis, the nominal threshold voltages of SOI FinFETs are calibrated to 140 mV, which is the same nominal threshold voltage as in the original cases.

RDF and PVE induced threshold voltage fluctuation is summarized in the Table 4.1. Com-paring with the original device, the threshold voltage fluctuation of 16-nm-gate NMOSFET is significantly reduced from 61 mV to 42 mV. The well control of device channel reduces both effects of RDF and PVE. Similarly, the random dopant fluctuation dominates the de-vice characteristic fluctuations. Figure 4.8 shows the static transfer characteristics of 16 nm SOI FinFET SRAM cells, where the dashed lines illustrated RDF and PVE fluctuated

4.2 : Device Level Improvement 65

cases, and the solid line is the nominal case. The nominal SNM is 125 mV and RDF and PVE induced fluctuations are suppressed to 5% and 1% only, respectively. The improved nominal SNM is due to the SOI-FinFET presented larger transconductance than planar MOSFET under the same V_th. A simplified correlation between device transconductance and SNM [4] could be expressed as following:

SNM ∝ s

1 − I_nx

g_m,pmos − I_ax

g_m,nmos, (4.1)

where the I_nx is the saturation drain current of driver transistor and I_ax is the saturation drain current of access transistor. The SNM thus increases as transconductance increases.

Therefore, even the SOI FinFETs is with low threshold voltage, 140 mV, as planar MOS-FETs, the large transconductance still provides a large enough SNM to maintain regular circuit operation. Additionally, the PVE- and RDF-induced V_th fluctuations of FinFETs are significantly suppressed to 8.3 and 42.2 mV, which are 2.2 and 1.45 times smaller than planar MOSFETs.

Figure 4.9 summarizes the device and circuit viewpoint improvement techniques. The 8T SRAM exhibits promising SNM and σSNM because of the turned off of access tran-sistors in 8T SRAM when data reading. For planar MOSFETs with 140 mV, the SNM is enlarged to 230 mV and the σSNM is reduced to 22 mV. The circuit improvement ap-proach can provide large SNM and is with no process change. Therefore, it’s promising in near future design at a cost of chip area. To prevent the increase of chip area, the design

approach from device engineering has to be developed. By adjusting the V_th to 350 mV, the SNM of 6T planar SRAM can be enhanced to 92 mV with 45% normalized σSNM (41.8 mV in σSNM ). We then employed the doping profile engineering to reduce the nor-malized σSNM to 39.1% (27.6 mV in σSNM ). However, the SNM is reduced to 71 mV because of the stronger SCEs. The design of device V_th and doping profile is trade-off and therefore can be further investigated. Therefore, to have a large SNM with sufficient small σSNM , the SOI FinFETs SRAM is design and exhibits a large enough SNM (125 mV) with 5.3% normalized σSN M (6.8 mV in σSNM ). The use of vertical channel transistor in SRAM circuit is useful and promising in the next generation nanoscale device circuit.

4.2 : Device Level Improvement 67

Figure 4.7: (a) Discrete dopants randomly distributed in the large cube with the average concentration of 1.48 × 10¹⁸cm⁻³. There will be 1516 dopants within the large cube, dopants may vary from 2 to 23 (average = 13) within sub cubes of 16 nm × 16 nm × 32 nm [(b) and (c)]. The sub-cubes are equivalently mapped into channel region of SOI FinFET for discrete dopant simulation as shown in (d).

Table 4.1: PVE and RDF induced V_thfluctuation of 16 nm SOI FinFET.

The fluctuations are significantly suppressed compared to planar MOSFETs.

Fluctuation Source VthFluctuation

PVE 8.3 mV

RDF 42.2 mV

Figure 4.8: Nominal and fluctuated static transfer characteristics of 16 nm SOI FinFET SRAM cells, where the nominal SNM is 125 mV.

4.2 : Device Level Improvement 69

Figure 4.9: Summary of RDF and PVE induced normalized SNM fluctuation and nominal SNM for different improvement techniques. For circuit level improvement, 8T SRAM reveals higher SNM and lower SNM fluctuation than 6T SRAM with CR = 2. For device level improvement, SOI FinFET SRAM increased the SNM to 125 mV and the normalized RDF and PVE induced SNM fluctuation are suppressed to 5.3% and 1.2%, respectively.

Conclusion

I

Finally, we suggest future work.

5.1 Summary

In this thesis, an experimentally validated three-dimensional “atomistic” coupled device-circuit simulation approach has been advanced to investigate the dependence of intrinsic parameter fluctuations in nanoscale SRAM cell. The roll-off characteristics of 6T SRAM from 65-nm- to 16-nm-gate are examined, in which the domination source of fluctuation, RDF, has been found. Additionally, the scaled SNM from 138 mV to 20 mV and enlarged SNM fluctuation from 4% to 80% implies the importance of suppression RDF fluctuation

70

5.1 : Summary 71

in SRAM circuit. The device-circuit simulation approach has been further examined by analytic expression of σV_th and statistically independent rule in Eqs. (3.1) and (3.3). To improve the scaled SNM and large σSNM in 16-nm-gate 6T SRAM, approaches pro-posed from circuit and device design were presented. From the time-to-market viewpoint, the circuit-level improvement of 8T SRAM is promising at a cost of 30% extra chip area.

To further increase the chip density, the device engineering is necessary. The techniques of raise of device V_thand doping profile engineering can increase SNM and reduce σSNM , respectively. However, there is a trade-off relation between these two techniques because of the degraded speed and enlarged SCEs, respectively. Hence, based on the same layout area, the use of SOI FinFETs in 6T SRAM has been examined. The SNM of 6T SOI FinFETs SRAM is 125 mV and the normalized SNM fluctuation is suppressed significantly to 5.3%

(6.8 mV in σSNM ). The result shows that the 8T SRAM architecture can provide largest SNM and is fascinating among discussed approaches in near future design; however, to prevent the increase of chip area and suppress the intrinsic parameter fluctuations, develop-ment of fabrication for SOI FinFET SRAM is crucial for sub-22nm technology era. This study investigates the roll-off characteristics and the stability of SRAM and consequently provides an insight into design of fluctuation resistant nanoscale memory circuits.