We have discussed the random-dopant-effect and process-variation-effect induced SNM fluctuation of SRAM circuits in the thesis. However, the influence of intrinsic parameter variability on write noise margin, operation speed, power consumption, and other charac-teristics are not clear yet and will be examined in the future. From our result, although the influence of gate length deviation and line edge roughness may be neglected in FinFET SRAM, the non-ideal fin taper angles (i.e., the fin angle is not approaches to 90 ˚) may need to be taken into account. In our previous study [63], the SCE is degrades due to slant of the sideward wall of silicon fin, which leads to current crowding and deteriorates the performance of a device.
There’s another fluctuation source called random telegraph noise (RTN), which is a stochastic fluctuation of the threshold voltage or the drain current between two levels, duced by the capture and emission of single electrons in a gate oxide trap [64]. The in-fluence of RTN is often investigated in flash memories [64, 65] and neglected in SRAM.
However, the RTN is comparable at half pitch 45 and becomes larger at half pitch 32 and beyond compared to RDF [66], and should be paid more attention. Moreover, the grain size variability of high-k metal gate induced SRAM characteristics fluctuation will be further studied. Other fluctuation suppression techniques can be further investigated such as new
5.2 : Future Work 73
circuit architecture or lateral asymmetry channel (LAC) doping profile. LAC MOS tech-nologies have been verified to have the ability to improve the SRAM performance [67], but the fluctuation has not been investigated yet. Besides, we will try to construct compact models to capture the RDF induced device variability.
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