Polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are currently investigated for applications in active matrices liquid crystal displays (AMLCDs).
The possibility to integrate on the same substrate driving circuit as well as switching devices seems to represent a major advantage of the poly-Si technology over the amorphous silicon one. For switching devices applications, the off-state leakage current of TFTs is the major concern. Although the field effect mobility of poly-Si TFTs is much higher than that of amorphous TFTs, the higher anomalous off-state leakage currents in poly-Si TFTs are also found. The leakage currents can be reduced by either decreasing the trap state density or reducing the high electric field near the drain junction. For the driving circuit applications, the hot carriers phenomena are likely to occur in poly-Si TFTs, where supply voltages can be relatively high in the range 10-30 V [1.63]. As well known in crystalline Si (c-Si) MOSFET’s, hot carrier phenomena are strongly depended upon the maximum electric field near the drain junction [1.64]. It is worth pointing out that in poly-Si TFTs, due to the high density
of trap states localized at the grain boundaries, it is possible to achieve high electric fields, even at moderate biases. Moreover, poly-Si TFTs also suffer from floating body effect due to impact ionization occurring in the high electric field region at the drain end of the channel. This effect results in an increase of the output conductance, and it is responsible for degradation of the device characteristics both in digital and in analog applications such as noise margins and available voltage gain loss [1.65].
All these undesirable effects, including off-state leakage currents, hot carriers reliability, kink effect are all related to the high electric field near the drain junction.
For the further development, high versatile circuits and systems need to be fully integrated on the display panel substrate, which is the concept of system-on-panel (SOP). As performance and complexity requirements increase, there is a need to scale down device geometries to achieve higher speeds and packing densities.
Unfortunately, those undesirable effects in the electrical characteristics that mentioned above become particularly important as the channel length and gate insulator thickness are reduced. Those all are increased with the higher drain electric field near the drain junction. These undesirable effects prohibit the use of LTPS TFTs in many high-performance circuit applications. Therefore, the drain-field-relief structure plays an essential role for the future prospection.
Device structures which can reduce the electric field near the drain junction can be adopted to reduce the leakage current of poly-Si TFTs. Lightly doped drain (LDD) and offset gate are commonly used structures for reducing leakage current. Besides, an additional advantage of such structures is enhancing the hot carrier endurance by the electric field relief. The typical offect and LDD structure are shown in Figs.1-1 and 1-2, respectively. However, although the high resistivity of LDD and offset regions can effectively reduce the leakage current, unfortunately, the driving
on the length of LDD and the dose in LDD. In order to reduce leakage current without degrading driving current significantly and to get a maximum on/off current ratio, the length and dose of LDD should be carefully determined. As well as LDD structure, the length of offset region of offset gate structure should be carefully determine to keep the driving capability.
Recently, advanced field-relief-structure such as field induced drain (FID) [1.66], [1.67] and gate-overlapped LDD (GOLDD) structure has been adopted to suppress the high drain field effects for improving device reliability and reducing leakage current while a high on-state current remains. The FID and GOLDD structure are shown in Figs.1-3 and 1-4, respectively.
In FID structures, the offset region is coupled by a sub-gate. The sub-gate is biased to induce inversion carriers in the offset region when the TFTs operate in the on state, so that the inversion carriers contribute to a lower resistivity in on state. In GOLDD structures, the LDD region is overlapped under gate edge. As well as FID structures, the surface of LDD region is inverted to a lower resistivity current path when the TFTs operate in the on state. A high on/off ratio can be achieved by such those advanced application because reducing leakage current while a high on-state current remains.
However, the formation of FID or GOLDD structure generally requires an additional lithography step or complex fabrication process. Besides increasing fabrication cost, the misalignment in layer registration can result in asymmetrical characteristics of TFT and poor uniformity of TFT performance, especially for large-area glass substrates.
Many other structures have been proposed to enhance TFT performance, such as the active poly-Si gate [1.68], [1.69], the multi-gate structure [1.70], the elevated channel structure [1.71], and the four-terminal TFT structure [1.72] etcetera. Most of
the newly developed structures can effectively improve the characteristics of conventional TFTs, especially in decreasing the anomalous leakage current in the off-state of poly-Si TFTs. In general, the reliability of poly-Si TFTs can also be enhanced by utilizing these structures because of the reduction of electric field near the drain junction.