Chapter 3 Reliability Analyses of T-Shaped-Gate Low-Temperature
3.2 Effects of Drain Avalanche Hot Carrier (DAHC) Stress on T-Gate LTPS TFTs with
Vacuum Gaps
Figures 3-1 and 3-2 show the transfer characteristics of the T-Gate and conventional TFTs before and after drain avalanche hot carrier stress at VD = 10 V, VG
= 1.5 V from 0 to 1000 seconds, restively. The corresponding extracted electrical parameters are listed in Table 3-2 and Table 3-3. The threshold voltage shift as a function of stress time is shown in Fig. 3-3. The threshold voltage shift of T-Gate and conventional TFTs after drain avalanche hot carrier stress at VD = 10 V, VG = 1.5 V for 1000 seconds were 0.11 V and 2.7 V, respectively. From Figs. 3-4 and 3-5, the less degradation is observed in T-Gate TFTs. It is obvious that a serious degradation on transconductance, on-current, drain induced barrier lowering (DIBL), and large threshold voltage shift in the conventional TFTs. On the other hand, the proposed T-Gate TFTs show a better immunity on drain avalanche hot carrier stress.
In the poly-Si TFT’s channel, defects in grain boundaries and intra-grains would trap carriers and form potential barriers, affecting the current transport. During the DAHC injection, more trap states (acceptor-like) or negative charges are created,
raising the barrier height [3.6]-[3.8]. Therefore, serious degradation on Ion can be observed clearly. Figure 3-6 shows the plot of the potential barrier for carrier transport induced by filled negative trap states (or negative charges) in the poly-Si channel.
Additionally, we can observe that the leakage current reduced after DAHC stress.
Considering that leakage current is associated with the amount of defects or traps in the drain depletion region, the schematic diagram of the depletion region and the corresponding energy band diagram of the drain in the off-state are shown in Fig. 3-7.
The generation of leakage current is attributed to thermionic emission at a low electric field and the field-enhanced emission (i.e., F–P emission or trap-assisted band-to-band tunneling) at a high electric filed. Hence, the magnitude of the electrical field and the amount of traps within the drain depletion region are the two important factors considered in studying the variations of leakage current.
The reduction of leakage current after DAHC stress is because some positive charges are created in the poor-quality gate oxide near the drain. These positive oxide charges lower the local electric field in the drain depletion region. The electric field near the drain side before and after the creation of positive oxide charges is schematically depicted in Fig. 3-8. The positive oxide charges lift the electric field in the gate oxide but reduce that in the poly-Si. Thus, the reduction of the local electric field in the drain depletion region decreases leakage current [3.8].
Furthermore, these positive oxide charges are created in the localized region (i.e.
near the drain). This phenomenon could be revealed by Figs. 3-9 and 3-10. In order to explain this phenomenon, the reverse mode transfer characteristics are measured. Fig.
3-10 shows the reverse mode measured transfer characteristics of the T-Gate TFTs before and after drain avalanche hot carrier stress at VD = 10 V and VG = 1.5 V from 0 to 1000 seconds. There is no shielding effect of positive oxide charges because of those positive oxide charges are only located near the drain , instead of the entire
channel region.
Another stress condition was applied to T-Gate TFTs to further characterize the local shield effect of positive oxide charges on leakage current variation. Fig. 3-12 shows the transfer characteristics measured at VD = 3 V of the T-Gate TFTs before and after “electron oxide trap stress＂ at VD = 0 V and VG = 20 V from 0 to 1000 seconds.
In this stress condition, negative oxide charge was created. The leakage current increased with the stress time as shown in Fig. 3-14. On the other hand, Fig. 3-13 shows the leakage current variation measured at VD=3V of the T-Gate TFTs before and after drain avalanche hot carrier stress at VD=10V, VG=1.5V for 10 to 1000 seconds. The minimum leakage current increased after DAHC stress, while the maximum leakage decreased. The increasing defect density arises form DAHC stress contributes to the increase of the minimum leakage current. The decreased maximum leakage current is attributed to the local shield effect of positive oxide charges in DAHC stress.
The reliability of T-Gate TFTs with and without NH3 passivation was also discussed. Fig. 3-15 shows the transfer characteristics of the T-Gate TFTs without plasma passivation before and after hot carrier stress at VD = 10 V and VG = 1.5 V from 0 to 1000 seconds. As comparied to the T-Gate TFTs with 1-hour NH3
passivation 1HR, that without plasma passivation exhibited a better reliability on DAHC, Figs. 3-16 and 3-17 show the transconductance and DIBL degradation of T-Gate TFTs with and without plasma passivation after DAHC, respectively. It was well known that conduction carriers can obtain energy from the high electric field and become “hot”. These high-energy carriers can easily break weak bonds existing in poly-Si during DAHC stress [3.9]. In NH3 passivation treatment, the incorporation of hydrogen into the channel layer to passivate the defect states is effective and
of device performance, however, the weak Si-H bond contribute to worsen the reliability.
3.3 Summary
In this chapter, T-Gate LTPS TFTs have been demonstrated a better immunity on drain avalanche hot carrier stress.
In the first part, the effects on DAHC stress of T-Gate TFTs was investigated.
After 1000-sec stress, the maximum transconductance decrease about 78% and 83%, and the threshold voltage shift was about 0.11 V and 1.7 V in T-Gate and conventional TFTs, respectively. Similarly, T-Gate TFTs have a smaller DIBL shift of 125 mV in comparison with 2727 mV of the conventional ones.
Furthermore, the variation of leakage current after DAHC stress was discussed.
Due to the local shield effect of positive oxide charges in DAHC stress, the maximum leakage current decreased but the minimum leakage current increased with the increasing stress time. The increase of minimum leakage current was because more defect states are arisen during DAHC stress. In addition, the positive oxide charges are only located near the drain region, so that the shield effect cannot not be seen in the reverse-mode measurement. Accordingly, the leakage current measured in the reverse-mode almost changes nothing.
Chapter 4
Conclusions
---
In this thesis, we have demonstrated high performance and high reliability T-Shaped-Gate polycrystalline silicon thin-film transistors fabricated by a low-cost process. The results and discussions are summarized in this chapter.
Simulation results show the proposed T-Gate structure can suppress the maximum lateral and vertical electric fields near the drain accompanied with the reduction of impact ionization coefficient. It is more effective for the thinner oxide case. The maximum lateral and vertical electrical fields near the drain are reduced with about 48.9% and 82.0%, respectively. High-performance T-Gate TFTs with on/off ratio exceeding 109 have been demonstrated. The maximum leakage current (i.e. the drain current at VG = -15 V and VD = 0.1 V) was distinctly improved to be about three orders lower by applying T-Gate structure. Meanwhile, with the aid of sub-gates of T-Gate TFTs the driving current is only decayed about with 35% at high gate bias (i.e.
VG = 15 V) in comparison with that of conventional ones. The resistance of the offset region related to the driving current reduction was also discussed. The offset resistance (Roffset) of T-Gate TFTs is 4.2k ohm, which is 30% of turn-on-resistance (Ron). In addiction, the alleviation of kink effect was also observed due to the lower impact ionization from the proposed structure.
T-Gate TFTs with thinner oxide have better field-relief efficiency as compare to those with thicker ones. It is because the vacuum contributes more weighting in the effective oxide thickness for the thinner oxide case.
The symmetry of electrical characteristics was performed to verify that ITO side etching step was a self-aligned process. The slight asymmetrical transfer characteristics of T-Gate TFTs without passivation treatment were caused from the variation of grain boundary distribution, and the mismatch can be eliminated by further passivation treatment. In the statistical analyses, normal distributions were also found in the statistical bar chart for △I (drain current difference between forward and reverse-mode measurement at VD=3V). The standard deviations of △I for T-Gate TFTs with and without NH3 passivation was 0.83 pA and 6.12 pA, respectively.
Accordingly, the self-aligned ITO side etching process was verified. Additionally, the oxide breakdown field can be promoted from 6.2 MV/cm to 8.5 MV/cm by adopting the T-Gate TFTs with 1000 Å-thick vacuum gaps.
Moreover, T-Gate LTPS TFTs have been demonstrated to a better immunity to drain avalanche hot carrier stress and self heating stress. After 1000sec stress time, the maximum transconductances decrease about 78% and 83% in T-Gate and conventional TFTs, respectively. The threshold voltage shift was about 0.11 V and 1.7 V. Similarly, T-Gate TFTs had a smaller DIBL shift of 125 mV as compared to 2727 mV of the conventional ones.
Furthermore, the variation of leakage current after DAHC stress was discussed.
Due to the local shield effect of positive oxide charges in DAHC stress, the maximum leakage current decreased with increasing the stress time, but the minimum leakage current increased with increasing the stress time. The increase of minimum leakage current was because more defect states were created during DAHC stress. In addition, the positive oxide charges were only located near the drain region, so that the shield effect cannot be observed in the reverse-mode measurement. Accordingly, the leakage current measured with reverse mode almost change nothing.
To sum up, T-Gate structure with vacuum gaps was attractive, especially for the
thin oxide devices. The characteristics of T-Gate LTPS TFTs with vacuum gaps exhibited excellent on/off current ratio. The leakage current can be decreased dramatically while the driving can be maintained. Besides, the improvement of oxide breakdown characteristics can enlarge the operation range of the gate bias.
Furthermore, the proposed T-Gate TFTs have much superior immunity to the hot carrier degradation as compared with the conventional ones.
Tables
function LCD driver LCD driver D/A converter
Table 1-1 The performances and the related processes of LTPS TFTs for the SOP roadmap are going on in the future.
Tvacuum Mobility
(cm2/V·s) Vth (V) Ion/off SS (mV/dec)
1000Å 129 -0.249 2.29E+09 238
500Å 130 -0.585 4.47E+08 201
0 Å (Conv.) 133 -0.393 1.89E+08 192
Table 2-1 Electrical characteristics of T-Gate and conventional TFTs with gate oxide of 400 Å, channel width of 10 μm and gate length of 5 μm.
Tox Leakage current
@VG = -15 V ; VD = 3 V
On current
@VG = 15 V ; VD = 3 V
T-Gate TFTs 6.31E-11 3.21E-4
400Å
Conv.
TFTs 1.81E-8
X(1/3490)
4.89E-4
X 0.65
T-Gate TFTs 1.77E-11 2.06E-4
800Å
Conv.
TFTs 4.72E-10
X (1/26)
2.9E-4
X 0.71
Table 2-2 Maximum leakage and on-state current of T-Gate and conventional TFTs with different gate oxide thickness, the channel width and length were 10μm and 5μm,
respectively.
Mobility (cm2/V·s)
Vth
(V) Ion/off SS (mV/dec)
DIBL (mV) No
passivation 106 -0.563 1.71E+08 246 302
NH3 1HR
passivaiotn 129 -0.249 2.29E+09 238 162
Table 2-3 Electrical characteristics of T-Gate TFTs before and after NH3 passivaiotn for 1HR
Average Standard Deviation
ᇞ I for No NH3 plasma
passivation
0.78 pA 6.12pA
ᇞ I for NH3 plasma
passivation1HR
0.06 pA 0.38 pA
Table 2-4 Average and standard deviation of 30 measured △I samples of T-Gate TFTs. The thickness of gate oxide was 400Å. The vacuum gaps height was 1000Å.
Table 3-1 Parameter variation and corresponding possible degradation mechanisms.
(Ref. Farmkis et al.,IEEE Electron Device Lett., 2001)
T-Gate TFTs
Stress Time(sec) Mobility
(cm2/V·s) Vth (V) Ion/off DIBL(mV)
0 129 -0.490 9.62E+08 189
10 67 -0.470 3.10E+08 218
50 44 -0.454 2.25E+08 234
100 40 -0.446 2.03E+08 247
200 35 -0.440 2.05E+08 251
500 32 -0.405 1.86E+08 289
1000 29 -0.381 1.72E+08 314
Table 3-2 Electrical parameter of the T-Gate TFTs before and after drain avalanche hot carrier stress at VD=10V, VG=1.5V for 10 to 1000 seconds.
Conv TFTs
Stress Time(sec) Mobility
(cm2/V·s) Vth (V) Ion/off DIBL(mV)
0 124 0.474 1.09E+09 117
10 37 0.862 9.98E+07 510
50 30 1.529 6.20E+07 1177
100 25 1.885 5.35E+07 1545
200 23 2.084 4.50E+07 1746
500 20 2.473 3.72E+07 2133
1000 21 3.178 3.23E+07 2844
Table 3-3 Electrical parameters of the conventional TFTs before and after drain avalanche hot carrier stress at VD=10V, VG=1.5V for 10 to 1000 seconds.
T-Gate TFTs Conv. TFTs
△Vth
After 100 sec 0.04V 1.41V
△Gm (%)
After 100 sec 66% 80%
△DIBL (mV)
After 100 sec 83 1428
Table 3-4 Electrical parameters shift of the T-Gate and conventional TFTs before and after drain avalanche hot carrier stress at VD=10V, VG=1.5V for 10 to 1000 seconds.
without NH
3
passivation
Stress Time(sec) Mobility (cm2/V·s)
Vth (V) Ion/off DIBL(mV)
0 99 -0.287 2.65E+08 342
10 59 -0.250 2.42E+08 383
50 41 -0.218 1.86E+08 415
100 38 -0.206 1.74E+08 427
200 35 -0.156 1.54E+08 477
500 29 -0.131 1.39E+08 504
1000 27 -0.097 1.33E+08 539
Table 3-5 Electrical parameters of the T-Gate TFTs without plasma passivation before and after drain avalanche hot carrier stress at VD=10V, VG=1.5V for 10 to 1000
seconds.
Figures
Fig. 1-1 The offset TFTs structure proposed by Jung-In Han et al.
Fig. 1-2 The LDD TFTs structure proposed by Shunji Seki et al.
Fig. 1-3 The FID TFTs structure proposed by Joon-Ha Park et al.
Fig. 1-4 The GOLDD TFTs structure proposed by Mutsuko Hatano et al.
Fig. 1-5 The Air-Gap TFTs structure proposed by Min-Cheol Lee et al.
Fig. 2-1 (a) The device structure of proposed T-Gate LTPS TFTs with vacuum gaps
Fig. 2-1 (b) The schematic illustration of the equivalent device structure of the proposed T-Gate LTPS TFTs with vacuum gaps
excimer laser irradiation
Fig. 2-2 (a) The schematic illustration of the low energy regime corresponding to energy densities that partially melting the a-Si thin film
excimer laser irradiation
melted Si
substrate substrate substrate
homogeneous nucleation
small-grain poly-Si
Fig. 2-2 (b) The schematic illustration of the high energy regime corresponding to energy densities that completely melting the a-Si thin film
excimer laser irradiation
Fig. 2-2 (c) The schematic illustration of the super lateral growth regime corresponding to energy densities that nearly completely melting the a-Si thin film
Fig. 2-3 (a) The two-dimensional electrical potential distributions of the conventional TFTs
Fig. 2-3 (b) The two-dimensional electrical potential distributions of the proposed T-Gate TFTs
0 2 4 6 8 10 12
Position Along Channel Layer, x (μm)
Conv. TFTs
T-GateTFTs (LSub-Gate= 2500 A)
Drain Source
Fig. 2-4 (a) The lateral electric fields along channel layer of the conventional and proposed T-Gate TFTs
Position Along Channel Layer, x (μm)
Conv. TFT
T-GateTFT (LSub-Gate= 2500A)
Drain Source
Fig. 2-4 (b) The vertical electric fields along channel layer of the conventional and proposed T-Gate TFTs
-2 0 2 4 6 8 10 12 14 16 18 20
Electric Field ( V/cm )
Position Along Channel Layer, X ( μm ) VG = 4 V ,VD = 12 V ,Tox = 1000 A
Conv. TFTs
Fig. 2-5(a) The lateral electric fields of conventional TFTs with varied channel lengths
-2 0 2 4 6 8 10 12 14 16 18 20
Electric Field ( V/cm )
Position Along Channel Layer, X ( μm ) VG= 4 V , VD = 12 V, Tox = 1000 A
Fig. 2-5(b) The lateral electric fields of T-gate TFTs with varied channel lengths
-2 0 2 4 6 8 10 12 14 16 18
Impact Ionization coefficient ( cm-1 )
Position Along Channel Layer, X (μm)
Conv. TFTs VG = 4 V, VD = 12 V,Tox = 1000 A
Fig. 2-6(a) The impact ionization coefficients of conventional TFTs with varied channel lengths
Fig. 2-6(b) The impact ionization coefficients of T-gate TFTs with varied channel
-2 0 2 4 6 8 10 12 14 16 18
Impact Ionization coefficient ( cm-1 )
Position Along Channel Layer, X ( μm )
T-Gate TFTs VG = 4 V, VD= 12 V,Tox= 1000 A
8.28 8.37 8.46
Electric Field ( V/cm )
Position Along Channel Layer, X ( μm ) Conventional TFTs
VG= 4V, VD=12V, L=5um
Fig. 2-7(a) The lateral electric fields of conventional TFTs with varied oxide thicknesses
Electric Field ( V/cm )
Position Along Channel Layer, X ( μm ) T-gate TFTs
VG =4V , VD =12V, L=5um
Fig. 2-7(b) The lateral electric fields of T-Gate TFTs with varied oxide thicknesses
8.0 8.2 8.4
Impact Ionization coefficient ( cm-1 )
Position Along Channel Layer, X ( μm )
Fig. 2-8(a) The impact ionization coefficients of conventional TFTs with varies oxide thicknesses
Impact Ionization coefficient ( cm-1 )
Position Along Channel Layer, X ( μm )
Fig. 2-8(b) The impact ionization coefficients of T-Gate TFTs with varied oxide thicknesses
Fig. 2-9 (a) Buffer layer deposition on the glass substrate
Fig. 2-9 (b) Amorphous Silicon layer deposition by PECVD system
Fig. 2-9 (c) Crystallization of the amorphous-Si film using excimer laser irradiation
Fig. 2-9 (d) Definition of active region
Fig. 2-9 (e) Gate oxide deposition by PECVD system at 300°C
Fig. 2-9 (f) The stacked ITO/Mo layer deposition followed by patterning as the gate electrode
Fig. 2-9 (g) Selective side etching of the ITO layer to form the T-shape gate electrode structure
Fig. 2-9 (h) Self-aligned source and drain implantation to form source and drain region
Fig. 2-9 (i) Silane-base SiOx passivation layer deposition by PECVD system resulting in the in-situ vacuum gaps and then dopant activation by RTA system
Fig. 2-9 (j) Contact hole opening and metallization
Fig. 2-9 (k) NH3 plasma passivation
Fig. 2-9 (l) The conventional structure
Fig. 2-10 The SEM image of the in-situ vacuum gaps under the T-shape gate structure
Fig. 2-11(a) SEM graphs of excimer laser crystallized polycrystalline silicon. The laser energy density was 225 mJ/cm2 and 98% overlapping
Fig. 2-11 (b) SEM graphs of excimer laser crystallized polycrystalline silicon. The laser energy density was 257 mJ/cm2 and 98% overlapping
Fig. 2-11 (c) SEM graphs of excimer laser crystallized polycrystalline silicon. The laser energy density was 263 mJ/cm2 and 98% overlapping
Fig. 2-11 (d) SEM graphs of excimer laser crystallized polycrystalline silicon. The
laser energy density was 257 mJ/cm2 and 99% overlapping
Fig. 2-12 The SEM graphs of the grain size corresponding to laser-energy densities and overlapping in SLG region.
Fig. 2-13 Cross-section SEM graphs and embedded TEM image of excimer laser
crystallized polycrystalline silicon
Log-scale drain current ( A )
Gate voltage ( V )
Fig. 2-14 Transfer characteristics of n-channel T-Gate LTPS TFTs with channel length of 5 μm and channel width of 10 μm, and gate oxide of 400 Å.
Fig. 2-15 Output characteristics of n-channel T-Gate LTPS TFTs with channel length
of 5 μm and channel width of 10 μm, and gate oxide of 400 Å.
Log-scale drain current ( A )
Gate voltage ( V )
Fig. 2-16 Transfer characteristics of n-channel T-Gate LTPS TFTs with channel length of 5 μm and channel width of 10 μm, and gate oxide of 400 Å.
Log-scale drain current ( A )
Fig. 2-17 Transfer characteristics of n-channel T-Gate LTPS TFTs with channel length of 5 μm and channel width of 10 μm, and gate oxide of 400 Å.
Fig. 2-18 The schematic illustration of the equivalent structure of T-Gate TFTs compared to conventional TFTs in which the thickness of gate oxide is 400 Å.
Fig. 2-19 The schematic illustration of the equivalent structure of T-Gate TFTs compared to conventional TFTs in which the thickness of gate oxide is 800 Å.
0 1 2 3 4 5 6 7 8 9 10 11
Turn-On Resistance R on (ohm)
Channel Length (μm)
5.63k ohm
Fig. 2-20 Turn-On resistance as a function of channel length at different gate voltages
for conventional TFTs
Turn-On Resistance R on (ohm)
Channel Length (μm)
9.22k ohm
Fig. 2-21 Turn-On resistance as a function of channel length at different gate voltages for T-Gate TFTs in which the thickness of vacuum gap is 500 Å
0 1 2 3 4 5 6 7 8 9 10 11
Turn-On Resistance R on (ohm)
Channel Length (μm)
Fig. 2-22 Turn-On resistance as a function of channel length at different gate voltages for T-Gate TFTs in which the thickness of vacuum gap is 1000 Å
-15 -10 -5 0 5 10 15
NH3 passivation 1HR No NH3 passivation Tvacuum =1000A Lsub-gate =2500A W10L5
Tox=400A
Mobility ( cm 2/Vs )
Fig. 2-23 Transfer characteristics of n-channel T-Gate LTPS TFTs with and without NH3 plasma passivation
Fig. 2-24 The schematic definition of the forward- and reverse-mode measurements
Fig. 2-25 Symmetrical transfer characteristics of n-channel T-Gate LTPS TFTs before NH3 plasma passivation
Fig. 2-26 The schematic definition of the forward mode and reverse mode
without plasma passivation
Fig. 2-27 The statistical bar chart of the drain current difference (△ I) between forward mode and reverse mode for T-Gate TFTs in which the thickness of vacuum
gap is 1000Å and the Lsubgate is 2500 Å without plasma passivation
-15 -10 -5 0 5 10 15 1E-14
Fig. 2-28 Symmetrical transfer characteristics of n-channel T-Gate LTPS TFTs with NH3 1 HR plasma passivation
NH3 plasma passivation 1HR
Fig. 2-29 The statistical bar chart of the drain current difference (△I) between forward mode and reverse mode for T-Gate TFTs in which the thickness of vacuum
gap is 1000 Å and the Lsubgate is 2500 Å with 1-HR NH3 plasma passivation
0 1 2 3 4 5 6 7 8 9 10
Fig. 2-30 Gate oxide breakdown fields of T-Gate and conventional TFTs
0 2 4 6 8 10 12
Position Along Channel Layer, X ( um ) Tvacuum=0 (CONV.)
Fig. 2-31 Simulated electric fields in the gate oxide of T-Gate and conventional TFTs
-15 -10 -5 0 5 10 15
Fig. 3-1 Transfer characteristics of the T-Gate TFTs before and after drain avalanche hot carrier stress at VD = 10 V and VG = 1.5 V from 0 to 1000 seconds.
Fig. 3-2 Transfer characteristics of the conventional TFTs before and after drain avalanche hot carrier stress at VD = 10 V and VG = 1.5 V from 0 to 1000 seconds.
1 10 100 1000
Fig. 3-3 Threshold voltage shift of T-Gate and conventional TFTs after drain avalanche hot carrier stress at VD = 10 V and VG = 1.5 V from 0 to 1000 seconds.
Fig. 3-4 Transconductance shift of T-Gate and conventional TFTs after drain avalanche hot carrier stress at VD = 10 V and VG = 1.5 V from 0 to 1000 seconds.
1 10 100 1000 0
500 1000 1500 2000 2500 3000
Stress time (s) T-Gate TFTs
Conv. TFTs
DIBL shift (mV)
Fig. 3-5 DIBL shift of T-Gate and conventional TFTs after drain avalanche hot carrier stress at VD = 10 V and VG = 1.5 V from 0 to 1000 seconds.
Fig. 3-6 Potential barrier for carrier transport raised by filled negative trap states (or charges) in poly-Si channel near drain.
(Ref. Shen De WANG, et al. JJAP Vol. 44, No. 9A, 2005, pp. 6435–6440)
Fig. 3-7 Schematic diagram of traps in drain depletion region and corresponding energy band diagram of Off-stated poly-Si TFT
(Ref. Shen De Wang, et al. JJAP Vol. 44, No. 9A, 2005, pp. 6435–6440)
Fig. 3-8 Comparison of electric fields in the interface of gate oxide and poly-Si near
Fig. 3-8 Comparison of electric fields in the interface of gate oxide and poly-Si near