In chapter 1, an overview of LTPS TFTs technology is given. The motivations of this thesis are subsequently explained to introduce this thesis.
In chapter 2, experimental processes of T-Gate TFTs are introduced. In order to verify the effect of the vacuum gaps on the electric field near the drain junction, device simulation was carried out by 2–D simulator for semiconductor devices.
Several simulations such as lateral and vertical electric field, impact ionization coefficient, and drain breakdown characteristic with various device geometries were
discussed. Electrical performance of the proposed devices was then revealed. After that, the series resistance of T-Gate TFTs was investigated. In order to verify the side etching process was self-aligned, symmetry of electrical characteristics was discussed.
The oxide breakdown characteristic was analyzed finally.
In chapter 3, the reliability issues of T-Gate LTPS TFTs with vacuum gaps were investigated by applying several drain avalanche hot carrier (DAHC) stress conditions.
Besides, variation of leakage current during DAHC stress was discussed.
Finally, conclusions will be given in chapter 4.
Chapter 2
Characterization of T-Shaped-Gate (T-Gate) Low-Temperature Polycrystalline Silicon Thin
Film Transistors with Vacuum Gaps
---2.1 Introduction
2.1.1 Introduction to T-Shaped-Gate Low-Temperature Polycrystalline Silicon Thin-Film Transistors (T-Gate LTPS TFTs) with Vacuum Gaps
In this work, a novel and simple process was introduced to fabricate T-Shaped-Gate (T-Gate) structures. The feature of the proposed structure is to embed vacuum (the lowest permittivity of k=1 in nature) [2.1] at the gate edge. Unlike other reported structures, our proposed structure needs neither additional lithography steps nor complex process. Therefore, a low-cost fabrication process can be achieved.
The schematic figure of the proposed T-Gate TFTs and its equivalent structure were shown in Figs. 2-1(a) and 2-1(b), respectively. The detail fabrication procedure was discussed in the later chapter. The vacuum gaps can reduce the vertical electric field near the drain due to the lowest permittivity of k=1. The vacuum gaps serve as an equivalent thicker oxide. Because the relative static permittivity of SiO2 is 3.9, the
equivalent oxide thickness of the vacuum gap is as high as 3.9 times. In this work, though the height of vacuum gap is only 1000Å, it is equivalent to a 3900 Å-thick SiO2 film [2.2]-[2.4]. The poly-Si region under vacuum gaps can be considered as the offset region and the gate edge over the vacuum cavity serves as a field plate connected with the gate, so that the proposed TFT operates as the field induced drain (FID) TFTs.
In this chapter, experimental process of T-Gate TFTs was introduced. The T-shaped-gate structure was analyzed by cross-section scanning electron microscope (SEM) image. In order to verify the effects of the vacuum gap on the electric field near the drain junction, device simulation was carried out by ISE (Integrated System Engineering) 2–D simulator for semiconductor device. Several simulations such as lateral and vertical electric fields, and impact ionization coefficient with various device geometries were discussed. Electrical performances of the proposed devices were then revealed. After that, the series resistance of T-Gate TFTs was investigated.
In order to verify the side etching step was a self-aligned process, symmetry of electrical characteristics was also investigated. These results successfully provide the demonstrations of fabricating high-performance T-Gate TFTs using a simple process.
2.1.2 Introduction to Excimer Laser Crystallization (ELC) Technique
In order to prepare poly-Si thin films, several ways have been reported including solid phase crystallization (SPC), metal induced lateral crystallization (MILC), and laser annealing [2.7]-[2.10]. Among these methods, the excimer laser annealing (ELA)
has been considered the most promising one. The excimer laser emits in UV light region with short pulse duration (10-30 ns) by the laser source of ArF, KrF, or XeCl (output wavelengths 193, 248, and 308 nm, respectively) gas source. The strong optical absorption of UV light and small diffusion length during the laser pulse in silicon imply that high temperature can be produced and cause melting of silicon without significant damage of glass substrate [2.11]. In addition, ELA poly-Si films possess good crystallinity and few intra-grain defects due to the melt-regrowth process. During ELA process, the mechanism of grain growth is quite sensitive to the laser energy density. Fig. 2-2 schematically illustrates the grain growth corresponding to the different laser energy densities. As shown in Fig. 2-2 (a), if the laser energy density is too small to melt the whole a-Si thin film, vertical solidification occurs and the un-melted solid layer remains to be a-Si, while the melted Si layer transform into poly-Si with small grain size [2.12]. Refer to Fig. 2-2 (b), if the laser energy density is large enough to completely melt the a-Si thin film, homogeneous nucleation occurs for deep supercooling, resulting in small grain size [2.13]. Only when the laser energy density is controlled around a specific threshold value large grain as large as 1 μm in diameter can be obtained, as shown in Fig. 2-2 (c). This specific controlled value is so called Super Lateral Growth (SLG) regime [2.14], which vividly illustrates the behavior of melted a-Si to recrystallize from very few un-melted Si residues to each other. For the very few residues as seeds, the lateral growth phenomenon causes large grain size.
2.2 Simulation Analyses of T-Gate LTPS TFTs with Vacuum Gaps
In order to verify the effects of the vacuum gaps of T-Gate TFTs on the electric field near the drain junction, the simulations with various channel lengths and gate oxide thicknesses have been carried out by ISE TCAD which is a commonly used 2-D numerical simulator for device analysis [2.16]. The geometrical dimension of vacuum gaps was fixed at which the thickness (Tvacuum) and the length (Lsub-gate) were 600 Å and 0.5 μm, respectively. The channel lengths varied form 10 μm to 1.5 μm, and the gate oxide thicknesses varied form 1000 Å to 100 Å. Fig. 2-3 (a) and Fig. 2-3 (b) show 2-D electrical potential distribution of the conventional and T-Gate TFTs, respectively. It can be seen that the dense equipotential lines near the drain region in conventional TFTs have been relaxed in the T-Gate TFTs. This indicated that electric field is consequently reduced by T-Gate structure. Fig. 2-4 (a) shows the lateral electric field along channel layer of the conventional and proposed T-Gate TFTs structure. It is observed that the lateral electric field near the drain region is sufficiently suppressed about 48.9% by the proposed T-Gate structure. Besides, the vertical electric field near the drain region has a 82.0% drop in comparison with conventional TFTs.
The simulation results of the lateral electrical field along the channel with various channel lengths were shown in Figs. 2-5 (a) and (b). It can be observed clearly that the electric field near the drain region is sufficiently suppressed by the proposed T-Gate structure especially when the channel length is scaled down. Furthermore, Figs.
2-6 (a) and (b) show the impact ionization coefficient with different channel lengths.
dependence on the electric field.
In addition, Figs. 2-7 and 2-8 show the lateral electric field and impact ionization coefficient along the channel with different oxide thicknesses. We can observe that the lateral electric field and the impact ionization factor are dramatically suppressed when the oxide thickness is decreased to 100 Å. The vacuum cap can be considered as an equivalent thicker oxide. When the thickness of gate oxide decreases to 100 Å, the vacuum cap can still provide a thick oxide near the drain region to suppress the drain electric field. From these simulation results, the T-Gate TFTs with thinner oxide thickness has better field-relief efficiency.
2.3 Fabrication of T-Gate LTPS TFTs with Vacuum Gaps
2.3.1 Fabrication Sequence of T-Gate LTPS TFTs with Vacuum Gaps
The detailed process flow of device fabrication is shown in Fig. 2-9(a)-(k). At first, a buffer layer that composed of 500 Å SiN and 1300 Å SiO2 thin film was deposited by plasma-enhanced chemical vapor (PECVD) system on the glass substrate. Then, a 500 Å amorphous silicon (a-Si) thin film was deposited by PECVD system on buffer layer. The a-Si thin film was transferred into poly-Si by 308 nm XeCl excimer laser. Before excimer laser crystallization, dehydrogenation was carried out in order to prevent the hydrogen explosion during laser irradiation. The laser energy density was 257 mJ/cm2 and 99% overlapping. After defining the active layer,
a 400 Å or 800 Å-thick SiO2 gate oxide was deposited by PECVD system at 300 °C.
Then, a 500 Å or 1000 Å-thick Indium Tin Oxides (ITO) was deposited follow by a 2000 Å-thick Mo films was deposited by sputter system sequentially. The stacked Mo/ITO films were simultaneously etched to pattern as the gate electrode. An Oxalic acid, (COOH)2‧2H2O, solution was then used to selectively etch the ITO layer without harming Mo thin film to form the T-shaped structure. The side etching length of ITO thin film was carefully controlled to 2500 Å and was confirmed by the scanning electron microscope (SEM) graph. A self-aligned phosphorous implantation was carried out to form source and drain regions. Following that, a 5000Å inter-layer of silane-based SiO2 was deposited by PECVD system and then densified through rapid thermal annealing (RTA) at 700 °C for 30 s. It should be noted that the silane (SiH4) free radicals are very active and chemisorbed on the substrates easily [2.15].
The dopants were activated during the densification of the inter-layer dielectric. Next, after the contact hole opening, 5000 Å Al was deposited and pattern to the interconnect metal. Finally, all TFTs were subjected to the NH3 plasma passivation treatment at 300°C for 1 hour to passivate the dangling bonds at the poly-Si/SiO2
interface and the trap-states of the poly-Si film. For the purpose of comparison, the conventional poly-Si TFTs without side-etching structure as shown in Fig.2-10 were also fabricated. The channel length (L) and width (W) of device used in this study were 5 μm and 10 μm, respectively. The channel length (L) is defined as the length of Mo gate electrode, the height of vacuum gap is defined as Tvacuum, and the length of ITO side etch is defined as Lsub-gate and confined to be 2500 Å for all T-Gate devices in this work. Lsub-gate and Tvacuum are determined according to the simulation results.
It should be noted that the vacuum gaps were in-situ formed during the inter-layer dielectric deposition by PECVD because of the chemical properties of
structure with vacuum gaps. A symmetrical T-shaped gate electrode has been successfully fabricated by the 2500-Å selective etching of ITO film under the Mo layer.
2.3.2 Material Analyses of ELC Poly-Si Thin Films
In this work, a 500 Å a-Si thin film was transferred to ploy-Si in Super Lateral Growth (SLG) regime mentioned in section 2.1.2. Figs. 2-11(a)-(d) show SEM graphs
of excimer laser crystallized ploy-Si with various laser energy densities and overlapping. Figure 2-12 reveals the dependence of grain size on laser energy densities and overlapping. We can observe that a larger grain size can be achieved by using larger laser energy density within the range from 225 to 263 mJ/cm2 when the overlapping was 98% or 99%. For 98% overlapping, the grain size of poly-Si crystallized with laser energy density of 225 mJ/cm2, 257 mJ/cm2, and 263 mJ/cm2 were about 800 Å, 3200 Å and 4600 Å, respectively. However, the large grain of ELC poly-Si thin film generally accompanies with poor uniformity and high surface roughness (usually called protrusion) resulted from volume expansion from liquid to solid phase. The protrusion shown in Fig. 2-13 of ELC poly-Si thin film could attribute to local breakdown of gate dielectric. Accordingly, it was a trade-off issue between the grain size and surface roughness.
The laser energy density of ELC used in this work was 257 mJ/cm2 with 99%
overlapping. The grain size of poly-Si film was about 3200 Å.
2.4 Electrical Characterization of T-Gate LTPS TFTs with Vacuum Gaps
2.4.1 Basic Electrical Characteristics of T-Gate LTPS TFTs with Vacuum Gaps
The method to determinate the threshold voltage (Vth) in this thesis was the constant drain current method that defined as the gate voltage required to achieve a normalized drain current of ID = (W/L)×10-8 A at |VD| = 0.1 V. The equivalent field effect mobility was extracted from the maximum transconductance in the linear region of ID-VG characteristics at |VD| = 0.1 V using the formula:
, where Cox was the gate oxide capacitance per unit area, and the transconductance (gm) is defined as:
V
The on/off current ratio was defined as the ratio of maximum drain current over minimum drain current at |VD| = 3 V. Drain Induced Barrier Lowering (DIBL) was defined as the Vth difference between VD = 0.1 V and 3 V. Substhreshold Swing (SS)
Critical characteristics of the T-Gate TFTs with 400 Å-thick gate oxide were
summarized in Table 2-1. The effects of different height of vacuum gaps were discussed with 1000 Å and 500 Å.
According to Table 2-1, the T-Gate TFTs exhibit superior on/off characteristics which is one order greater than those of conventional structure, especially the T-Gate TFTs with 1000 Å vacuum gap. Meanwhile, the field effect mobility was almost non-changed between T-Gate and conventional TFTs. The weaker substhreshold swing (SS) is caused from the little loss of gate controllability of T-shaped-gate structure. The transfer characteristics of n-channel T-Gate LTPS TFTs with channel length of 5 μm and channel width of 10 μm, and gate oxide thickness of 400 Å was shown in Fig 2-14.
Aside from the improvement of on/off ratio, the maximum leakage current (i.e.
drain current at VG = -15 V) has a dramatic improvement drop by applying the T-Gate structure. Take the T-Gate TFTs with 400 Å-thick gate oxide for example, the maximum leakage current of T-Gate TFTs with 1000 Å-thick vacuum gaps is 6.31×10-11 A, and that of conventional TFTs is 1.81×10-8 A. Also, it can be observed that the T-Gate TFTs with thicker vacuum gaps have the lower leakage current.
The leakage current at large gate bias of LTPS TFTs could be attributed to the high electric field near the drain junction. By applying the T-shaped-gate structure, the maximum electric field near the drain can be effectively decreased from the vacuum gaps. These have been already confirmed by the simulation results in the former chapter. Thus, the magnitude of leakage current in large gate bias (-15 V) can be suppressed three orders in comparison with those conventional TFTs.
The magnitude of on-state current of T-Gate TFTs with 1000 Å vacuum gaps decayed about 35% in comparison with the conventional TFTs at the high gate bias (15 V). Despite of the reduction of driving current, the on/off ratio still enhanced about one order. This was attributed to the dramatic reduction on leakage current.
Similarly, the driving current of T-Gate TFTs with 500 Å vacuum gap decayed about 25% in comparison with the conventional ones at the high gate bias of 15 V.
Figure 2-15 shows the output characteristics of T-Gate and conventional TFTs with channel length of 5 μm, channel width of 10 μm, and gate oxide of 400 Å, respectively. We can observe that the kink effect was sufficiently suppressed by T-Gate TFTs as compared to the conventional TFTs under the same bias condition.
The phenomenon of impact ionization at the drain junction is the reason for the occurrence of kink current at large drain bias. The simulation results in former chapter pointed that impact ionization coefficient of T-Gate TFTs is much lower than the conventional ones. Consequently, the kink effect can be suppressed by T-Gate structure.
In this work, T-Gate TFTs were prepared with two different oxide thicknesses in which were 400 Å and 800 Å. The transfer characteristics of these two kinds of T-Gate TFTs are shown in Figs. 2-28 and 2-29, respectively. The channel width and channel length were 10 μm and 5 μm. Tvacuum and Lsub-gate were fixed at 1000 Å and 2500 Å, respectively. The leakage current as well as the driving current at large gate bias (i.e. at VG = -15 V and 15 V) are listed at Table 2-2. A better outcome of leakage current reduction is observed in the T-Gate TFTs with thinner gate insulator (i.e. 400 Å) in comparison with the thicker one (i.e. 800 Å). Fig. 2-30 and Fig. 2-31 are the schematic illustrations of the equivalent structure of T-Gate TFTs in which the thickness of gate oxide are 400 Å and 800 Å, respectively. The equivalent oxide thickness at the gate edge of T-Gate TFTs with 400 Å gate oxide is 4400 Å in which is 11 times the thickness of the conventional TFTs. As to the T-Gate TFTs with 800 Å gate oxide, only 6 times is observed. This conclusion is consisted with the simulation result mentioned in section 2.3.
NH3 plasma passivation. Because NH3 plasma can passivate the dangling bonds at the poly-Si/SiO2 interface and the trap-states of the poly-Si film, all the electrical characteristics can be improved. The electrical characteristics are listed in Table 2-3.
2.4.2 Series Resistance Analyses of T-Gate LTPS TFTs with Vacuum Gaps
In this study, the series resistances (Rseries) accompanied with the offset-region resistance (Roffset) were extracted from device characteristics directly. It is well known that the turn-on resistance (RON) for devices operation in linear region can be express as:
, where Rchannel and Rseries represented the channel resistance and the series resistance, respectively, the channel resistance in the linear region can be given approximately by:
, where Cox was the capacitance per unit area, W, L, and Vth were the intrinsic channel width, length, and threshold voltage, respectively. Vth is defined, for devices with long channel length. With characteristics of devices with different channel length, the series resistance Rseries can be extracted by plotting turn-on resistance (RON) versus channel length (L) at VD = 0.1 V [2.5]-[2.6].
As shown in Figs. 2-20, 2-21 and 2-22, the extracted series resistance of conventional TFTs is 5.63k ohm. The series resistance of T-Gate TFTs with Tvccuum =
1000 Å and Tvccuum = 500 Å were 9.86k ohm and 9.22k ohm, respectively.
The difference of series resistance between the proposed T-Gate TFTs and conventional TFTs is only the influence of offset region in the T-Gate TFTs. In the proposed T-Gate TFTs, the offset region provide an additional series resistance beside the conventional parasitic resistance including spreading resistance, sheet resistance, and contact resistance along the current path. Therefore the resistance resulting form the offset region (Roffset) of T-Gate TFTs can be expressed as:
) . ( )
(T GateTFTs R ConvTFTs R
Roffset = series − − series ………….…..….(6)
, where Roffset was the series resistance that results from the offset region in T-Gate TFTs, Rseries (T-Gate TFTs), Rseries (Conv. TFTs),were the series resistance of T-Gate TFTs and Conv. TFTs with the same device dimension.
According to equation (6), for low drain bias (VD = 0.1 V) the series resistance of offset region (Roffset) has a value of about 4.23k ohm for Tvccuum = 1000 Å T-Gate TFTs and about 3.59k ohm for Tvccuum = 500 Å T-Gate TFTs.
The larger Roffset value of T-Gate TFTs with Tvccuum = 1000 Å than those with Tvccuum = 500 Å was observed. In the T-Gate TFTs, the vacuum serves as the equivalent 3.9 times thicker oxide. As the vacuum gap is higher, the equivalent oxide thickness is thicker. For the 400 Å-thick gate insulator T-Gate TFTs with 1000 Å- and 500 Å-height vacuum gaps, the equivalent oxide thickness at the gate edge was 4400 Å and 2400 Å, respectively. When MOSFET operated in the on-state, the thicker gate insulator induces less inversion carrier. Therefore, the T-Gate TFTs with 1000 Å vacuum gaps had less inversion carrier in the offset region compared to those with 500 Å vacuum gaps, so that the T-Gate TFTs with with 1000 Å vacuum gaps have a larger Roffset in on-state. This observation is consisted with the transfer characteristics of T-Gate TFTs as shown in Fig.2-14.
2.4.3 Symmetry of Electrical Characteristics of T-Gate LTPS TFTs with Vacuum Gaps
The symmetry of electrical characteristics is discussed to verify the ITO side etching step is a self-aligned process. Figure 2-26 is the schematic illustration of definition of the forward-mode and reverse-mode measurement. There are two possibilities to cause the deviation between forward mode and the reverse mode measurement. One is the asymmetry of side etching of ITO thin film; the other is the grain uniformity variation. Figure 2-27 shows the transfer characteristic of T-Gate TFTs without NH3 plasma passivation. It is observed that the measured drain current has a difference between forward mode and the reverse mode measurement, especially the leakage current at the small gate bias. The driving current and the leakage current at the large gate bias are almost the same in these two measurement modes. The leakage current in poly-Si TFTs at small gate bias is via thermionic emission [2.17]-[2.19], and is dominated by trap density of poly-Si film.
Consequently, the leakage current difference between these two modes may be arising form the grain uniformity variation.
To further affirm the asymmetry of electrical characteristic, the statistical
To further affirm the asymmetry of electrical characteristic, the statistical